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GET /api/patches/2225478/?format=api
{ "id": 2225478, "url": "http://patchwork.ozlabs.org/api/patches/2225478/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421051346.41106-20-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421051346.41106-20-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2026-04-21T05:13:28", "name": "[19/37] fpu: Add scalbn argument to fp8 conversion routines", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a58b17f3f8af7428fd1dee689c6508cb48c90cd6", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421051346.41106-20-richard.henderson@linaro.org/mbox/", "series": [ { "id": 500729, "url": "http://patchwork.ozlabs.org/api/series/500729/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500729", "date": "2026-04-21T05:13:11", "name": "target/arm: Implement FEAT_FAMINMAX, FEAT_FPMR, FEAT_FP8", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500729/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225478/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225478/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Imjm8jdd;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g09ft5SKrz1yHB\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 21 Apr 2026 15:20:38 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wF3Sc-0000X5-Tz; Tue, 21 Apr 2026 01:15:46 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wF3Rf-00084c-If\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:14:51 -0400", "from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wF3RZ-0006Xw-Db\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:14:47 -0400", "by mail-pj1-x102f.google.com with SMTP id\n 98e67ed59e1d1-35da9c0c007so3538252a91.2\n for <qemu-devel@nongnu.org>; Mon, 20 Apr 2026 22:14:38 -0700 (PDT)", "from stoup.. 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"<20260421051346.41106-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::102f;\n envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "All Arm fp8 conversions have a power-of-2 scaling factor.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n include/fpu/softfloat.h | 16 ++++++++++------\n fpu/softfloat.c | 35 +++++++++++++++++++++--------------\n 2 files changed, 31 insertions(+), 20 deletions(-)", "diff": "diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h\nindex 8389a07b04..6f86848b7e 100644\n--- a/include/fpu/softfloat.h\n+++ b/include/fpu/softfloat.h\n@@ -195,13 +195,17 @@ float128 uint128_to_float128(Int128, float_status *status);\n \n float8_e4m3 float4_e2m1_to_float8_e4m3(float4_e2m1, float_status *status);\n \n-bfloat16 float8_e4m3_to_bfloat16(float8_e4m3, float_status *status);\n-float8_e4m3 bfloat16_to_float8_e4m3(bfloat16, bool sat, float_status *status);\n-float8_e4m3 float32_to_float8_e4m3(float32, bool sat, float_status *status);\n+bfloat16 float8_e4m3_to_bfloat16(float8_e4m3, int scale, float_status *status);\n+float8_e4m3 bfloat16_to_float8_e4m3(bfloat16, int scale,\n+ bool sat, float_status *status);\n+float8_e4m3 float32_to_float8_e4m3(float32, int scale,\n+ bool sat, float_status *status);\n \n-bfloat16 float8_e5m2_to_bfloat16(float8_e5m2, float_status *status);\n-float8_e5m2 bfloat16_to_float8_e5m2(bfloat16, bool sat, float_status *status);\n-float8_e5m2 float32_to_float8_e5m2(float32, bool sat, float_status *status);\n+bfloat16 float8_e5m2_to_bfloat16(float8_e5m2, int scale, float_status *status);\n+float8_e5m2 bfloat16_to_float8_e5m2(bfloat16, int scale,\n+ bool sat, float_status *status);\n+float8_e5m2 float32_to_float8_e5m2(float32, int scale,\n+ bool sat, float_status *status);\n \n /*----------------------------------------------------------------------------\n | Software half-precision conversion routines.\ndiff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex 91c34307c8..bcec7d38c8 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -2853,7 +2853,8 @@ static void parts_float_to_ahp(FloatParts64 *a, float_status *s)\n }\n }\n \n-static void parts_float_to_e5m2(FloatParts64 *a, float_status *s, bool saturate)\n+static void parts_float_to_e5m2(FloatParts64 *a, float_status *s,\n+ int scale, bool saturate)\n {\n switch (a->cls) {\n case float_class_snan:\n@@ -2873,8 +2874,10 @@ static void parts_float_to_e5m2(FloatParts64 *a, float_status *s, bool saturate)\n \n case float_class_denormal:\n float_raise(float_flag_input_denormal_used, s);\n- break;\n+ /* fall through */\n case float_class_normal:\n+ a->exp += MIN(MAX(scale, -0x7f), 0x7f);\n+ break;\n case float_class_zero:\n break;\n default:\n@@ -2955,21 +2958,21 @@ float8_e4m3 float4_e2m1_to_float8_e4m3(float4_e2m1 a, float_status *s)\n return float8_e4m3_round_pack_canonical(&p, s, false);\n }\n \n-bfloat16 float8_e4m3_to_bfloat16(float8_e4m3 a, float_status *s)\n+bfloat16 float8_e4m3_to_bfloat16(float8_e4m3 a, int scale, float_status *s)\n {\n FloatParts64 p;\n \n float8_e4m3_unpack_canonical(&p, a, s);\n- parts_float_to_float(&p, s);\n+ parts_scalbn(&p, scale, s);\n return bfloat16_round_pack_canonical(&p, s);\n }\n \n-bfloat16 float8_e5m2_to_bfloat16(float8_e5m2 a, float_status *s)\n+bfloat16 float8_e5m2_to_bfloat16(float8_e5m2 a, int scale, float_status *s)\n {\n FloatParts64 p;\n \n float8_e5m2_unpack_canonical(&p, a, s);\n- parts_float_to_float(&p, s);\n+ parts_scalbn(&p, scale, s);\n return bfloat16_round_pack_canonical(&p, s);\n }\n \n@@ -2993,21 +2996,23 @@ float64 float16_to_float64(float16 a, bool ieee, float_status *s)\n return float64_round_pack_canonical(&p, s);\n }\n \n-float8_e4m3 float32_to_float8_e4m3(float32 a, bool saturate, float_status *s)\n+float8_e4m3 float32_to_float8_e4m3(float32 a, int scale,\n+ bool saturate, float_status *s)\n {\n FloatParts64 p;\n \n float32_unpack_canonical(&p, a, s);\n- parts_float_to_float(&p, s);\n+ parts_scalbn(&p, scale, s);\n return float8_e4m3_round_pack_canonical(&p, s, saturate);\n }\n \n-float8_e5m2 float32_to_float8_e5m2(float32 a, bool saturate, float_status *s)\n+float8_e5m2 float32_to_float8_e5m2(float32 a, int scale,\n+ bool saturate, float_status *s)\n {\n FloatParts64 p;\n \n float32_unpack_canonical(&p, a, s);\n- parts_float_to_e5m2(&p, s, saturate);\n+ parts_float_to_e5m2(&p, s, scale, saturate);\n return float8_e5m2_round_pack_canonical(&p, s, saturate);\n }\n \n@@ -3078,21 +3083,23 @@ float32 float64_to_float32(float64 a, float_status *s)\n return float32_round_pack_canonical(&p, s);\n }\n \n-float8_e4m3 bfloat16_to_float8_e4m3(bfloat16 a, bool saturate, float_status *s)\n+float8_e4m3 bfloat16_to_float8_e4m3(bfloat16 a, int scale,\n+ bool saturate, float_status *s)\n {\n FloatParts64 p;\n \n bfloat16_unpack_canonical(&p, a, s);\n- parts_float_to_float(&p, s);\n+ parts_scalbn(&p, scale, s);\n return float8_e4m3_round_pack_canonical(&p, s, saturate);\n }\n \n-float8_e5m2 bfloat16_to_float8_e5m2(bfloat16 a, bool saturate, float_status *s)\n+float8_e5m2 bfloat16_to_float8_e5m2(bfloat16 a, int scale,\n+ bool saturate, float_status *s)\n {\n FloatParts64 p;\n \n bfloat16_unpack_canonical(&p, a, s);\n- parts_float_to_e5m2(&p, s, saturate);\n+ parts_float_to_e5m2(&p, s, scale, saturate);\n return float8_e5m2_round_pack_canonical(&p, s, saturate);\n }\n \n", "prefixes": [ "19/37" ] }