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{ "id": 2225427, "url": "http://patchwork.ozlabs.org/api/patches/2225427/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/aebpMxWTwGvnmVce@cowardly-lion.the-meissners.org/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<aebpMxWTwGvnmVce@cowardly-lion.the-meissners.org>", "list_archive_url": null, "date": "2026-04-21T03:04:19", "name": "GCC 17.0 PowerPC patches V6 [PATCH 5/5]: Add paddis support.", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5aa8eeac69a73a970805cc2c756f67a3abf593c4", "submitter": { "id": 73991, "url": "http://patchwork.ozlabs.org/api/people/73991/?format=api", "name": "Michael Meissner", "email": "meissner@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/aebpMxWTwGvnmVce@cowardly-lion.the-meissners.org/mbox/", "series": [ { "id": 500719, "url": "http://patchwork.ozlabs.org/api/series/500719/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=500719", "date": "2026-04-21T03:04:19", "name": "GCC 17.0 PowerPC patches V6 [PATCH 5/5]: Add paddis support.", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500719/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225427/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225427/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=Ec4QhDkp;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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a=rsa-sha256; d=sourceware.org; s=key; t=1776740678; cv=none;\n b=oQRMxpeZAs15QlR1EIdXb93aVfJWmiC4N7Jia2/Mj3Cr03GeAo4Tv5KQapcMtymazhP1PhlqAbIf+jBjWipAjXAwqa3kJ9l5ABC6DbV1PFcTNmkvN+w7OcdqyNo0g45s24gjVCt3qxvnfzM1uugsdKsGWl+t0NF2WRnNmHlPn7A=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1776740678; c=relaxed/simple;\n bh=1XF7gVxxuige9d2eDiAYmVatVC0Ad5cvIkwoqVswa0A=;\n h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version;\n b=gbo6Os2XvBgUFVOTbjBBLBL9oLu6rUYWH+9u6Z7uxxkZPdQECCC2hSnNZLfG3tkEsAKLLk7wPruYAMVk5Ov/8Drf7NSbOpwxXFyr3FpKcbemxKDVY9atfLn3T3s8z60jq7wzSXJQrPJ5ZTwLCNL2OsbrPdgFh1NPlj5UC6UalrM=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=\n content-type:date:from:in-reply-to:message-id:mime-version\n :references:subject:to; s=pp1; bh=x/yXVgAOsgm4coTw1KeO4bl52UROFU\n q7V4F/n7pyEPo=; b=Ec4QhDkpaqLoBpiex4hNfer0tOBh9rCXgubjSZySqabvTy\n qXJRM4d5CE8okRSfFKaPh8fiIViTyMpa0gVmJ384torP+8v6cO/JokjH0AoFoIyF\n AB/IaLKxkBYiRz4yXgjxpZYd+pX45Yijz7ta4u/mz9kUZwO5PvzMVJDOWtt1v1Cd\n lso+O6GP8CQCChfYceDZ2epm1NKGfGJHYSoto68hPd7kkbZeIr0C1w6uP4Ks3qQM\n ipJxmXfo7uD0W1tQFn8OkZF9UtC1lVZ7x6RXj81SsmXs9VBavb1lJJAfZr5titzp\n kOmVmz4Ir+wOERM9CWOLwQGC9yy3vdpCKsE5dpUA==", "Date": "Mon, 20 Apr 2026 23:04:19 -0400", "From": "Michael Meissner <meissner@linux.ibm.com>", "To": "Michael Meissner <meissner@linux.ibm.com>, gcc-patches@gcc.gnu.org,\n Segher Boessenkool <segher@kernel.crashing.org>,\n jeevitha <jeevitha@linux.ibm.com>,\n Surya Kumari Jangala <jskumari@linux.ibm.com>,\n Kishan Parmar <kishan@linux.ibm.com>,\n Avinash Jayakar <avinashd@linux.ibm.com>,\n Ayappan Perumal <ayappap2@in.ibm.com>,\n Juergen Christ <jchrist@linux.ibm.com>", "Subject": "GCC 17.0 PowerPC patches V6 [PATCH 5/5]: Add paddis support.", "Message-ID": "<aebpMxWTwGvnmVce@cowardly-lion.the-meissners.org>", "Mail-Followup-To": "Michael Meissner <meissner@linux.ibm.com>,\n gcc-patches@gcc.gnu.org,\n Segher Boessenkool <segher@kernel.crashing.org>,\n jeevitha <jeevitha@linux.ibm.com>,\n Surya Kumari Jangala <jskumari@linux.ibm.com>,\n Kishan Parmar <kishan@linux.ibm.com>,\n Avinash Jayakar <avinashd@linux.ibm.com>,\n Ayappan Perumal <ayappap2@in.ibm.com>,\n Juergen Christ <jchrist@linux.ibm.com>", "References": "<aebT1QQbPenBOFeH@cowardly-lion.the-meissners.org>\n <aebmUidtQeOwvHIY@cowardly-lion.the-meissners.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=us-ascii", "Content-Disposition": "inline", "In-Reply-To": "<aebmUidtQeOwvHIY@cowardly-lion.the-meissners.org>", "X-TM-AS-GCONF": "00", "X-Proofpoint-GUID": "ZV09kMki14FGdbXqPAH3FDAfziZFiYcN", "X-Proofpoint-ORIG-GUID": "ZV09kMki14FGdbXqPAH3FDAfziZFiYcN", "X-Authority-Analysis": "v=2.4 cv=VP7tWdPX c=1 sm=1 tr=0 ts=69e6e944 cx=c_pps\n a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17\n a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=mDV3o1hIAAAA:8\n a=VnNF1IyMAAAA:8 a=R5kucAZ_kg4dczVn-TsA:9 a=CjuIK1q_8ugA:10 a=O8hF6Hzn-FEA:10", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIxMDAyNiBTYWx0ZWRfX/+Q0lv6mPU5v\n USWwvdOwI+ybZwe47glBFeGOaw5Erskricpqi6ZCauuww/ju2dTYvhmQELyIzrJTsnGIN+7qym2\n eha5GSUYB51yJrGBaP0N3McUrFbmrb8M9lQ86LKFwhDgcQblsJwIschEiKULOLDtnD0YBoNg097\n 5kbrQuRTSY0O4t4vGs5FikLuaHiZ+EolFrEc50JQaunXUPaVqMl9+eKGLMtDL3xhJKrQkzbNNTg\n OnM47VIqga9k8I8gdi5/vn1CmAu+K7l03Ltm4Hzhw+JYo2KW1PkTBhKKOADvQIlIgZkzLv7SdTT\n vFR+Ze+phVk3QHYkS95HAllc639tBYolxL77lPG+apDthVmXF+RDTkXdx2gqEaRN28zhZaJ0pZs\n Ave2/xQe3HliS9eByRBtnYezClhl+C7X7bYFTAaulqq9l8AvvApMYgjKpCkE6UdI5pC/Nw/GuxG\n KmqLaWl0zblG6oewECg==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-20_05,2026-04-20_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n clxscore=1015 impostorscore=0 suspectscore=0 priorityscore=1501 adultscore=0\n spamscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 malwarescore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604210026", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "This patch adds support for the paddis instruction that might be added to a\nfuture PowerPC processor.\n\nThis patch needs the -mcpu=future patch posted on April 8th, 2026:\n\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/712532.html\n\nI have built bootstrap little endian compilers on power10 systems, and\nbig endian compiler on power9 systems. There were no regression in the\ntests. Can I add the patches to the GCC trunk after the -mcpu=future\npatch is applied and GCC 17 has opened up?\n\ngcc/\n\n2026-04-20 Michael Meissner <meissner@linux.ibm.com>\n\n\t* config/rs6000/constraints.md (eU): New constraint.\n\t(eV): Likewise.\n\t* config/rs6000/predicates.md (paddis_operand): New predicate.\n\t(paddis_paddi_operand): Likewise.\n\t(add_operand): Add paddis support.\n\t* config/rs6000/rs6000.cc (num_insns_constant_gpr): Add paddis support.\n\t(num_insns_constant_multi): Likewise.\n\t(print_operand): Add %B<n> for paddis support.\n\t* config/rs6000/rs6000.h (TARGET_PADDIS): New macro.\n\t(SIGNED_INTEGER_32BIT_P): Likewise.\n\t* config/rs6000/rs6000.md (isa attribute): Add paddis support.\n\t(enabled attribute); Likewise.\n\t(add<mode>3): Likewise.\n\t(adddi3 splitter): New splitter for paddis.\n\t(movdi_internal64): Add paddis support.\n\t(movdi splitter): New splitter for paddis.\n\ngcc/testsuite/\n\n2026-04-20 Michael Meissner <meissner@linux.ibm.com>\n\n\t* gcc.target/powerpc/prefixed-addis.c: New test.\n---\n gcc/config/rs6000/constraints.md | 10 ++\n gcc/config/rs6000/predicates.md | 52 +++++++++-\n gcc/config/rs6000/rs6000.cc | 24 +++++\n gcc/config/rs6000/rs6000.h | 4 +\n gcc/config/rs6000/rs6000.md | 96 ++++++++++++++++---\n .../gcc.target/powerpc/prefixed-addis.c | 24 +++++\n 6 files changed, 196 insertions(+), 14 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/powerpc/prefixed-addis.c", "diff": "diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md\nindex 0d1cde5bd4d..a755fb31df8 100644\n--- a/gcc/config/rs6000/constraints.md\n+++ b/gcc/config/rs6000/constraints.md\n@@ -222,6 +222,16 @@ (define_constraint \"eQ\"\n \"An IEEE 128-bit constant that can be loaded into VSX registers.\"\n (match_operand 0 \"easy_vector_constant_ieee128\"))\n \n+(define_constraint \"eU\"\n+ \"@internal integer constant that can be loaded with paddis\"\n+ (and (match_code \"const_int\")\n+ (match_operand 0 \"paddis_operand\")))\n+\n+(define_constraint \"eV\"\n+ \"@internal integer constant that can be loaded with paddis + paddi\"\n+ (and (match_code \"const_int\")\n+ (match_operand 0 \"paddis_paddi_operand\")))\n+\n ;; Floating-point constraints. These two are defined so that insn\n ;; length attributes can be calculated exactly.\n \ndiff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md\nindex 8221e0fa2d0..6a6eb4f3653 100644\n--- a/gcc/config/rs6000/predicates.md\n+++ b/gcc/config/rs6000/predicates.md\n@@ -378,6 +378,53 @@ (define_predicate \"cint34_operand\"\n return SIGNED_INTEGER_34BIT_P (INTVAL (op));\n })\n \n+;; Return 1 if op is a 64-bit constant that uses the paddis instruction\n+(define_predicate \"paddis_operand\"\n+ (match_code \"const_int\")\n+{\n+ if (!TARGET_PADDIS && TARGET_POWERPC64)\n+ return 0;\n+\n+ /* If addi, addis, or paddi can handle the number, don't return true. */\n+ HOST_WIDE_INT value = INTVAL (op);\n+ if (SIGNED_INTEGER_34BIT_P (value))\n+ return false;\n+\n+ /* If the number is too large for padds, return false. */\n+ if (!SIGNED_INTEGER_32BIT_P (value >> 32))\n+ return false;\n+\n+ /* If the bottom 32-bits are non-zero, paddis can't handle it. */\n+ if ((value & HOST_WIDE_INT_C(0xffffffff)) != 0)\n+ return false;\n+\n+ return true;\n+})\n+\n+;; Return 1 if op is a 64-bit constant that needs the paddis instruction and an\n+;; addi/addis/paddi instruction combination.\n+(define_predicate \"paddis_paddi_operand\"\n+ (match_code \"const_int\")\n+{\n+ if (!TARGET_PADDIS && TARGET_POWERPC64)\n+ return 0;\n+\n+ /* If addi, addis, or paddi can handle the number, don't return true. */\n+ HOST_WIDE_INT value = INTVAL (op);\n+ if (SIGNED_INTEGER_34BIT_P (value))\n+ return false;\n+\n+ /* If the number is too large for padds, return false. */\n+ if (!SIGNED_INTEGER_32BIT_P (value >> 32))\n+ return false;\n+\n+ /* If the bottom 32-bits are zero, we can use paddis alone to handle it. */\n+ if ((value & HOST_WIDE_INT_C(0xffffffff)) == 0)\n+ return false;\n+\n+ return true;\n+})\n+\n ;; Return 1 if op is a register that is not special.\n ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where\n ;; you need to be careful in moving a SFmode to SImode and vice versa due to\n@@ -1122,7 +1169,10 @@ (define_predicate \"add_operand\"\n (if_then_else (match_code \"const_int\")\n (match_test \"satisfies_constraint_I (op)\n \t\t || satisfies_constraint_L (op)\n-\t\t || satisfies_constraint_eI (op)\")\n+\t\t || satisfies_constraint_eI (op)\n+\t\t || satisfies_constraint_eU (op)\n+\t\t || satisfies_constraint_eV (op)\")\n+\n (match_operand 0 \"gpc_reg_operand\")))\n \n ;; Return 1 if the operand is either a non-special register, or 0, or -1.\ndiff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc\nindex f0446ac9b44..bb65320e321 100644\n--- a/gcc/config/rs6000/rs6000.cc\n+++ b/gcc/config/rs6000/rs6000.cc\n@@ -6167,6 +6167,14 @@ num_insns_constant_gpr (HOST_WIDE_INT value)\n else if (TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P (value))\n return 1;\n \n+ /* PADDIS support. */\n+ else if (TARGET_PADDIS && TARGET_POWERPC64\n+\t && !IN_RANGE (value >> 32, -1, 0)\n+\t && (SIGNED_INTEGER_32BIT_P (value >> 32)))\n+ return ((value & HOST_WIDE_INT_C (0xffffffff)) == 0\n+\t ? 1\n+\t : 2);\n+\n else if (TARGET_POWERPC64)\n {\n int num_insns = 0;\n@@ -6187,6 +6195,14 @@ num_insns_constant_multi (HOST_WIDE_INT value, machine_mode mode)\n {\n int nregs = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;\n int total = 0;\n+ if (nregs == 1\n+ && TARGET_PADDIS && TARGET_POWERPC64\n+ && !IN_RANGE (value >> 32, -1, 0)\n+ && SIGNED_INTEGER_32BIT_P (value >> 32))\n+ return ((value & HOST_WIDE_INT_C (0xffffffff)) == 0\n+\t ? 1\n+\t : 2);\n+\n while (nregs-- > 0)\n {\n HOST_WIDE_INT low = sext_hwi (value, BITS_PER_WORD);\n@@ -14277,6 +14293,14 @@ print_operand (FILE *file, rtx x, int code)\n \tfprintf (file, \"%d\", (REGNO (x) - FIRST_FPR_REGNO) / 4);\n return;\n \n+ case 'B':\n+ /* Upper 32-bits of a constant. */\n+ if (!CONST_INT_P (x))\n+\toutput_operand_lossage (\"Not a constant.\");\n+\n+ fprintf (file, \"%\" HOST_LONG_FORMAT \"d\", INTVAL (x) >> 32);\n+ return;\n+\n case 'D':\n /* Like 'J' but get to the GT bit only. */\n if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))\ndiff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h\nindex f4c4060564e..88a8717a9d8 100644\n--- a/gcc/config/rs6000/rs6000.h\n+++ b/gcc/config/rs6000/rs6000.h\n@@ -570,6 +570,9 @@ extern int rs6000_vector_align[];\n /* Whether we have XVRLW support. */\n #define TARGET_XVRLW\t\t\tTARGET_FUTURE\n \n+/* Whether we have PADDIS support. */\n+#define TARGET_PADDIS\t\t\tTARGET_FUTURE\n+\n /* Whether the various reciprocal divide/square root estimate instructions\n exist, and whether we should automatically generate code for the instruction\n by default. */\n@@ -2487,6 +2490,7 @@ typedef struct GTY(()) machine_function\n \t (HOST_WIDE_INT_1 << ((N)-1)) - 1)\n \n #define SIGNED_INTEGER_16BIT_P(VALUE)\tSIGNED_INTEGER_NBIT_P (VALUE, 16)\n+#define SIGNED_INTEGER_32BIT_P(VALUE)\tSIGNED_INTEGER_NBIT_P (VALUE, 32)\n #define SIGNED_INTEGER_34BIT_P(VALUE)\tSIGNED_INTEGER_NBIT_P (VALUE, 34)\n \n /* Like SIGNED_INTEGER_16BIT_P and SIGNED_INTEGER_34BIT_P, but with an extra\ndiff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md\nindex 199a95b84c4..1c1c4ef5779 100644\n--- a/gcc/config/rs6000/rs6000.md\n+++ b/gcc/config/rs6000/rs6000.md\n@@ -371,7 +371,7 @@ (define_attr \"cpu\"\n (const (symbol_ref \"(enum attr_cpu) rs6000_tune\")))\n \n ;; The ISA we implement.\n-(define_attr \"isa\" \"any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10\"\n+(define_attr \"isa\" \"any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10,paddis\"\n (const_string \"any\"))\n \n ;; Is this alternative enabled for the current CPU/ISA/etc.?\n@@ -423,6 +423,11 @@ (define_attr \"enabled\" \"\"\n (and (eq_attr \"isa\" \"p10\")\n \t (match_test \"TARGET_POWER10\"))\n (const_int 1)\n+\n+ (and (eq_attr \"isa\" \"paddis\")\n+\t (match_test \"TARGET_PADDIS\"))\n+ (const_int 1)\n+\n ] (const_int 0)))\n \n ;; If this instruction is microcoded on the CELL processor\n@@ -1845,17 +1850,42 @@ (define_expand \"add<mode>3\"\n })\n \n (define_insn \"*add<mode>3\"\n- [(set (match_operand:GPR 0 \"gpc_reg_operand\" \"=r,r,r,r\")\n-\t(plus:GPR (match_operand:GPR 1 \"gpc_reg_operand\" \"%r,b,b,b\")\n-\t\t (match_operand:GPR 2 \"add_operand\" \"r,I,L,eI\")))]\n+ [(set (match_operand:GPR 0 \"gpc_reg_operand\" \"=r,r,r,r,r,b\")\n+\t(plus:GPR (match_operand:GPR 1 \"gpc_reg_operand\" \"%r,b,b,b,b,b\")\n+\t\t (match_operand:GPR 2 \"add_operand\" \"r,I,L,eI,eU,eV\")))]\n \"\"\n \"@\n add %0,%1,%2\n addi %0,%1,%2\n addis %0,%1,%v2\n- addi %0,%1,%2\"\n+ addi %0,%1,%2\n+ paddis %0,%1,%B2\n+ #\"\n [(set_attr \"type\" \"add\")\n- (set_attr \"isa\" \"*,*,*,p10\")])\n+ (set_attr \"isa\" \"*,*,*,p10,paddis,paddis\")\n+ (set_attr \"length\" \"*,*,*,*,12,24\")\n+ (set_attr \"prefixed\" \"*,*,*,*,yes,yes\")\n+ (set_attr \"maybe_prefixed\" \"*,*,*,*,no,no\")])\n+\n+(define_split\n+ [(set (match_operand:DI 0 \"gpc_reg_operand\")\n+\t(plus:DI (match_operand:DI 1 \"gpc_reg_operand\")\n+\t\t (match_operand:DI 2 \"paddis_paddi_operand\")))]\n+ \"TARGET_PADDIS && TARGET_POWERPC64\"\n+ [(set (match_dup 3)\n+\t(plus:DI (match_dup 1)\n+\t\t (match_dup 4)))\n+ (set (match_dup 0)\n+\t(plus:DI (match_dup 3)\n+\t\t (match_dup 5)))]\n+{\n+ HOST_WIDE_INT value = INTVAL (operands[2]);\n+ operands[3] = (can_create_pseudo_p ()\n+\t\t ? gen_reg_rtx (DImode)\n+\t\t : operands[0]);\n+ operands[4] = GEN_INT (value & ~HOST_WIDE_INT_C (0xffffffff));\n+ operands[5] = GEN_INT (value & HOST_WIDE_INT_C (0xffffffff));\n+})\n \n (define_insn \"*addsi3_high\"\n [(set (match_operand:SI 0 \"gpc_reg_operand\" \"=b\")\n@@ -9878,7 +9908,7 @@ (define_split\n DONE;\n })\n \n-;;\t GPR store GPR load GPR move\n+;;\t GPR store GPR load GPR move GPR paddis GPR paddis+paddi\n ;;\t GPR li GPR lis GPR pli GPR #\n ;;\t FPR store FPR load FPR move\n ;;\t AVX store AVX store AVX load AVX load VSX move\n@@ -9888,7 +9918,7 @@ (define_split\n ;;\t VSX->GPR GPR->VSX\n (define_insn \"*movdi_internal64\"\n [(set (match_operand:DI 0 \"nonimmediate_operand\"\n-\t \"=YZ, r, r,\n+\t \"=YZ, r, r, r, b,\n \t r, r, r, r,\n \t m, ^d, ^d,\n \t wY, Z, $v, $v, ^wa,\n@@ -9897,7 +9927,7 @@ (define_insn \"*movdi_internal64\"\n \t r, *h, *h,\n \t ?r, ?wa\")\n \t(match_operand:DI 1 \"input_operand\"\n-\t \"r, YZ, r,\n+\t \"r, YZ, r, eU, eV,\n \t I, L, eI, nF,\n \t ^d, m, ^d,\n \t ^v, $v, wY, Z, ^wa,\n@@ -9912,6 +9942,8 @@ (define_insn \"*movdi_internal64\"\n std%U0%X0 %1,%0\n ld%U1%X1 %0,%1\n mr %0,%1\n+ paddis %0,0,%B1\n+ #\n li %0,%1\n lis %0,%v1\n li %0,%1\n@@ -9937,7 +9969,7 @@ (define_insn \"*movdi_internal64\"\n mfvsrd %0,%x1\n mtvsrd %x0,%1\"\n [(set_attr \"type\"\n-\t \"store, load, *,\n+\t \"store, load, *, *, *,\n \t *, *, *, *,\n \t fpstore, fpload, fpsimple,\n \t fpstore, fpstore, fpload, fpload, veclogical,\n@@ -9947,7 +9979,7 @@ (define_insn \"*movdi_internal64\"\n \t mfvsr, mtvsr\")\n (set_attr \"size\" \"64\")\n (set_attr \"length\"\n-\t \"*, *, *,\n+\t \"*, *, *, 12, 24,\n \t *, *, *, 20,\n \t *, *, *,\n \t *, *, *, *, *,\n@@ -9956,14 +9988,32 @@ (define_insn \"*movdi_internal64\"\n \t *, *, *,\n \t *, *\")\n (set_attr \"isa\"\n-\t \"*, *, *,\n+\t \"*, *, *, paddis, paddis,\n \t *, *, p10, *,\n \t *, *, *,\n \t p9v, p7v, p9v, p7v, *,\n \t p9v, p9v, p7v, *, *,\n \t p7v, p7v,\n \t *, *, *,\n-\t p8v, p8v\")])\n+\t p8v, p8v\")\n+ (set_attr \"prefixed\"\n+\t \"*, *, *, yes, yes,\n+\t *, *, *, *,\n+\t *, *, *,\n+\t *, *, *, *, *,\n+\t *, *, *, *, *,\n+\t *, *,\n+\t *, *, *,\n+\t *, *\")\n+ (set_attr \"maybe_prefixed\"\n+\t \"*, *, *, no, no,\n+\t *, *, *, *,\n+\t *, *, *,\n+\t *, *, *, *, *,\n+\t *, *, *, *, *,\n+\t *, *,\n+\t *, *, *,\n+\t *, *\")])\n \n ; Some DImode loads are best done as a load of -1 followed by a mask\n ; instruction.\n@@ -9981,6 +10031,26 @@ (define_split\n \t\t(match_dup 1)))]\n \"\")\n \n+;; Split a constant that can be generated by a paddis and paddi into 2\n+;; instructions.\n+(define_split\n+ [(set (match_operand:DI 0 \"int_reg_operand\")\n+\t(match_operand:DI 1 \"paddis_paddi_operand\"))]\n+ \"TARGET_PADDIS && TARGET_POWERPC64\"\n+ [(set (match_dup 2)\n+\t(match_dup 3))\n+ (set (match_dup 0)\n+\t(plus:DI (match_dup 2)\n+\t\t (match_dup 4)))]\n+{\n+ HOST_WIDE_INT value = INTVAL (operands[1]);\n+ operands[2] = (can_create_pseudo_p ()\n+\t\t ? gen_reg_rtx (DImode)\n+\t\t : operands[0]);\n+ operands[3] = GEN_INT (value & ~HOST_WIDE_INT_C (0xffffffff));\n+ operands[4] = GEN_INT (value & HOST_WIDE_INT_C (0xffffffff));\n+})\n+\n ;; Split a load of a large constant into the appropriate five-instruction\n ;; sequence. Handle anything in a constant number of insns.\n ;; When non-easy constants can go in the TOC, this should use\ndiff --git a/gcc/testsuite/gcc.target/powerpc/prefixed-addis.c b/gcc/testsuite/gcc.target/powerpc/prefixed-addis.c\nnew file mode 100644\nindex 00000000000..d08e3675f94\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/prefixed-addis.c\n@@ -0,0 +1,24 @@\n+/* { dg-do compile } */\n+/* { dg-require-effective-target powerpc_future_ok } */\n+/* { dg-require-effective-target lp64 } */\n+/* { dg-options \"-mdejagnu-cpu=future -O2\" } */\n+\n+/* Test whether the xvrl (vector word rotate left using VSX registers insead of\n+ Altivec registers is generated. */\n+\n+#include <stddef.h>\n+\n+size_t\n+prefix_addis_addi (size_t x)\n+{\n+ return x + 0x123456789ABCDEUL;\t/* paddis + paddi. */\n+}\n+\n+size_t\n+prefix_addis (size_t x)\n+{\n+ return x + 0x12345600000000UL;\t/* paddis. */\n+}\n+\n+/* { dg-final { scan-assembler-times {\\mpaddis\\M} 2 } } */\n+/* { dg-final { scan-assembler-times {\\mpaddi\\M} 1 } } */\n", "prefixes": [] }