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{ "id": 2225426, "url": "http://patchwork.ozlabs.org/api/patches/2225426/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/aebo1Aht270GpDnU@cowardly-lion.the-meissners.org/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<aebo1Aht270GpDnU@cowardly-lion.the-meissners.org>", "list_archive_url": null, "date": "2026-04-21T03:02:44", "name": "GCC 17.0 PowerPC patches V6 [PATCH 4/5]: Support load/store vector with right length.", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9d421f7e4c8e931a1f3f4b551cda6a9d0487db18", "submitter": { "id": 73991, "url": "http://patchwork.ozlabs.org/api/people/73991/?format=api", "name": "Michael Meissner", "email": "meissner@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/aebo1Aht270GpDnU@cowardly-lion.the-meissners.org/mbox/", "series": [ { "id": 500718, "url": "http://patchwork.ozlabs.org/api/series/500718/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=500718", "date": "2026-04-21T03:02:44", "name": "GCC 17.0 PowerPC patches V6 [PATCH 4/5]: Support load/store vector with right length.", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500718/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225426/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225426/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=WIXYNw62;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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a=rsa-sha256; d=sourceware.org; s=key; t=1776740572; cv=none;\n b=f2QdXPFEQsT5nrtjpJWxfkjihNrFOSMZ6EYAhHYzUFz7PEVVBkF6JwvWipBoT7MeSkKWUCbp/E20opMNHn6I406TWjtEoqiJAzIyIRCFEbyjsyvjYA6PK1FtLj5fnRzuLfOh6MRoeTtXj3ayirq6AsSzqibEtSTDzAc2Q6X912I=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1776740572; c=relaxed/simple;\n bh=cg4l/ZbFg17Ovm0YhKeq7NOaW24GvunjC5XNfLu1enI=;\n h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version;\n b=axMmXwPIvBMpo6kx1dcAGyTyKbmYkz+qa96uZYiWkuuHl5ovtG1p/t/q2Qo78Qfo/14MNrbkvtW2PMOKEek06BfYhX6w9Kw+9LsfOkQ2In25ttjHZJbuszPI3GYEmDwQrkrTs9/5pfZGnGC7cVZPrAFxhGeOXJPHQ/djoBz51Bk=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=\n content-type:date:from:in-reply-to:message-id:mime-version\n :references:subject:to; s=pp1; bh=DrPe+mWe5MFj1fddCxsZwt0IA8fZN+\n DUlLfaVKXp+AA=; b=WIXYNw62bhoOQCiWvhgD8c97RGqM9XuBk404yUEt8yjoYI\n EKHcYIekLUM3/yVJWCgGCCwKloTRXtkbIqWo+oejJ5QeYKcftq1XBLd/my1urCPc\n o/PHoP8JidTYeenWeC/JUjiXAJlYFlg8U/sXuphIkrpJDPfH/+4vf7occadzvG/6\n IBurNPcqxC467DqfN5yJiEVfkmzIRY5buK+8nKBmkERfUy1A1D/AB6zirSGjelAU\n 0AhjYi20B51q4nqHrAueC4I4z2W3SsXkTkaE4CLeTWQXQjBfHQeX6agdjpjPLMj1\n oq/gVgGy0tlEKP1sHIXAM6TZfJ7zRs8U+Jc2qJNA==", "Date": "Mon, 20 Apr 2026 23:02:44 -0400", "From": "Michael Meissner <meissner@linux.ibm.com>", "To": "Michael Meissner <meissner@linux.ibm.com>, gcc-patches@gcc.gnu.org,\n Segher Boessenkool <segher@kernel.crashing.org>,\n jeevitha <jeevitha@linux.ibm.com>,\n Surya Kumari Jangala <jskumari@linux.ibm.com>,\n Kishan Parmar <kishan@linux.ibm.com>,\n Avinash Jayakar <avinashd@linux.ibm.com>,\n Ayappan Perumal <ayappap2@in.ibm.com>,\n Juergen Christ <jchrist@linux.ibm.com>", "Subject": "GCC 17.0 PowerPC patches V6 [PATCH 4/5]: Support load/store vector\n with right length.", "Message-ID": "<aebo1Aht270GpDnU@cowardly-lion.the-meissners.org>", "Mail-Followup-To": "Michael Meissner <meissner@linux.ibm.com>,\n gcc-patches@gcc.gnu.org,\n Segher Boessenkool <segher@kernel.crashing.org>,\n jeevitha <jeevitha@linux.ibm.com>,\n Surya Kumari Jangala <jskumari@linux.ibm.com>,\n Kishan Parmar <kishan@linux.ibm.com>,\n Avinash Jayakar <avinashd@linux.ibm.com>,\n Ayappan Perumal <ayappap2@in.ibm.com>,\n Juergen Christ <jchrist@linux.ibm.com>", "References": "<aebT1QQbPenBOFeH@cowardly-lion.the-meissners.org>\n <aebmUidtQeOwvHIY@cowardly-lion.the-meissners.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=us-ascii", "Content-Disposition": "inline", "In-Reply-To": "<aebmUidtQeOwvHIY@cowardly-lion.the-meissners.org>", "X-TM-AS-GCONF": "00", "X-Proofpoint-GUID": "Pb5yFaUh5UAsj_yUWBzNLBeMfszf1eqA", "X-Proofpoint-ORIG-GUID": "Pb5yFaUh5UAsj_yUWBzNLBeMfszf1eqA", "X-Authority-Analysis": "v=2.4 cv=VP7tWdPX c=1 sm=1 tr=0 ts=69e6e8db cx=c_pps\n a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17\n a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=mDV3o1hIAAAA:8\n a=VnNF1IyMAAAA:8 a=64wFKvqrGctzgdl1C0wA:9 a=CjuIK1q_8ugA:10", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIxMDAyNiBTYWx0ZWRfX7nWetvd9XPPN\n FUMjB/aTilHUYQdyG5xIaBrBLAje8JB0vbZ4M8yEu/g/CdwmkNc1KCQrhcl3whm3xPx9i+T7nmO\n 8j6rieXWjunfSRMLDrsYYo1J1a7CcpitYK7iuJpv2DH2peQ0gERTMqlPPLTT2VzkWtI9G638vNB\n 9POmaQ7XpyaUQ5YbtXQVfvskT9eeA9YC9QhdtAdlEd1Zikk6lc0x3VOshYMWQZGf9kuVLzRVaP9\n 6+KFgOpN9fONV2+kIDPbgaISrWh8whXC4c1BoJoanhvcMhgN29XYiDc+Jg0tAW1eoZcrn9SFjX5\n Px2xyLOA0fxPnXEP+twwvBO1dLfa8bWbXvWngii+49lKUFi9+xNx5PnqTNcxzRzGjThDJwVoB3g\n w6IBwxI8+DaCi00V9d/3iZI8RHeg6Xz0qWum7K6F9HIaS+2JmM+ynlq5qqXDg2JeppZ18Y1U7jj\n dvOyTxCzdR+5XHBTYAQ==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-20_05,2026-04-20_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n clxscore=1015 impostorscore=0 suspectscore=0 priorityscore=1501 adultscore=0\n spamscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 malwarescore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604210026", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "This patch adds support for new instructions that may be added to the PowerPC\narchitecture in the future to enhance the load and store vector with length\ninstructions.\n\nThe current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to use\nsince the count for the number of bytes must be in the top 8 bits of the GPR\nregister, instead of the bottom 8 bits. This meant that code generating these\ninstructions typically had to do a shift left by 56 bits to get the count into\nthe right position. In a future version of the PowerPC architecture, new\nvariants of these instructions might be added that expect the count to be in\nthe bottom 8 bits of the GPR register. These patches add this support to GCC\nif the user uses the -mcpu=future option.\n\nI discovered that the code in rs6000-string.cc to generate ISA 3.1 lxvl/stxvl\nfuture lxvll/stxvll instructions would generate these instructions on 32-bit.\nHowever the patterns for these instructions is only done on 64-bit systems. So\nI added a check for 64-bit support before generating the instructions.\n\nThis patch needs the -mcpu=future patch posted on April 8th, 2026:\n\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/712532.html\n\nI have built bootstrap little endian compilers on power10 systems, and\nbig endian compiler on power9 systems. There were no regression in the\ntests. Can I add the patches to the GCC trunk after the -mcpu=future\npatch is applied and GCC 17 has opened up?\n\ngcc/\n\n2026-04-20 Michael Meissner <meissner@linux.ibm.com>\n\n\t* config/rs6000/rs6000-string.cc (expand_block_move): Do not generate\n\tlxvl and stxvl on 32-bit.\n\t* config/rs6000/vsx.md (lxvl): If -mcpu=future, generate the lxvl with\n\tthe shift count automaticaly used in the insn.\n\t(lxvrl): New insn for -mcpu=future.\n\t(lxvrll): Likewise.\n\t(stxvl): If -mcpu=future, generate the stxvl with the shift count\n\tautomaticaly used in the insn.\n\t(stxvrl): New insn for -mcpu=future.\n\t(stxvrll): Likewise.\n\ngcc/testsuite/\n\n2026-04-20 Michael Meissner <meissner@linux.ibm.com>\n\n\t* gcc.target/powerpc/lxvrl.c: New test.\n---\n gcc/config/rs6000/rs6000-string.cc | 1 +\n gcc/config/rs6000/vsx.md | 122 +++++++++++++++++++----\n gcc/testsuite/gcc.target/powerpc/lxvrl.c | 32 ++++++\n 3 files changed, 134 insertions(+), 21 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/powerpc/lxvrl.c", "diff": "diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc\nindex 35bb259c024..faa6ee049f0 100644\n--- a/gcc/config/rs6000/rs6000-string.cc\n+++ b/gcc/config/rs6000/rs6000-string.cc\n@@ -2786,6 +2786,7 @@ expand_block_move (rtx operands[], bool might_overlap)\n \n if (TARGET_MMA && TARGET_BLOCK_OPS_UNALIGNED_VSX\n \t && TARGET_BLOCK_OPS_VECTOR_PAIR\n+\t && TARGET_POWERPC64\n \t && bytes >= 32\n \t && (align >= 256 || !STRICT_ALIGNMENT))\n \t{\ndiff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md\nindex cfad9b8c6d5..c162467571f 100644\n--- a/gcc/config/rs6000/vsx.md\n+++ b/gcc/config/rs6000/vsx.md\n@@ -5712,20 +5712,32 @@ (define_expand \"first_mismatch_or_eos_index_<mode>\"\n DONE;\n })\n \n-;; Load VSX Vector with Length\n+;; Load VSX Vector with Length. If we have lxvrl, we don't have to do an\n+;; explicit shift left into a pseudo.\n (define_expand \"lxvl\"\n- [(set (match_dup 3)\n- (ashift:DI (match_operand:DI 2 \"register_operand\")\n- (const_int 56)))\n- (set (match_operand:V16QI 0 \"vsx_register_operand\")\n-\t(unspec:V16QI\n-\t [(match_operand:DI 1 \"gpc_reg_operand\")\n- (mem:V16QI (match_dup 1))\n-\t (match_dup 3)]\n-\t UNSPEC_LXVL))]\n+ [(use (match_operand:V16QI 0 \"vsx_register_operand\"))\n+ (use (match_operand:DI 1 \"gpc_reg_operand\"))\n+ (use (match_operand:DI 2 \"gpc_reg_operand\"))]\n \"TARGET_P9_VECTOR && TARGET_64BIT\"\n {\n- operands[3] = gen_reg_rtx (DImode);\n+ rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56));\n+ rtx len;\n+\n+ if (TARGET_FUTURE)\n+ len = shift_len;\n+ else\n+ {\n+ len = gen_reg_rtx (DImode);\n+ emit_insn (gen_rtx_SET (len, shift_len));\n+ }\n+\n+ rtx dest = operands[0];\n+ rtx addr = operands[1];\n+ rtx mem = gen_rtx_MEM (V16QImode, addr);\n+ rtvec rv = gen_rtvec (3, addr, mem, len);\n+ rtx lxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_LXVL);\n+ emit_insn (gen_rtx_SET (dest, lxvl));\n+ DONE;\n })\n \n (define_insn \"*lxvl\"\n@@ -5749,6 +5761,34 @@ (define_insn \"lxvll\"\n \"lxvll %x0,%1,%2\"\n [(set_attr \"type\" \"vecload\")])\n \n+;; For lxvrl and lxvrll, use the combiner to eliminate the shift. The\n+;; define_expand for lxvl will already incorporate the shift in generating the\n+;; insn. The lxvll buitl-in function required the user to have already done\n+;; the shift. Defining lxvrll this way, will optimize cases where the user has\n+;; done the shift immediately before the built-in.\n+(define_insn \"*lxvrl\"\n+ [(set (match_operand:V16QI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V16QI\n+\t [(match_operand:DI 1 \"gpc_reg_operand\" \"b\")\n+\t (mem:V16QI (match_dup 1))\n+\t (ashift:DI (match_operand:DI 2 \"register_operand\" \"r\")\n+\t\t (const_int 56))]\n+\t UNSPEC_LXVL))]\n+ \"TARGET_FUTURE && TARGET_64BIT\"\n+ \"lxvrl %x0,%1,%2\"\n+ [(set_attr \"type\" \"vecload\")])\n+\n+(define_insn \"*lxvrll\"\n+ [(set (match_operand:V16QI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V16QI [(match_operand:DI 1 \"gpc_reg_operand\" \"b\")\n+ (mem:V16QI (match_dup 1))\n+\t\t (ashift:DI (match_operand:DI 2 \"register_operand\" \"r\")\n+\t\t\t\t (const_int 56))]\n+\t\t UNSPEC_LXVLL))]\n+ \"TARGET_FUTURE\"\n+ \"lxvrll %x0,%1,%2\"\n+ [(set_attr \"type\" \"vecload\")])\n+\n ;; Expand for builtin xl_len_r\n (define_expand \"xl_len_r\"\n [(match_operand:V16QI 0 \"vsx_register_operand\")\n@@ -5780,18 +5820,29 @@ (define_insn \"stxvll\"\n \n ;; Store VSX Vector with Length\n (define_expand \"stxvl\"\n- [(set (match_dup 3)\n-\t(ashift:DI (match_operand:DI 2 \"register_operand\")\n-\t\t (const_int 56)))\n- (set (mem:V16QI (match_operand:DI 1 \"gpc_reg_operand\"))\n-\t(unspec:V16QI\n-\t [(match_operand:V16QI 0 \"vsx_register_operand\")\n-\t (mem:V16QI (match_dup 1))\n-\t (match_dup 3)]\n-\t UNSPEC_STXVL))]\n+ [(use (match_operand:V16QI 0 \"vsx_register_operand\"))\n+ (use (match_operand:DI 1 \"gpc_reg_operand\"))\n+ (use (match_operand:DI 2 \"gpc_reg_operand\"))]\n \"TARGET_P9_VECTOR && TARGET_64BIT\"\n {\n- operands[3] = gen_reg_rtx (DImode);\n+ rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56));\n+ rtx len;\n+\n+ if (TARGET_FUTURE)\n+ len = shift_len;\n+ else\n+ {\n+ len = gen_reg_rtx (DImode);\n+ emit_insn (gen_rtx_SET (len, shift_len));\n+ }\n+\n+ rtx src = operands[0];\n+ rtx addr = operands[1];\n+ rtx mem = gen_rtx_MEM (V16QImode, addr);\n+ rtvec rv = gen_rtvec (3, src, mem, len);\n+ rtx stxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_STXVL);\n+ emit_insn (gen_rtx_SET (mem, stxvl));\n+ DONE;\n })\n \n ;; Define optab for vector access with length vectorization exploitation.\n@@ -5836,6 +5887,35 @@ (define_insn \"*stxvl\"\n \"stxvl %x0,%1,%2\"\n [(set_attr \"type\" \"vecstore\")])\n \n+;; For stxvrl and stxvrll, use the combiner to eliminate the shift. The\n+;; define_expand for stxvl will already incorporate the shift in generating the\n+;; insn. The stxvll buitl-in function required the user to have already done\n+;; the shift. Defining stxvrll this way, will optimize cases where the user\n+;; has done the shift immediately before the built-in.\n+\n+(define_insn \"*stxvrl\"\n+ [(set (mem:V16QI (match_operand:DI 1 \"gpc_reg_operand\" \"b\"))\n+\t(unspec:V16QI\n+\t [(match_operand:V16QI 0 \"vsx_register_operand\" \"wa\")\n+\t (mem:V16QI (match_dup 1))\n+\t (ashift:DI (match_operand:DI 2 \"register_operand\" \"r\")\n+\t\t (const_int 56))]\n+\t UNSPEC_STXVL))]\n+ \"TARGET_FUTURE && TARGET_64BIT\"\n+ \"stxvrl %x0,%1,%2\"\n+ [(set_attr \"type\" \"vecstore\")])\n+\n+(define_insn \"*stxvrll\"\n+ [(set (mem:V16QI (match_operand:DI 1 \"gpc_reg_operand\" \"b\"))\n+\t(unspec:V16QI [(match_operand:V16QI 0 \"vsx_register_operand\" \"wa\")\n+\t\t (mem:V16QI (match_dup 1))\n+\t\t (ashift:DI (match_operand:DI 2 \"register_operand\" \"r\")\n+\t\t\t\t (const_int 56))]\n+\t UNSPEC_STXVLL))]\n+ \"TARGET_FUTURE\"\n+ \"stxvrll %x0,%1,%2\"\n+ [(set_attr \"type\" \"vecstore\")])\n+\n ;; Expand for builtin xst_len_r\n (define_expand \"xst_len_r\"\n [(match_operand:V16QI 0 \"vsx_register_operand\" \"=wa\")\ndiff --git a/gcc/testsuite/gcc.target/powerpc/lxvrl.c b/gcc/testsuite/gcc.target/powerpc/lxvrl.c\nnew file mode 100644\nindex 00000000000..71854c50c91\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/lxvrl.c\n@@ -0,0 +1,32 @@\n+/* { dg-do compile } */\n+/* { dg-require-effective-target powerpc_future_ok } */\n+/* { dg-require-effective-target lp64 } */\n+/* { dg-options \"-mdejagnu-cpu=future -O2\" } */\n+\n+/* Test whether the lxvrl and stxvrl instructions are generated for\n+ -mcpu=future on memory copy operations. */\n+\n+#ifndef VSIZE\n+#define VSIZE 2\n+#endif\n+\n+#ifndef LSIZE\n+#define LSIZE 5\n+#endif\n+\n+struct foo {\n+ vector unsigned char vc[VSIZE];\n+ unsigned char leftover[LSIZE];\n+};\n+\n+void memcpy_ptr (struct foo *p, struct foo *q)\n+{\n+ __builtin_memcpy ((void *) p,\t\t/* lxvrl and stxvrl. */\n+\t\t (void *) q,\n+\t\t (sizeof (vector unsigned char) * VSIZE) + LSIZE);\n+}\n+\n+/* { dg-final { scan-assembler {\\mlxvrl\\M} } } */\n+/* { dg-final { scan-assembler {\\mstxvrl\\M} } } */\n+/* { dg-final { scan-assembler-not {\\mlxvl\\M} } } */\n+/* { dg-final { scan-assembler-not {\\mstxvl\\M} } } */\n", "prefixes": [] }