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GET /api/patches/2225367/?format=api
{ "id": 2225367, "url": "http://patchwork.ozlabs.org/api/patches/2225367/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260420213529.1645560-8-l.scorcia@gmail.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260420213529.1645560-8-l.scorcia@gmail.com>", "list_archive_url": null, "date": "2026-04-20T21:30:06", "name": "[v5,7/9] regulator: Add MediaTek MT6392 regulator", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1d9da20986cb8d79a59d3edb532347b8aa928e38", "submitter": { "id": 92693, "url": "http://patchwork.ozlabs.org/api/people/92693/?format=api", "name": "Luca Leonardo Scorcia", "email": "l.scorcia@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260420213529.1645560-8-l.scorcia@gmail.com/mbox/", "series": [ { "id": 500687, "url": "http://patchwork.ozlabs.org/api/series/500687/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=500687", "date": "2026-04-20T21:30:02", "name": "Add support for MT6392 PMIC", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/500687/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225367/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225367/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-35283-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Dx4d8hrz;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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It is a so called PMIC and\nconnects as a slave to a SoC using SPI, wrapped inside PWRAP.\n\nSigned-off-by: Fabien Parent <parent.f@gmail.com>\nCo-developed-by: Val Packett <val@packett.cool>\nSigned-off-by: Val Packett <val@packett.cool>\nSigned-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>\n---\n drivers/regulator/Kconfig | 9 +\n drivers/regulator/Makefile | 1 +\n drivers/regulator/mt6392-regulator.c | 740 +++++++++++++++++++++\n include/linux/regulator/mt6392-regulator.h | 42 ++\n 4 files changed, 792 insertions(+)\n create mode 100644 drivers/regulator/mt6392-regulator.c\n create mode 100644 include/linux/regulator/mt6392-regulator.h", "diff": "diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig\nindex 10e64e3ffb1f..f1f722e20484 100644\n--- a/drivers/regulator/Kconfig\n+++ b/drivers/regulator/Kconfig\n@@ -1000,6 +1000,15 @@ config REGULATOR_MT6380\n \t This driver supports the control of different power rails of device\n \t through regulator interface.\n \n+config REGULATOR_MT6392\n+\ttristate \"MediaTek MT6392 PMIC\"\n+\tdepends on MFD_MT6397\n+\thelp\n+\t Say y here to select this option to enable the power regulator of\n+\t MediaTek MT6392 PMIC.\n+\t This driver supports the control of different power rails of device\n+\t through regulator interface.\n+\n config REGULATOR_MT6397\n \ttristate \"MediaTek MT6397 PMIC\"\n \tdepends on MFD_MT6397\ndiff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile\nindex 35639f3115fd..e5f1fa91b967 100644\n--- a/drivers/regulator/Makefile\n+++ b/drivers/regulator/Makefile\n@@ -118,6 +118,7 @@ obj-$(CONFIG_REGULATOR_MT6360) += mt6360-regulator.o\n obj-$(CONFIG_REGULATOR_MT6363) += mt6363-regulator.o\n obj-$(CONFIG_REGULATOR_MT6370) += mt6370-regulator.o\n obj-$(CONFIG_REGULATOR_MT6380)\t+= mt6380-regulator.o\n+obj-$(CONFIG_REGULATOR_MT6392)\t+= mt6392-regulator.o\n obj-$(CONFIG_REGULATOR_MT6397)\t+= mt6397-regulator.o\n obj-$(CONFIG_REGULATOR_MTK_DVFSRC) += mtk-dvfsrc-regulator.o\n obj-$(CONFIG_REGULATOR_QCOM_LABIBB) += qcom-labibb-regulator.o\ndiff --git a/drivers/regulator/mt6392-regulator.c b/drivers/regulator/mt6392-regulator.c\nnew file mode 100644\nindex 000000000000..5b6f5a98b7e0\n--- /dev/null\n+++ b/drivers/regulator/mt6392-regulator.c\n@@ -0,0 +1,740 @@\n+// SPDX-License-Identifier: GPL-2.0\n+//\n+// Copyright (c) 2020 MediaTek Inc.\n+// Copyright (c) 2020 BayLibre, SAS.\n+// Author: Chen Zhong <chen.zhong@mediatek.com>\n+// Author: Fabien Parent <fparent@baylibre.com>\n+// Author: Luca Leonardo Scorcia <l.scorcia@gmail.com>\n+//\n+// The data sheet for MT6392 regulators is spotty to say the least,\n+// many important registers/fields are missing and the ones that aren't\n+// lack crucial information. Some useful details have been retrieved from\n+// Android sources.\n+// The driver code is mostly based on the MT6397 one.\n+\n+#include <linux/module.h>\n+#include <linux/linear_range.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <linux/regmap.h>\n+#include <linux/mfd/mt6397/core.h>\n+#include <linux/mfd/mt6392/registers.h>\n+#include <linux/regulator/driver.h>\n+#include <linux/regulator/machine.h>\n+#include <linux/regulator/mt6392-regulator.h>\n+#include <linux/regulator/of_regulator.h>\n+#include <dt-bindings/regulator/mediatek,mt6392-regulator.h>\n+\n+/**\n+ * MT6392 regulators' information\n+ *\n+ * @desc: standard fields of regulator description.\n+ * @qi_status_reg: Register to query enable signal status of regulators\n+ * @qi_status_mask: Mask to query enable signal status of regulators (RO)\n+ * @vselctrl_reg: Vsel control mode selector register\n+ * @vselctrl_mask: Vsel control mode selector mask (RO)\n+ * @vsel_reg_mode_reg: Vsel register when Vsel control mode selector = 0 (Register mode)\n+ * @vsel_reg_mode_mask: Vsel register mask in Register mode (RW)\n+ * @vsel_normal_mode_reg: Vsel register when Vsel control mode selector = 1 (Normal mode)\n+ * @vsel_normal_mode_mask: Vsel register mask in Register mode (RW)\n+ * @pwm_modeset_reg: Register to control buck mode (Auto/Force PWM)\n+ * @pwm_modeset_mask: Mask to control buck mode (RW)\n+ * @lp_modeget_reg: Register to get LDO low-power mode\n+ * @lp_modeget_mask: Mask to get LDO low-power mode (RO)\n+ * @lp_modeset_reg: Register to control LDO low-power mode\n+ * @lp_modeset_mask: Mask to control LDO low-power mode (WO)\n+ */\n+struct mt6392_regulator_info {\n+\tstruct regulator_desc desc;\n+\tu32 qi_status_reg;\n+\tu32 qi_status_mask;\n+\tu32 vselctrl_reg;\n+\tu32 vselctrl_mask;\n+\tu32 vsel_reg_mode_reg;\n+\tu32 vsel_reg_mode_mask;\n+\tu32 vsel_normal_mode_reg;\n+\tu32 vsel_normal_mode_mask;\n+\tu32 pwm_modeset_reg;\n+\tu32 pwm_modeset_mask;\n+\tu32 lp_modeget_reg;\n+\tu32 lp_modeget_mask;\n+\tu32 lp_modeset_reg;\n+\tu32 lp_modeset_mask;\n+};\n+\n+#define MT6392_BUCK(match, vreg, supply, min, max, step, volt_ranges,\t\\\n+\t_qi_status_reg, _qi_status_mask, _enable_reg, _enable_mask,\t\\\n+\t_vselctrl_reg, _vselctrl_mask,\t\t\t\t\t\\\n+\t_vsel_reg_mode_reg, _vsel_reg_mode_mask,\t\t\t\\\n+\t_vsel_normal_mode_reg, _vsel_normal_mode_mask,\t\t\t\\\n+\t_pwm_modeset_reg, _pwm_modeset_mask, _ramp_delay)\t\t\\\n+[MT6392_ID_##vreg] = {\t\t\t\t\t\t\t\\\n+\t.desc = {\t\t\t\t\t\t\t\\\n+\t\t.name = #vreg,\t\t\t\t\t\t\\\n+\t\t.supply_name = supply,\t\t\t\t\t\\\n+\t\t.of_match = of_match_ptr(match),\t\t\t\\\n+\t\t.regulators_node = of_match_ptr(\"regulators\"),\t\t\\\n+\t\t.ops = &mt6392_volt_range_ops,\t\t\t\t\\\n+\t\t.type = REGULATOR_VOLTAGE,\t\t\t\t\\\n+\t\t.id = MT6392_ID_##vreg,\t\t\t\t\t\\\n+\t\t.owner = THIS_MODULE,\t\t\t\t\t\\\n+\t\t.n_voltages = ((max) - (min)) / (step) + 1,\t\t\\\n+\t\t.linear_ranges = volt_ranges,\t\t\t\t\\\n+\t\t.n_linear_ranges = ARRAY_SIZE(volt_ranges),\t\t\\\n+\t\t.enable_reg = _enable_reg,\t\t\t\t\\\n+\t\t.enable_mask = _enable_mask,\t\t\t\t\\\n+\t\t.ramp_delay = _ramp_delay,\t\t\t\t\\\n+\t},\t\t\t\t\t\t\t\t\\\n+\t.qi_status_reg = _qi_status_reg,\t\t\t\t\\\n+\t.qi_status_mask = _qi_status_mask,\t\t\t\t\\\n+\t.vselctrl_reg = _vselctrl_reg,\t\t\t\t\t\\\n+\t.vselctrl_mask = _vselctrl_mask,\t\t\t\t\\\n+\t.vsel_reg_mode_reg = _vsel_reg_mode_reg,\t\t\t\\\n+\t.vsel_reg_mode_mask = _vsel_reg_mode_mask,\t\t\t\\\n+\t.vsel_normal_mode_reg = _vsel_normal_mode_reg,\t\t\t\\\n+\t.vsel_normal_mode_mask = _vsel_normal_mode_mask,\t\t\\\n+\t.pwm_modeset_reg = _pwm_modeset_reg,\t\t\t\t\\\n+\t.pwm_modeset_mask = _pwm_modeset_mask,\t\t\t\t\\\n+}\n+\n+#define MT6392_LDO(match, vreg, supply, ldo_volt_table,\t\t\t\\\n+\t_qi_status_reg, _qi_status_mask,\t\t\t\t\\\n+\t_enable_reg, _enable_mask,\t\t\t\t\t\\\n+\t_vsel_reg, _vsel_mask,\t\t\t\t\t\t\\\n+\t_lp_modeget_reg, _lp_modeget_mask,\t\t\t\t\\\n+\t_lp_modeset_reg, _lp_modeset_mask,\t\t\t\t\\\n+\t_enable_time)\t\t\t\t\t\t\t\\\n+[MT6392_ID_##vreg] = {\t\t\t\t\t\t\t\\\n+\t.desc = {\t\t\t\t\t\t\t\\\n+\t\t.name = #vreg,\t\t\t\t\t\t\\\n+\t\t.supply_name = supply,\t\t\t\t\t\\\n+\t\t.of_match = of_match_ptr(match),\t\t\t\\\n+\t\t.regulators_node = of_match_ptr(\"regulators\"),\t\t\\\n+\t\t.ops = &mt6392_volt_table_ops,\t\t\t\t\\\n+\t\t.type = REGULATOR_VOLTAGE,\t\t\t\t\\\n+\t\t.id = MT6392_ID_##vreg,\t\t\t\t\t\\\n+\t\t.owner = THIS_MODULE,\t\t\t\t\t\\\n+\t\t.n_voltages = ARRAY_SIZE(ldo_volt_table),\t\t\\\n+\t\t.volt_table = ldo_volt_table,\t\t\t\t\\\n+\t\t.vsel_reg = _vsel_reg,\t\t\t\t\t\\\n+\t\t.vsel_mask = _vsel_mask,\t\t\t\t\\\n+\t\t.enable_reg = _enable_reg,\t\t\t\t\\\n+\t\t.enable_mask = _enable_mask,\t\t\t\t\\\n+\t\t.enable_time = _enable_time,\t\t\t\t\\\n+\t},\t\t\t\t\t\t\t\t\\\n+\t.qi_status_reg = _qi_status_reg,\t\t\t\t\\\n+\t.qi_status_mask = _qi_status_mask,\t\t\t\t\\\n+\t.lp_modeget_reg = _lp_modeget_reg,\t\t\t\t\\\n+\t.lp_modeget_mask = _lp_modeget_mask,\t\t\t\t\\\n+\t.lp_modeset_reg = _lp_modeset_reg,\t\t\t\t\\\n+\t.lp_modeset_mask = _lp_modeset_mask,\t\t\t\t\\\n+}\n+\n+#define MT6392_LDO_LINEAR(match, vreg, supply, min, max, step,\t\t\\\n+\tvolt_ranges,\t\t\t\t\t\t\t\\\n+\t_qi_status_reg, _qi_status_mask,\t\t\t\t\\\n+\t_enable_reg, _enable_mask,\t\t\t\t\t\\\n+\t_vsel_reg, _vsel_mask,\t\t\t\t\t\t\\\n+\t_lp_modeget_reg, _lp_modeget_mask,\t\t\t\t\\\n+\t_lp_modeset_reg, _lp_modeset_mask,\t\t\t\t\\\n+\t_enable_time)\t\t\t\t\t\t\t\\\n+[MT6392_ID_##vreg] = {\t\t\t\t\t\t\t\\\n+\t.desc = {\t\t\t\t\t\t\t\\\n+\t\t.name = #vreg,\t\t\t\t\t\t\\\n+\t\t.supply_name = supply,\t\t\t\t\t\\\n+\t\t.of_match = of_match_ptr(match),\t\t\t\\\n+\t\t.regulators_node = of_match_ptr(\"regulators\"),\t\t\\\n+\t\t.ops = &mt6392_volt_ldo_range_ops,\t\t\t\\\n+\t\t.type = REGULATOR_VOLTAGE,\t\t\t\t\\\n+\t\t.id = MT6392_ID_##vreg,\t\t\t\t\t\\\n+\t\t.owner = THIS_MODULE,\t\t\t\t\t\\\n+\t\t.n_voltages = ((max) - (min)) / (step) + 1,\t\t\\\n+\t\t.linear_ranges = volt_ranges,\t\t\t\t\\\n+\t\t.n_linear_ranges = ARRAY_SIZE(volt_ranges),\t\t\\\n+\t\t.vsel_reg = _vsel_reg,\t\t\t\t\t\\\n+\t\t.vsel_mask = _vsel_mask,\t\t\t\t\\\n+\t\t.enable_reg = _enable_reg,\t\t\t\t\\\n+\t\t.enable_mask = _enable_mask,\t\t\t\t\\\n+\t\t.enable_time = _enable_time,\t\t\t\t\\\n+\t},\t\t\t\t\t\t\t\t\\\n+\t.qi_status_reg = _qi_status_reg,\t\t\t\t\\\n+\t.qi_status_mask = _qi_status_mask,\t\t\t\t\\\n+\t.lp_modeget_reg = _lp_modeget_reg,\t\t\t\t\\\n+\t.lp_modeget_mask = _lp_modeget_mask,\t\t\t\t\\\n+\t.lp_modeset_reg = _lp_modeset_reg,\t\t\t\t\\\n+\t.lp_modeset_mask = _lp_modeset_mask,\t\t\t\t\\\n+}\n+\n+#define MT6392_REG_FIXED(match, vreg, supply, volt,\t\t\t\\\n+\t_qi_status_reg, _qi_status_mask,\t\t\t\t\\\n+\t_enable_reg, _enable_mask,\t\t\t\t\t\\\n+\t_lp_modeget_reg, _lp_modeget_mask,\t\t\t\t\\\n+\t_lp_modeset_reg, _lp_modeset_mask,\t\t\t\t\\\n+\t_enable_time)\t\t\t\t\t\t\t\\\n+[MT6392_ID_##vreg] = {\t\t\t\t\t\t\t\\\n+\t.desc = {\t\t\t\t\t\t\t\\\n+\t\t.name = #vreg,\t\t\t\t\t\t\\\n+\t\t.supply_name = supply,\t\t\t\t\t\\\n+\t\t.of_match = of_match_ptr(match),\t\t\t\\\n+\t\t.regulators_node = of_match_ptr(\"regulators\"),\t\t\\\n+\t\t.ops = &mt6392_volt_fixed_ops,\t\t\t\t\\\n+\t\t.type = REGULATOR_VOLTAGE,\t\t\t\t\\\n+\t\t.id = MT6392_ID_##vreg,\t\t\t\t\t\\\n+\t\t.owner = THIS_MODULE,\t\t\t\t\t\\\n+\t\t.n_voltages = 1,\t\t\t\t\t\\\n+\t\t.min_uV = volt,\t\t\t\t\t\t\\\n+\t\t.enable_reg = _enable_reg,\t\t\t\t\\\n+\t\t.enable_mask = _enable_mask,\t\t\t\t\\\n+\t\t.enable_time = _enable_time,\t\t\t\t\\\n+\t},\t\t\t\t\t\t\t\t\\\n+\t.qi_status_reg = _qi_status_reg,\t\t\t\t\\\n+\t.qi_status_mask = _qi_status_mask,\t\t\t\t\\\n+\t.lp_modeget_reg = _lp_modeget_reg,\t\t\t\t\\\n+\t.lp_modeget_mask = _lp_modeget_mask,\t\t\t\t\\\n+\t.lp_modeset_reg = _lp_modeset_reg,\t\t\t\t\\\n+\t.lp_modeset_mask = _lp_modeset_mask,\t\t\t\t\\\n+}\n+\n+#define MT6392_REG_FIXED_NO_MODE(match, vreg, supply, volt,\t\t\\\n+\t_qi_status_reg, _qi_status_mask,\t\t\t\t\\\n+\t_enable_reg, _enable_mask, _enable_time)\t\t\t\\\n+[MT6392_ID_##vreg] = {\t\t\t\t\t\t\t\\\n+\t.desc = {\t\t\t\t\t\t\t\\\n+\t\t.name = #vreg,\t\t\t\t\t\t\\\n+\t\t.supply_name = supply,\t\t\t\t\t\\\n+\t\t.of_match = of_match_ptr(match),\t\t\t\\\n+\t\t.regulators_node = of_match_ptr(\"regulators\"),\t\t\\\n+\t\t.ops = &mt6392_volt_fixed_no_mode_ops,\t\t\t\\\n+\t\t.type = REGULATOR_VOLTAGE,\t\t\t\t\\\n+\t\t.id = MT6392_ID_##vreg,\t\t\t\t\t\\\n+\t\t.owner = THIS_MODULE,\t\t\t\t\t\\\n+\t\t.n_voltages = 1,\t\t\t\t\t\\\n+\t\t.min_uV = volt,\t\t\t\t\t\t\\\n+\t\t.enable_reg = _enable_reg,\t\t\t\t\\\n+\t\t.enable_mask = _enable_mask,\t\t\t\t\\\n+\t\t.enable_time = _enable_time,\t\t\t\t\\\n+\t},\t\t\t\t\t\t\t\t\\\n+\t.qi_status_reg = _qi_status_reg,\t\t\t\t\\\n+\t.qi_status_mask = _qi_status_mask,\t\t\t\t\\\n+}\n+\n+#define MT6392_REG(match, vreg, supply, volt)\t\t\t\t\\\n+[MT6392_ID_##vreg] = {\t\t\t\t\t\t\t\\\n+\t.desc = {\t\t\t\t\t\t\t\\\n+\t\t.name = #vreg,\t\t\t\t\t\t\\\n+\t\t.supply_name = supply,\t\t\t\t\t\\\n+\t\t.of_match = of_match_ptr(match),\t\t\t\\\n+\t\t.regulators_node = of_match_ptr(\"regulators\"),\t\t\\\n+\t\t.ops = &mt6392_volt_no_ops,\t\t\t\t\\\n+\t\t.type = REGULATOR_VOLTAGE,\t\t\t\t\\\n+\t\t.id = MT6392_ID_##vreg,\t\t\t\t\t\\\n+\t\t.owner = THIS_MODULE,\t\t\t\t\t\\\n+\t\t.n_voltages = 1,\t\t\t\t\t\\\n+\t\t.min_uV = volt,\t\t\t\t\t\t\\\n+\t},\t\t\t\t\t\t\t\t\\\n+}\n+\n+static const struct linear_range buck_volt_range1[] = {\n+\tREGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250),\n+};\n+\n+static const struct linear_range buck_volt_range2[] = {\n+\tREGULATOR_LINEAR_RANGE(1400000, 0, 0x7f, 12500),\n+};\n+\n+static const u32 ldo_volt_table1[] = {\n+\t1800000, 1900000, 2000000, 2200000,\n+};\n+\n+static const struct linear_range ldo_volt_range2[] = {\n+\tREGULATOR_LINEAR_RANGE(3300000, 0, 3, 100000),\n+};\n+\n+static const u32 ldo_volt_table3[] = {\n+\t1800000, 3300000,\n+};\n+\n+static const u32 ldo_volt_table4[] = {\n+\t3000000, 3300000,\n+};\n+\n+static const u32 ldo_volt_table5[] = {\n+\t1200000, 1300000, 1500000, 1800000, 2000000, 2800000, 3000000, 3300000,\n+};\n+\n+static const u32 ldo_volt_table6[] = {\n+\t1240000, 1390000,\n+};\n+\n+static const u32 ldo_volt_table7[] = {\n+\t1200000, 1300000, 1500000, 1800000,\n+};\n+\n+static const u32 ldo_volt_table8[] = {\n+\t1800000, 2000000,\n+};\n+\n+static int mt6392_buck_set_mode(struct regulator_dev *rdev, unsigned int mode)\n+{\n+\tint ret, val = 0;\n+\tstruct mt6392_regulator_info *info = rdev_get_drvdata(rdev);\n+\tu32 reg_value;\n+\n+\tif (!info->pwm_modeset_mask) {\n+\t\tdev_err(&rdev->dev, \"regulator %s doesn't support set_mode\\n\", info->desc.name);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tswitch (mode) {\n+\tcase REGULATOR_MODE_FAST:\n+\t\tval = MT6392_BUCK_MODE_FORCE_PWM;\n+\t\tbreak;\n+\tcase REGULATOR_MODE_NORMAL:\n+\t\tval = MT6392_BUCK_MODE_AUTO;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tval <<= ffs(info->pwm_modeset_mask) - 1;\n+\n+\tret = regmap_update_bits(rdev->regmap, info->pwm_modeset_reg,\n+\t\t\t\t info->pwm_modeset_mask, val);\n+\n+\tif (regmap_read(rdev->regmap, info->pwm_modeset_reg, ®_value) < 0) {\n+\t\tdev_err(&rdev->dev, \"Failed to read register value\\n\");\n+\t\treturn -EIO;\n+\t}\n+\n+\tdev_info(&rdev->dev, \"%s: info->pwm_modeset_reg 0x%x = 0x%x\\n\",\n+\t\t info->desc.name, info->pwm_modeset_reg, reg_value);\n+\n+\treturn ret;\n+}\n+\n+static unsigned int mt6392_buck_get_mode(struct regulator_dev *rdev)\n+{\n+\tunsigned int val;\n+\tunsigned int mode;\n+\tint ret;\n+\tstruct mt6392_regulator_info *info = rdev_get_drvdata(rdev);\n+\n+\tif (!info->pwm_modeset_mask) {\n+\t\tdev_err(&rdev->dev, \"regulator %s doesn't support get_mode\\n\", info->desc.name);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = regmap_read(rdev->regmap, info->pwm_modeset_reg, &val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tval &= info->pwm_modeset_mask;\n+\tval >>= ffs(info->pwm_modeset_mask) - 1;\n+\n+\tif (val & 0x1)\n+\t\tmode = REGULATOR_MODE_FAST;\n+\telse\n+\t\tmode = REGULATOR_MODE_NORMAL;\n+\n+\treturn mode;\n+}\n+\n+static int mt6392_ldo_set_mode(struct regulator_dev *rdev, unsigned int mode)\n+{\n+\tint ret, val = 0;\n+\tstruct mt6392_regulator_info *info = rdev_get_drvdata(rdev);\n+\n+\tif (!info->lp_modeset_mask) {\n+\t\tdev_err(&rdev->dev, \"regulator %s doesn't support set_mode\\n\",\n+\t\t\tinfo->desc.name);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tswitch (mode) {\n+\tcase REGULATOR_MODE_STANDBY:\n+\t\tval = MT6392_LDO_MODE_LP;\n+\t\tbreak;\n+\tcase REGULATOR_MODE_NORMAL:\n+\t\tval = MT6392_LDO_MODE_NORMAL;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tval <<= ffs(info->lp_modeset_mask) - 1;\n+\n+\tret = regmap_update_bits(rdev->regmap, info->lp_modeset_reg,\n+\t\t\t\t info->lp_modeset_mask, val);\n+\n+\treturn ret;\n+}\n+\n+static unsigned int mt6392_ldo_get_mode(struct regulator_dev *rdev)\n+{\n+\tunsigned int val;\n+\tunsigned int mode;\n+\tint ret;\n+\tstruct mt6392_regulator_info *info = rdev_get_drvdata(rdev);\n+\n+\tif (!info->lp_modeset_mask) {\n+\t\tdev_err(&rdev->dev, \"regulator %s doesn't support get_mode\\n\",\n+\t\t\tinfo->desc.name);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = regmap_read(rdev->regmap, info->lp_modeset_reg, &val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tval &= info->lp_modeset_mask;\n+\tval >>= ffs(info->lp_modeset_mask) - 1;\n+\n+\tif (val & 0x1)\n+\t\tmode = REGULATOR_MODE_STANDBY;\n+\telse\n+\t\tmode = REGULATOR_MODE_NORMAL;\n+\n+\treturn mode;\n+}\n+\n+static int mt6392_get_status(struct regulator_dev *rdev)\n+{\n+\tint ret;\n+\tu32 regval;\n+\tstruct mt6392_regulator_info *info = rdev_get_drvdata(rdev);\n+\n+\tret = regmap_read(rdev->regmap, info->qi_status_reg, ®val);\n+\tif (ret != 0) {\n+\t\tdev_err(&rdev->dev, \"Failed to read qi_status_reg: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\treturn (regval & info->qi_status_mask) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;\n+}\n+\n+static const struct regulator_ops mt6392_volt_range_ops = {\n+\t.list_voltage = regulator_list_voltage_linear_range,\n+\t.map_voltage = regulator_map_voltage_linear_range,\n+\t.set_voltage_sel = regulator_set_voltage_sel_regmap,\n+\t.get_voltage_sel = regulator_get_voltage_sel_regmap,\n+\t.set_voltage_time_sel = regulator_set_voltage_time_sel,\n+\t.enable = regulator_enable_regmap,\n+\t.disable = regulator_disable_regmap,\n+\t.is_enabled = regulator_is_enabled_regmap,\n+\t.get_status = mt6392_get_status,\n+\t.set_mode = mt6392_buck_set_mode,\n+\t.get_mode = mt6392_buck_get_mode,\n+};\n+\n+static const struct regulator_ops mt6392_volt_table_ops = {\n+\t.list_voltage = regulator_list_voltage_table,\n+\t.map_voltage = regulator_map_voltage_iterate,\n+\t.set_voltage_sel = regulator_set_voltage_sel_regmap,\n+\t.get_voltage_sel = regulator_get_voltage_sel_regmap,\n+\t.set_voltage_time_sel = regulator_set_voltage_time_sel,\n+\t.enable = regulator_enable_regmap,\n+\t.disable = regulator_disable_regmap,\n+\t.is_enabled = regulator_is_enabled_regmap,\n+\t.get_status = mt6392_get_status,\n+\t.set_mode = mt6392_ldo_set_mode,\n+\t.get_mode = mt6392_ldo_get_mode,\n+};\n+\n+static const struct regulator_ops mt6392_volt_ldo_range_ops = {\n+\t.list_voltage = regulator_list_voltage_linear_range,\n+\t.map_voltage = regulator_map_voltage_linear_range,\n+\t.set_voltage_sel = regulator_set_voltage_sel_regmap,\n+\t.get_voltage_sel = regulator_get_voltage_sel_regmap,\n+\t.set_voltage_time_sel = regulator_set_voltage_time_sel,\n+\t.enable = regulator_enable_regmap,\n+\t.disable = regulator_disable_regmap,\n+\t.is_enabled = regulator_is_enabled_regmap,\n+\t.get_status = mt6392_get_status,\n+\t.set_mode = mt6392_ldo_set_mode,\n+\t.get_mode = mt6392_ldo_get_mode,\n+};\n+\n+static const struct regulator_ops mt6392_volt_fixed_ops = {\n+\t.list_voltage = regulator_list_voltage_linear,\n+\t.enable = regulator_enable_regmap,\n+\t.disable = regulator_disable_regmap,\n+\t.is_enabled = regulator_is_enabled_regmap,\n+\t.get_status = mt6392_get_status,\n+\t.set_mode = mt6392_ldo_set_mode,\n+\t.get_mode = mt6392_ldo_get_mode,\n+};\n+\n+static const struct regulator_ops mt6392_volt_fixed_no_mode_ops = {\n+\t.list_voltage = regulator_list_voltage_linear,\n+\t.enable = regulator_enable_regmap,\n+\t.disable = regulator_disable_regmap,\n+\t.is_enabled = regulator_is_enabled_regmap,\n+\t.get_status = mt6392_get_status,\n+};\n+\n+static const struct regulator_ops mt6392_volt_no_ops = {\n+\t.list_voltage = regulator_list_voltage_linear,\n+};\n+\n+/* The array is indexed by id(MT6392_ID_XXX) */\n+static struct mt6392_regulator_info mt6392_regulators[] = {\n+\tMT6392_BUCK(\"vproc\", VPROC, \"vproc\", 700000, 1493750, 6250,\n+\t\t buck_volt_range1,\n+\t\t MT6392_VPROC_CON7, BIT(13), // Regulator status\n+\t\t MT6392_VPROC_CON7, BIT(0), // Regulator enable\n+\t\t MT6392_VPROC_CON5, BIT(0), // Vsel ctrl mode selector,not present in data sheet\n+\t\t MT6392_VPROC_CON9, GENMASK(6, 0), // Vsel when control mode = register (0)\n+\t\t MT6392_VPROC_CON10, GENMASK(6, 0), // Vsel when control mode = normal (1)\n+\t\t MT6392_VPROC_CON2, BIT(8), // Auto / Force PWM mode\n+\t\t 12500),\n+\tMT6392_BUCK(\"vsys\", VSYS, \"vsys\", 1400000, 2987500, 12500,\n+\t\t buck_volt_range2,\n+\t\t MT6392_VSYS_CON7, BIT(13),\n+\t\t MT6392_VSYS_CON7, BIT(0),\n+\t\t MT6392_VSYS_CON5, BIT(0), // Not present in data sheet\n+\t\t MT6392_VSYS_CON9, GENMASK(6, 0),\n+\t\t MT6392_VSYS_CON10, GENMASK(6, 0),\n+\t\t MT6392_VSYS_CON2, BIT(8),\n+\t\t 25000),\n+\tMT6392_BUCK(\"vcore\", VCORE, \"vcore\", 700000, 1493750, 6250,\n+\t\t buck_volt_range1,\n+\t\t MT6392_VCORE_CON7, BIT(13),\n+\t\t MT6392_VCORE_CON7, BIT(0),\n+\t\t MT6392_VCORE_CON5, BIT(0), // Not present in data sheet\n+\t\t MT6392_VCORE_CON9, GENMASK(6, 0),\n+\t\t MT6392_VCORE_CON10, GENMASK(6, 0),\n+\t\t MT6392_VCORE_CON2, BIT(8),\n+\t\t 12500),\n+\n+\tMT6392_REG_FIXED(\"vxo22\", VXO22, \"ldo1\", 2200000,\n+\t\t\t MT6392_ANALDO_CON1, BIT(15),\n+\t\t\t MT6392_ANALDO_CON1, BIT(10), // Not present in data sheet\n+\t\t\t MT6392_ANALDO_CON1, BIT(7),\n+\t\t\t MT6392_ANALDO_CON1, BIT(1), // Not present in data sheet\n+\t\t\t 110),\n+\tMT6392_LDO(\"vaud22\", VAUD22, \"ldo1\", ldo_volt_table1,\n+\t\t MT6392_ANALDO_CON2, BIT(15),\n+\t\t MT6392_ANALDO_CON2, BIT(14), // Not present in data sheet\n+\t\t MT6392_ANALDO_CON8, GENMASK(6, 5), // Not present in data sheet\n+\t\t MT6392_ANALDO_CON2, BIT(7),\n+\t\t MT6392_ANALDO_CON2, BIT(1), // Not present in data sheet\n+\t\t 264),\n+\tMT6392_REG_FIXED_NO_MODE(\"vcama\", VCAMA, \"ldo1\", 2800000,\n+\t\t\t\t MT6392_ANALDO_CON4, BIT(15),\n+\t\t\t\t MT6392_ANALDO_CON4, BIT(15),\n+\t\t\t\t 264),\n+\tMT6392_REG_FIXED(\"vaud28\", VAUD28, \"ldo1\", 2800000,\n+\t\t\t MT6392_ANALDO_CON23, BIT(15),\n+\t\t\t MT6392_ANALDO_CON23, BIT(14), // Not present in data sheet\n+\t\t\t MT6392_ANALDO_CON23, BIT(7),\n+\t\t\t MT6392_ANALDO_CON23, BIT(1), // Not present in data sheet\n+\t\t\t 264),\n+\tMT6392_REG_FIXED(\"vadc18\", VADC18, \"ldo1\", 1800000,\n+\t\t\t MT6392_ANALDO_CON25, BIT(15),\n+\t\t\t MT6392_ANALDO_CON25, BIT(14), // Not present in data sheet\n+\t\t\t MT6392_ANALDO_CON25, BIT(7),\n+\t\t\t MT6392_ANALDO_CON25, BIT(1), // Not present in data sheet\n+\t\t\t 264),\n+\tMT6392_LDO_LINEAR(\"vcn35\", VCN35, \"ldo2\", 3300000, 3600000, 100000, ldo_volt_range2,\n+\t\t\t MT6392_ANALDO_CON17, BIT(15), // Not present in data sheet\n+\t\t\t MT6392_ANALDO_CON21, BIT(12), // Not present in data sheet\n+\t\t\t MT6392_ANALDO_CON16, GENMASK(4, 3),\n+\t\t\t MT6392_ANALDO_CON21, BIT(7),\n+\t\t\t MT6392_ANALDO_CON21, BIT(1), // Not present in data sheet\n+\t\t\t 264),\n+\tMT6392_REG_FIXED(\"vio28\", VIO28, \"ldo2\", 2800000,\n+\t\t\t MT6392_DIGLDO_CON0, BIT(15),\n+\t\t\t MT6392_DIGLDO_CON0, BIT(14), // Not present in data sheet\n+\t\t\t MT6392_DIGLDO_CON0, BIT(7),\n+\t\t\t MT6392_DIGLDO_CON0, BIT(1), // Not present in data sheet\n+\t\t\t 264),\n+\tMT6392_REG_FIXED(\"vusb\", VUSB, \"ldo3\", 3300000,\n+\t\t\t MT6392_DIGLDO_CON2, BIT(15),\n+\t\t\t MT6392_DIGLDO_CON2, BIT(14), // Not present in data sheet\n+\t\t\t MT6392_DIGLDO_CON2, BIT(7),\n+\t\t\t MT6392_DIGLDO_CON2, BIT(1), // Not present in data sheet\n+\t\t\t 264),\n+\tMT6392_LDO(\"vmc\", VMC, \"ldo2\", ldo_volt_table3,\n+\t\t MT6392_DIGLDO_CON3, BIT(15),\n+\t\t MT6392_DIGLDO_CON3, BIT(12),\n+\t\t MT6392_DIGLDO_CON24, BIT(4),\n+\t\t MT6392_DIGLDO_CON3, BIT(7),\n+\t\t MT6392_DIGLDO_CON3, BIT(1), // Not present in data sheet\n+\t\t 264),\n+\tMT6392_LDO(\"vmch\", VMCH, \"ldo2\", ldo_volt_table4,\n+\t\t MT6392_DIGLDO_CON5, BIT(15),\n+\t\t MT6392_DIGLDO_CON5, BIT(14),\n+\t\t MT6392_DIGLDO_CON26, BIT(7),\n+\t\t MT6392_DIGLDO_CON5, BIT(7),\n+\t\t MT6392_DIGLDO_CON5, BIT(1), // Not present in data sheet\n+\t\t 264),\n+\tMT6392_LDO(\"vemc3v3\", VEMC3V3, \"ldo3\", ldo_volt_table4,\n+\t\t MT6392_DIGLDO_CON6, BIT(15),\n+\t\t MT6392_DIGLDO_CON6, BIT(14), // Not present in data sheet\n+\t\t MT6392_DIGLDO_CON27, BIT(7),\n+\t\t MT6392_DIGLDO_CON6, BIT(7),\n+\t\t MT6392_DIGLDO_CON6, BIT(1), // Not present in data sheet\n+\t\t 264),\n+\tMT6392_LDO(\"vgp1\", VGP1, \"ldo3\", ldo_volt_table5,\n+\t\t MT6392_DIGLDO_CON7, BIT(15),\n+\t\t MT6392_DIGLDO_CON7, BIT(15),\n+\t\t MT6392_DIGLDO_CON28, GENMASK(7, 5),\n+\t\t MT6392_DIGLDO_CON7, BIT(7),\n+\t\t MT6392_DIGLDO_CON7, BIT(1), // Not present in data sheet\n+\t\t 264),\n+\tMT6392_LDO(\"vgp2\", VGP2, \"ldo3\", ldo_volt_table5,\n+\t\t MT6392_DIGLDO_CON8, BIT(15),\n+\t\t MT6392_DIGLDO_CON8, BIT(15),\n+\t\t MT6392_DIGLDO_CON29, GENMASK(7, 5),\n+\t\t MT6392_DIGLDO_CON8, BIT(7),\n+\t\t MT6392_DIGLDO_CON8, BIT(1), // Not present in data sheet\n+\t\t 264),\n+\tMT6392_REG_FIXED(\"vcn18\", VCN18, \"avddldo\", 1800000,\n+\t\t\t MT6392_DIGLDO_CON11, BIT(15),\n+\t\t\t MT6392_DIGLDO_CON11, BIT(14), // Not present in data sheet\n+\t\t\t MT6392_DIGLDO_CON11, BIT(7),\n+\t\t\t MT6392_DIGLDO_CON11, BIT(1), // Not present in data sheet\n+\t\t\t 264),\n+\tMT6392_LDO(\"vcamaf\", VCAMAF, \"ldo3\", ldo_volt_table5,\n+\t\t MT6392_DIGLDO_CON31, BIT(15),\n+\t\t MT6392_DIGLDO_CON31, BIT(15),\n+\t\t MT6392_DIGLDO_CON32, GENMASK(7, 5),\n+\t\t MT6392_DIGLDO_CON31, BIT(7),\n+\t\t MT6392_DIGLDO_CON31, BIT(1), // Not present in data sheet\n+\t\t 264),\n+\tMT6392_LDO(\"vm\", VM, \"avddldo\", ldo_volt_table6,\n+\t\t MT6392_DIGLDO_CON47, BIT(15),\n+\t\t MT6392_DIGLDO_CON47, BIT(14), // Not present in data sheet\n+\t\t MT6392_DIGLDO_CON48, GENMASK(5, 4), // Not present in data sheet\n+\t\t MT6392_DIGLDO_CON47, BIT(7), // Not present in data sheet\n+\t\t MT6392_DIGLDO_CON47, BIT(1),\n+\t\t 264),\n+\tMT6392_REG_FIXED(\"vio18\", VIO18, \"avddldo\", 1800000,\n+\t\t\t MT6392_DIGLDO_CON49, BIT(15),\n+\t\t\t MT6392_DIGLDO_CON49, BIT(14), // Not present in data sheet\n+\t\t\t MT6392_DIGLDO_CON49, BIT(7),\n+\t\t\t MT6392_DIGLDO_CON49, BIT(1), // Not present in data sheet\n+\t\t\t 264),\n+\tMT6392_LDO(\"vcamd\", VCAMD, \"avddldo\", ldo_volt_table7,\n+\t\t MT6392_DIGLDO_CON51, BIT(15),\n+\t\t MT6392_DIGLDO_CON51, BIT(14),\n+\t\t MT6392_DIGLDO_CON52, GENMASK(6, 5),\n+\t\t MT6392_DIGLDO_CON51, BIT(7),\n+\t\t MT6392_DIGLDO_CON51, BIT(1),\n+\t\t 264),\n+\tMT6392_REG_FIXED(\"vcamio\", VCAMIO, \"avddldo\", 1800000,\n+\t\t\t MT6392_DIGLDO_CON53, BIT(15),\n+\t\t\t MT6392_DIGLDO_CON53, BIT(14),\n+\t\t\t MT6392_DIGLDO_CON53, BIT(7),\n+\t\t\t MT6392_DIGLDO_CON53, BIT(1), // Not present in data sheet\n+\t\t\t 264),\n+\tMT6392_REG_FIXED(\"vm25\", VM25, \"ldo3\", 2500000,\n+\t\t\t MT6392_DIGLDO_CON55, BIT(15),\n+\t\t\t MT6392_DIGLDO_CON55, BIT(14), // Not present in data sheet\n+\t\t\t MT6392_DIGLDO_CON55, BIT(7),\n+\t\t\t MT6392_DIGLDO_CON55, BIT(1), // Not present in data sheet\n+\t\t\t 264),\n+\tMT6392_LDO(\"vefuse\", VEFUSE, \"ldo2\", ldo_volt_table8,\n+\t\t MT6392_DIGLDO_CON57, BIT(15),\n+\t\t MT6392_DIGLDO_CON57, BIT(14), // Not present in data sheet\n+\t\t MT6392_DIGLDO_CON58, BIT(5), // Not present in data sheet\n+\t\t MT6392_DIGLDO_CON57, BIT(7),\n+\t\t MT6392_DIGLDO_CON57, BIT(1), // Not present in data sheet\n+\t\t 264),\n+\tMT6392_REG(\"vdig18\", VDIG18, \"ldo2\", 1800000), // Internal non changeable regulator\n+\tMT6392_REG_FIXED_NO_MODE(\"vrtc\", VRTC, \"ldo1\", 2800000,\n+\t\t\t\t MT6392_DIGLDO_CON15, BIT(15),\n+\t\t\t\t MT6392_DIGLDO_CON15, BIT(8), // Not present in data sheet\n+\t\t\t\t 264)\n+};\n+\n+// Buck regulators can be in Register mode or Normal mode.\n+// Each mode uses a different register to set the desired voltage.\n+static int mt6392_set_buck_vsel_reg(struct platform_device *pdev)\n+{\n+\tstruct mt6397_chip *mt6392 = dev_get_drvdata(pdev->dev.parent);\n+\tint i;\n+\tu32 regval;\n+\n+\tfor (i = 0; i < MT6392_MAX_REGULATOR; i++) {\n+\t\tif (mt6392_regulators[i].vselctrl_reg) {\n+\t\t\t// Read the vselctrl_reg register\n+\t\t\tif (regmap_read(mt6392->regmap,\n+\t\t\t\t\tmt6392_regulators[i].vselctrl_reg,\n+\t\t\t\t\t®val) < 0) {\n+\t\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\t\"Failed to read buck ctrl\\n\");\n+\t\t\t\treturn -EIO;\n+\t\t\t}\n+\n+\t\t\t// vselctrl_reg[vselctrl_mask] defines the mode\n+\t\t\tif (regval & mt6392_regulators[i].vselctrl_mask) {\n+\t\t\t\t// Regulator in Normal mode\n+\t\t\t\tmt6392_regulators[i].desc.vsel_reg =\n+\t\t\t\t\tmt6392_regulators[i].vsel_normal_mode_reg;\n+\t\t\t\tmt6392_regulators[i].desc.vsel_mask =\n+\t\t\t\t\tmt6392_regulators[i].vsel_normal_mode_mask;\n+\t\t\t} else {\n+\t\t\t\t// Regulator in Register mode\n+\t\t\t\tmt6392_regulators[i].desc.vsel_reg =\n+\t\t\t\t\tmt6392_regulators[i].vsel_reg_mode_reg;\n+\t\t\t\tmt6392_regulators[i].desc.vsel_mask =\n+\t\t\t\t\tmt6392_regulators[i].vsel_reg_mode_mask;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mt6392_regulator_probe(struct platform_device *pdev)\n+{\n+\tstruct mt6397_chip *mt6392 = dev_get_drvdata(pdev->dev.parent);\n+\tstruct regulator_config config = {};\n+\tstruct regulator_dev *rdev;\n+\tint i;\n+\n+\tdevice_set_of_node_from_dev(&pdev->dev, pdev->dev.parent);\n+\n+\t// Initialize the bucks' vsel_reg and vsel_mask according to current HW state\n+\tif (mt6392_set_buck_vsel_reg(pdev))\n+\t\treturn -EIO;\n+\n+\tconfig.dev = mt6392->dev;\n+\tconfig.regmap = mt6392->regmap;\n+\tfor (i = 0; i < MT6392_MAX_REGULATOR; i++) {\n+\t\tconfig.driver_data = &mt6392_regulators[i];\n+\n+\t\trdev = devm_regulator_register(&pdev->dev,\n+\t\t\t\t\t &mt6392_regulators[i].desc,\n+\t\t\t\t\t &config);\n+\t\tif (IS_ERR(rdev)) {\n+\t\t\tdev_err(&pdev->dev, \"failed to register %s\\n\",\n+\t\t\t\tmt6392_regulators[i].desc.name);\n+\t\t\treturn PTR_ERR(rdev);\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct platform_device_id mt6392_platform_ids[] = {\n+\t{\"mt6392-regulator\", 0},\n+\t{ /* sentinel */ },\n+};\n+MODULE_DEVICE_TABLE(platform, mt6392_platform_ids);\n+\n+static struct platform_driver mt6392_regulator_driver = {\n+\t.driver = {\n+\t\t.name = \"mt6392-regulator\",\n+\t\t.probe_type = PROBE_PREFER_ASYNCHRONOUS,\n+\t},\n+\t.probe = mt6392_regulator_probe,\n+\t.id_table = mt6392_platform_ids,\n+};\n+\n+module_platform_driver(mt6392_regulator_driver);\n+\n+MODULE_AUTHOR(\"Chen Zhong <chen.zhong@mediatek.com>\");\n+MODULE_DESCRIPTION(\"Regulator Driver for MediaTek MT6392 PMIC\");\n+MODULE_LICENSE(\"GPL\");\ndiff --git a/include/linux/regulator/mt6392-regulator.h b/include/linux/regulator/mt6392-regulator.h\nnew file mode 100644\nindex 000000000000..0eccd085b062\n--- /dev/null\n+++ b/include/linux/regulator/mt6392-regulator.h\n@@ -0,0 +1,42 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/*\n+ * Copyright (c) 2019 MediaTek Inc.\n+ * Author: Chen Zhong <chen.zhong@mediatek.com>\n+ */\n+\n+#ifndef __LINUX_REGULATOR_MT6392_H\n+#define __LINUX_REGULATOR_MT6392_H\n+\n+enum {\n+\tMT6392_ID_VPROC = 0,\n+\tMT6392_ID_VSYS,\n+\tMT6392_ID_VCORE,\n+\tMT6392_ID_VXO22,\n+\tMT6392_ID_VAUD22,\n+\tMT6392_ID_VCAMA,\n+\tMT6392_ID_VAUD28,\n+\tMT6392_ID_VADC18,\n+\tMT6392_ID_VCN35,\n+\tMT6392_ID_VIO28,\n+\tMT6392_ID_VUSB = 10,\n+\tMT6392_ID_VMC,\n+\tMT6392_ID_VMCH,\n+\tMT6392_ID_VEMC3V3,\n+\tMT6392_ID_VGP1,\n+\tMT6392_ID_VGP2,\n+\tMT6392_ID_VCN18,\n+\tMT6392_ID_VCAMAF,\n+\tMT6392_ID_VM,\n+\tMT6392_ID_VIO18,\n+\tMT6392_ID_VCAMD,\n+\tMT6392_ID_VCAMIO,\n+\tMT6392_ID_VM25,\n+\tMT6392_ID_VEFUSE,\n+\tMT6392_ID_VDIG18,\n+\tMT6392_ID_VRTC,\n+\tMT6392_ID_RG_MAX,\n+};\n+\n+#define MT6392_MAX_REGULATOR\tMT6392_ID_RG_MAX\n+\n+#endif /* __LINUX_REGULATOR_MT6392_H */\n", "prefixes": [ "v5", "7/9" ] }