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GET /api/patches/2224951/?format=api
{ "id": 2224951, "url": "http://patchwork.ozlabs.org/api/patches/2224951/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260420013554.418485-1-marek.vasut+renesas@mailbox.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260420013554.418485-1-marek.vasut+renesas@mailbox.org>", "list_archive_url": null, "date": "2026-04-20T01:32:35", "name": "arm64: dts: renesas: r8a779md: Add support for R-Car M3Le R8A779MD Geist", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "cff9aaf316542f6514da4e2c2bce3ef9176ebe51", "submitter": { "id": 85650, "url": "http://patchwork.ozlabs.org/api/people/85650/?format=api", "name": "Marek Vasut", "email": "marek.vasut+renesas@mailbox.org" }, "delegate": { "id": 1699, "url": "http://patchwork.ozlabs.org/api/users/1699/?format=api", "username": "marex", "first_name": "Marek", "last_name": "Vasut", "email": "marek.vasut@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260420013554.418485-1-marek.vasut+renesas@mailbox.org/mbox/", "series": [ { "id": 500539, "url": "http://patchwork.ozlabs.org/api/series/500539/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=500539", "date": "2026-04-20T01:32:35", "name": "arm64: dts: renesas: r8a779md: Add support for R-Car M3Le R8A779MD Geist", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500539/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224951/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224951/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": 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h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:\n content-transfer-encoding:content-transfer-encoding;\n bh=KhfuIlk4QWsDAvJmREH3B/ZFt38sFi7S/SnDWq0b5ls=;\n b=MnCK6IyBjDkOjLiHxgloHZ503dW55GwDmKw/MdJSjFxMSd+K1RHlypiCiEoQ6BvhWNfNXt\n lMGjQnnCtsS6H1siyDk8TLTK3uwrOUeXhB/s9GZSGsF7nvos3sud2eX0TdZGko70eHQxys\n jsNMoylcB1mwsjiKb0zCnZxGVhlbN3t76DE7+WhnMROjo6iIbLT691tDFmA+jK7VX48fLw\n hVqHkDLl0BHGlIq01U9bNgCG8EKnwnZarhKgtdeLF4l8F22GCQbBqaMJAeDEd9EUF4M7DB\n YZj0Niri9u1YRLUmRNtzhpDsHpJP+joH6ERMs/ohW8klkGmElvwgBa60AzHrrA==" ], "From": "Marek Vasut <marek.vasut+renesas@mailbox.org>", "To": "u-boot@lists.denx.de", "Cc": "Nguyen Tran <nguyen.tran.pz@bp.renesas.com>,\n Huy Bui <huy.bui.pz@bp.renesas.com>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>,\n Hai Pham <hai.pham.ud@renesas.com>,\n Nobuhiro Iwamatsu <iwamatsu@nigauri.org>, Tom Rini <trini@konsulko.com>", "Subject": "[PATCH] arm64: dts: renesas: r8a779md: Add support for R-Car M3Le\n R8A779MD Geist", "Date": "Mon, 20 Apr 2026 03:32:35 +0200", "Message-ID": "<20260420013554.418485-1-marek.vasut+renesas@mailbox.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-MBO-RS-ID": "8c3619b9a55637e1d9a", "X-MBO-RS-META": "34xcf8c414g78c8tcyqz1t7gamrmir5z", "X-Rspamd-Queue-Id": "4fzSkB17Zgz9tmT", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Nguyen Tran <nguyen.tran.pz@bp.renesas.com>\n\nAdd support for the Geist board based on the Renesas R8A779MD (M3Le) SoC, a\nregister-compatible variant of the R8A77965 (M3N) with reduced peripherals.\nThe Geist board design references the Renesas Salvator-X/XS boards, adapting\ntheir configuration for the R8A779MD SoC.\n\nThe board will be switched to OF_UPSTREAM once the DTs land in upstream.\n\nSigned-off-by: Huy Bui <huy.bui.pz@bp.renesas.com>\nSigned-off-by: Nguyen Tran <nguyen.tran.pz@bp.renesas.com>\nSigned-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>\n---\nCc: Hai Pham <hai.pham.ud@renesas.com>\nCc: Huy Bui <huy.bui.pz@bp.renesas.com>\nCc: Nguyen Tran <nguyen.tran.pz@bp.renesas.com>\nCc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>\nCc: Tom Rini <trini@konsulko.com>\nCc: u-boot@lists.denx.de\n---\nNOTE: DTs are also submitted to Linux kernel ML:\n https://lore.kernel.org/linux-arm-kernel/20260419193718.133174-1-marek.vasut+renesas@mailbox.org/\n The DTs in this MR match the Linux ones, except for pciec0_rp\n node which was added to Linux r8a77965.dtsi only very recently\n and will be synced together with Linux DTs at a future date.\n Until the sync happens, the PCIe is described using fixed clock.\n---\n arch/arm/dts/Makefile | 3 +\n arch/arm/dts/r8a779md-geist-u-boot.dtsi | 59 ++\n arch/arm/dts/r8a779md-geist.dts | 827 ++++++++++++++++++++++++\n arch/arm/dts/r8a779md.dtsi | 48 ++\n arch/arm/mach-renesas/Kconfig.rcar3 | 8 +\n arch/arm/mach-renesas/cpu_info.c | 13 +\n board/renesas/geist/Kconfig | 15 +\n board/renesas/geist/Makefile | 9 +\n board/renesas/geist/geist.c | 36 ++\n configs/r8a779md_geist_defconfig | 75 +++\n include/configs/geist.h | 18 +\n 11 files changed, 1111 insertions(+)\n create mode 100644 arch/arm/dts/r8a779md-geist-u-boot.dtsi\n create mode 100644 arch/arm/dts/r8a779md-geist.dts\n create mode 100644 arch/arm/dts/r8a779md.dtsi\n create mode 100644 board/renesas/geist/Kconfig\n create mode 100644 board/renesas/geist/Makefile\n create mode 100644 board/renesas/geist/geist.c\n create mode 100644 configs/r8a779md_geist_defconfig\n create mode 100644 include/configs/geist.h", "diff": "diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex bff341d6118..347e74616c8 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -906,6 +906,9 @@ dtb-$(CONFIG_RZA1) += \\\n \tr7s72100-genmai.dtb \\\n \tr7s72100-gr-peach.dtb\n \n+dtb-$(CONFIG_RCAR_GEN3) += \\\n+\tr8a779md-geist.dtb\n+\n dtb-$(CONFIG_RCAR_GEN5) += \\\n \tr8a78000-ironhide.dtb\n \ndiff --git a/arch/arm/dts/r8a779md-geist-u-boot.dtsi b/arch/arm/dts/r8a779md-geist-u-boot.dtsi\nnew file mode 100644\nindex 00000000000..fbda218002a\n--- /dev/null\n+++ b/arch/arm/dts/r8a779md-geist-u-boot.dtsi\n@@ -0,0 +1,59 @@\n+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+/*\n+ * Device Tree Source extras for U-Boot for the Geist board with r8a779md\n+ *\n+ * Copyright (C) 2025-2026 Renesas Electronics Corp.\n+ */\n+\n+/ {\n+\taliases {\n+\t\tspi0 = &rpc;\n+\t};\n+};\n+\n+&pfc {\n+\tqspi0_pins: qspi0 {\n+\t\tgroups = \"qspi0_ctrl\", \"qspi0_data4\";\n+\t\tfunction = \"qspi0\";\n+\t};\n+};\n+\n+/*\n+ * SPI access works only if TFA is built with RCAR_RPC_HYPERFLASH_LOCKED=0\n+ * and SPD=none , otherwise the RPC access is blocked either by TFA in case\n+ * the former is set to 1, or by OPTEE-OS in case SPD=opteed .\n+ */\n+&rpc {\n+\tpinctrl-0 = <&qspi0_pins>;\n+\tpinctrl-names = \"default\";\n+\n+\t#address-cells = <1>;\n+\t#size-cells = <0>;\n+\tspi-max-frequency = <40000000>;\n+\tstatus = \"okay\";\n+\n+\tflash@0 {\n+\t\tcompatible = \"jedec,spi-nor\";\n+\t\treg = <0>;\n+\t\tspi-max-frequency = <40000000>;\n+\t\tspi-tx-bus-width = <1>;\n+\t\tspi-rx-bus-width = <1>;\n+\t};\n+};\n+\n+&sdhi0 {\n+\tsd-uhs-sdr12;\n+\tsd-uhs-sdr25;\n+\tsd-uhs-sdr104;\n+\tmax-frequency = <208000000>;\n+};\n+\n+&sdhi2 {\n+\tmmc-ddr-1_8v;\n+\tmmc-hs200-1_8v;\n+\tmax-frequency = <200000000>;\n+};\n+\n+&vcc_sdhi0 {\n+\tu-boot,off-on-delay-us = <20000>;\n+};\ndiff --git a/arch/arm/dts/r8a779md-geist.dts b/arch/arm/dts/r8a779md-geist.dts\nnew file mode 100644\nindex 00000000000..10b22583943\n--- /dev/null\n+++ b/arch/arm/dts/r8a779md-geist.dts\n@@ -0,0 +1,827 @@\n+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+/*\n+ * Device Tree Source for the Geist board with R-Car M3Le\n+ *\n+ * Copyright (C) 2025-2026 Renesas Electronics Corp.\n+ */\n+\n+/dts-v1/;\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/input/input.h>\n+#include \"r8a779md.dtsi\"\n+\n+/ {\n+\tmodel = \"Renesas Geist board based on r8a779md\";\n+\tcompatible = \"renesas,geist\", \"renesas,r8a779md\", \"renesas,r8a77965\";\n+\n+\taliases {\n+\t\tserial0 = &scif2;\n+\t\tserial1 = &hscif1;\n+\t\tethernet0 = &avb;\n+\t\tmmc0 = &sdhi2;\n+\t\tmmc1 = &sdhi0;\n+\t};\n+\n+\tchosen {\n+\t\tbootargs = \"ignore_loglevel rw root=/dev/nfs ip=on\";\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tmemory@48000000 {\n+\t\tdevice_type = \"memory\";\n+\t\t/* first 128MB is reserved for secure area. */\n+\t\treg = <0x0 0x48000000 0x0 0x78000000>;\n+\t};\n+\n+\treserved-memory {\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tranges;\n+\n+\t\t/* Device specific region for Lossy Decompression */\n+\t\tlossy_decompress: linux,lossy_decompress@54000000 {\n+\t\t\tno-map;\n+\t\t\treg = <0x00000000 0x54000000 0x0 0x03000000>;\n+\t\t};\n+\t};\n+\n+\taudio_clkout: audio-clkout {\n+\t\t/*\n+\t\t * FIXME\n+\t\t * This is same as <&rcar_sound 0>\n+\t\t * but needed to avoid cs2500/rcar_sound probe dead-lock\n+\t\t */\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <12288000>;\n+\t};\n+\n+\tbacklight: backlight {\n+\t\tcompatible = \"pwm-backlight\";\n+\t\tpwms = <&pwm1 0 50000>;\n+\n+\t\tbrightness-levels = <256 128 64 16 8 4 0>;\n+\t\tdefault-brightness-level = <6>;\n+\n+\t\tpower-supply = <®_12v>;\n+\t\tenable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;\n+\t};\n+\n+\tcvbs-in {\n+\t\tcompatible = \"composite-video-connector\";\n+\t\tlabel = \"CVBS IN\";\n+\n+\t\tport {\n+\t\t\tcvbs_con: endpoint {\n+\t\t\t\tremote-endpoint = <&adv7482_ain7>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\thdmi-in {\n+\t\tcompatible = \"hdmi-connector\";\n+\t\tlabel = \"HDMI IN\";\n+\t\ttype = \"a\";\n+\n+\t\tport {\n+\t\t\thdmi_in_con: endpoint {\n+\t\t\t\tremote-endpoint = <&adv7482_hdmi>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tkeys {\n+\t\tcompatible = \"gpio-keys\";\n+\n+\t\tpinctrl-0 = <&keys_pins>;\n+\t\tpinctrl-names = \"default\";\n+\n+\t\tkey-1 {\n+\t\t\tgpios = <&gpio5 17 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <KEY_1>;\n+\t\t\tlabel = \"SW4-1\";\n+\t\t\twakeup-source;\n+\t\t\tdebounce-interval = <20>;\n+\t\t};\n+\n+\t\tkey-2 {\n+\t\t\tgpios = <&gpio5 20 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <KEY_2>;\n+\t\t\tlabel = \"SW4-2\";\n+\t\t\twakeup-source;\n+\t\t\tdebounce-interval = <20>;\n+\t\t};\n+\n+\t\tkey-3 {\n+\t\t\tgpios = <&gpio5 22 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <KEY_3>;\n+\t\t\tlabel = \"SW4-3\";\n+\t\t\twakeup-source;\n+\t\t\tdebounce-interval = <20>;\n+\t\t};\n+\n+\t\tkey-4 {\n+\t\t\tgpios = <&gpio5 23 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <KEY_4>;\n+\t\t\tlabel = \"SW4-4\";\n+\t\t\twakeup-source;\n+\t\t\tdebounce-interval = <20>;\n+\t\t};\n+\n+\t\tkey-a {\n+\t\t\tgpios = <&gpio6 11 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <KEY_A>;\n+\t\t\tlabel = \"TSW0\";\n+\t\t\twakeup-source;\n+\t\t\tdebounce-interval = <20>;\n+\t\t};\n+\n+\t\tkey-b {\n+\t\t\tgpios = <&gpio6 12 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <KEY_B>;\n+\t\t\tlabel = \"TSW1\";\n+\t\t\twakeup-source;\n+\t\t\tdebounce-interval = <20>;\n+\t\t};\n+\n+\t\tkey-c {\n+\t\t\tgpios = <&gpio6 13 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <KEY_C>;\n+\t\t\tlabel = \"TSW2\";\n+\t\t\twakeup-source;\n+\t\t\tdebounce-interval = <20>;\n+\t\t};\n+\t};\n+\n+\treg_1p8v: regulator0 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"fixed-1.8V\";\n+\t\tregulator-min-microvolt = <1800000>;\n+\t\tregulator-max-microvolt = <1800000>;\n+\t\tregulator-boot-on;\n+\t\tregulator-always-on;\n+\t};\n+\n+\treg_3p3v: regulator1 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"fixed-3.3V\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tregulator-boot-on;\n+\t\tregulator-always-on;\n+\t};\n+\n+\treg_12v: regulator2 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"fixed-12V\";\n+\t\tregulator-min-microvolt = <12000000>;\n+\t\tregulator-max-microvolt = <12000000>;\n+\t\tregulator-boot-on;\n+\t\tregulator-always-on;\n+\t};\n+\n+\tsound_card: sound {\n+\t\tcompatible = \"audio-graph-card\";\n+\n+\t\tlabel = \"rcar-sound\";\n+\t\tdais = <&rsnd_port0>; /* AK4619 Audio Codec */\n+\t};\n+\n+\tvbus0_usb2: regulator-vbus0-usb2 {\n+\t\tcompatible = \"regulator-fixed\";\n+\n+\t\tregulator-name = \"USB20_VBUS0\";\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-max-microvolt = <5000000>;\n+\n+\t\tgpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t};\n+\n+\tvcc_sdhi0: regulator-vcc-sdhi0 {\n+\t\tcompatible = \"regulator-fixed\";\n+\n+\t\tregulator-name = \"SDHI0 Vcc\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\n+\t\tgpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t};\n+\n+\tvccq_sdhi0: regulator-vccq-sdhi0 {\n+\t\tcompatible = \"regulator-gpio\";\n+\n+\t\tregulator-name = \"SDHI0 VccQ\";\n+\t\tregulator-min-microvolt = <1800000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\n+\t\tgpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;\n+\t\tgpios-states = <1>;\n+\t\tstates = <3300000 1>, <1800000 0>;\n+\t};\n+\n+\tvga {\n+\t\tcompatible = \"vga-connector\";\n+\n+\t\tport {\n+\t\t\tvga_in: endpoint {\n+\t\t\t\tremote-endpoint = <&adv7123_out>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tvga-encoder {\n+\t\tcompatible = \"adi,adv7123\";\n+\n+\t\tports {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tport@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t\tadv7123_in: endpoint {\n+\t\t\t\t\tremote-endpoint = <&du_out_rgb>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t\tport@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t\tadv7123_out: endpoint {\n+\t\t\t\t\tremote-endpoint = <&vga_in>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tx12_clk: x12 {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <24576000>;\n+\t};\n+\n+\t/* External DU dot clocks */\n+\tx21_clk: x21-clock {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <33000000>;\n+\t};\n+\n+\tx22_clk: x22-clock {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <33000000>;\n+\t};\n+\n+\tx23_clk: x23-clock {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <25000000>;\n+\t};\n+\n+\tx3013_clk: x3013-clock {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <25000000>;\n+\t};\n+};\n+\n+&audio_clk_a {\n+\tclock-frequency = <22579200>;\n+};\n+\n+&avb {\n+\tpinctrl-0 = <&avb_pins>;\n+\tpinctrl-names = \"default\";\n+\tphy-handle = <&phy0>;\n+\ttx-internal-delay-ps = <2000>;\n+\tstatus = \"okay\";\n+\n+\tphy0: ethernet-phy@0 {\n+\t\trxc-skew-ps = <1500>;\n+\t\treg = <0>;\n+\t\tinterrupt-parent = <&gpio2>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\treset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;\n+\t\treset-assert-us = <100>;\n+\t\treset-deassert-us = <100>;\n+\t};\n+};\n+\n+&csi40 {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\tcsi40_in: endpoint {\n+\t\t\t\tclock-lanes = <0>;\n+\t\t\t\tdata-lanes = <1 2 3 4>;\n+\t\t\t\tremote-endpoint = <&adv7482_txa>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&du {\n+\tpinctrl-0 = <&du_pins>;\n+\tpinctrl-names = \"default\";\n+\tclocks = <&cpg CPG_MOD 724>,\n+\t\t <&cpg CPG_MOD 723>,\n+\t\t <&cpg CPG_MOD 721>,\n+\t\t <&versaclock5 1>,\n+\t\t <&x21_clk>,\n+\t\t <&versaclock5 2>;\n+\tclock-names = \"du.0\", \"du.1\", \"du.3\",\n+\t\t \"dclkin.0\", \"dclkin.1\", \"dclkin.3\";\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\tdu_out_rgb: endpoint {\n+\t\t\t\tremote-endpoint = <&adv7123_in>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&ehci0 {\n+\tdr_mode = \"otg\";\n+\tstatus = \"okay\";\n+};\n+\n+&ehci1 {\n+\tstatus = \"okay\";\n+};\n+\n+&extalr_clk {\n+\tclock-frequency = <32768>;\n+};\n+\n+&extal_clk {\n+\tclock-frequency = <16666666>;\n+};\n+\n+&hscif1 {\n+\tpinctrl-0 = <&hscif1_pins>;\n+\tpinctrl-names = \"default\";\n+\n+\tuart-has-rtscts;\n+\t/* Please only enable hscif1 or scif1 */\n+\tstatus = \"okay\";\n+};\n+\n+&hsusb {\n+\tdr_mode = \"otg\";\n+\tstatus = \"okay\";\n+};\n+\n+&i2c2 {\n+\tpinctrl-0 = <&i2c2_pins>;\n+\tpinctrl-names = \"default\";\n+\tclock-frequency = <100000>;\n+\tstatus = \"okay\";\n+\n+\tak4619: codec@10 {\n+\t\tcompatible = \"asahi-kasei,ak4619\";\n+\t\treg = <0x10>;\n+\t\tclocks = <&rcar_sound 3>;\n+\t\tclock-names = \"mclk\";\n+\t\t#sound-dai-cells = <0>;\n+\n+\t\tport {\n+\t\t\tak4619_endpoint: endpoint {\n+\t\t\t\tremote-endpoint = <&rsnd_endpoint0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t/* Pin-to-pin, register map, and control compatible with CS2000 and CS2200 */\n+\tcs2500: clk_multiplier@4f {\n+\t\t#clock-cells = <0>;\n+\t\tcompatible = \"cirrus,cs2500-cp\", \"cirrus,cs2000-cp\";\n+\t\treg = <0x4f>;\n+\t\tclocks = <&audio_clkout>, <&x12_clk>;\n+\t\tclock-names = \"clk_in\", \"ref_clk\";\n+\n+\t\tassigned-clocks = <&cs2500>;\n+\t\tassigned-clock-rates = <24576000>; /* 1/1 divide */\n+\t};\n+};\n+\n+&i2c4 {\n+\tclock-frequency = <400000>;\n+\tstatus = \"okay\";\n+\n+\tversaclock3: clock-generator@68 {\n+\t\tcompatible = \"renesas,5p35023\";\n+\t\treg = <0x68>;\n+\t\t#clock-cells = <1>;\n+\t\tclocks = <&x3013_clk>;\n+\t\tassigned-clocks = <&versaclock3 4>, <&versaclock3 5>;\n+\t\tassigned-clock-rates = <100000000>, <100000000>;\n+\t};\n+\n+\tversaclock5: clock-generator@6a {\n+\t\tcompatible = \"idt,5p49v5923\";\n+\t\treg = <0x6a>;\n+\t\t#clock-cells = <1>;\n+\t\tclocks = <&x23_clk>;\n+\t\tclock-names = \"xin\";\n+\t};\n+\n+\tvideo-receiver@70 {\n+\t\tcompatible = \"adi,adv7482\";\n+\t\treg = <0x70 0x71 0x72 0x73 0x74 0x75\n+\t\t 0x60 0x61 0x62 0x63 0x64 0x65>;\n+\t\treg-names = \"main\", \"dpll\", \"cp\", \"hdmi\", \"edid\", \"repeater\",\n+\t\t\t \"infoframe\", \"cbus\", \"cec\", \"sdp\", \"txa\", \"txb\" ;\n+\n+\t\tinterrupt-parent = <&gpio6>;\n+\t\tinterrupts = <30 IRQ_TYPE_LEVEL_LOW>,\n+\t\t\t <31 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-names = \"intrq1\", \"intrq2\";\n+\n+\t\tports {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tport@7 {\n+\t\t\t\treg = <7>;\n+\n+\t\t\t\tadv7482_ain7: endpoint {\n+\t\t\t\t\tremote-endpoint = <&cvbs_con>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tport@8 {\n+\t\t\t\treg = <8>;\n+\n+\t\t\t\tadv7482_hdmi: endpoint {\n+\t\t\t\t\tremote-endpoint = <&hdmi_in_con>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tport@a {\n+\t\t\t\treg = <10>;\n+\n+\t\t\t\tadv7482_txa: endpoint {\n+\t\t\t\t\tclock-lanes = <0>;\n+\t\t\t\t\tdata-lanes = <1 2 3 4>;\n+\t\t\t\t\tremote-endpoint = <&csi40_in>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tcsa_vdd: adc@7c {\n+\t\tcompatible = \"maxim,max9611\";\n+\t\treg = <0x7c>;\n+\n+\t\tshunt-resistor-micro-ohms = <5000>;\n+\t};\n+\n+\tcsa_dvfs: adc@7f {\n+\t\tcompatible = \"maxim,max9611\";\n+\t\treg = <0x7f>;\n+\n+\t\tshunt-resistor-micro-ohms = <5000>;\n+\t};\n+};\n+\n+&i2c_dvfs {\n+\tstatus = \"okay\";\n+\n+\tclock-frequency = <400000>;\n+\n+\teeprom@50 {\n+\t\tcompatible = \"rohm,br24t01\", \"atmel,24c01\";\n+\t\treg = <0x50>;\n+\t\tpagesize = <8>;\n+\t};\n+};\n+\n+&ohci0 {\n+\tdr_mode = \"otg\";\n+\tstatus = \"okay\";\n+};\n+\n+&ohci1 {\n+\tstatus = \"okay\";\n+};\n+\n+&pcie_bus_clk {\n+\tclock-frequency = <100000000>;\n+};\n+\n+&pciec0 {\n+\tstatus = \"okay\";\n+};\n+\n+&pfc {\n+\tpinctrl-0 = <&scif_clk_pins>;\n+\tpinctrl-names = \"default\";\n+\n+\tavb_pins: avb {\n+\t\tmux {\n+\t\t\tgroups = \"avb_link\", \"avb_mdio\", \"avb_mii\";\n+\t\t\tfunction = \"avb\";\n+\t\t};\n+\n+\t\tpins_mdio {\n+\t\t\tgroups = \"avb_mdio\";\n+\t\t\tdrive-strength = <24>;\n+\t\t};\n+\n+\t\tpins_mii_tx {\n+\t\t\tpins = \"PIN_AVB_TX_CTL\", \"PIN_AVB_TXC\", \"PIN_AVB_TD0\",\n+\t\t\t \"PIN_AVB_TD1\", \"PIN_AVB_TD2\", \"PIN_AVB_TD3\";\n+\t\t\tdrive-strength = <12>;\n+\t\t};\n+\t};\n+\n+\tdu_pins: du {\n+\t\tgroups = \"du_rgb888\", \"du_sync\", \"du_oddf\", \"du_clk_out_0\";\n+\t\tfunction = \"du\";\n+\t};\n+\n+\thscif1_pins: hscif1 {\n+\t\tgroups = \"hscif1_data_a\", \"hscif1_ctrl_a\";\n+\t\tfunction = \"hscif1\";\n+\t};\n+\n+\ti2c2_pins: i2c2 {\n+\t\tgroups = \"i2c2_a\";\n+\t\tfunction = \"i2c2\";\n+\t};\n+\n+\tirq0_pins: irq0 {\n+\t\tgroups = \"intc_ex_irq0\";\n+\t\tfunction = \"intc_ex\";\n+\t};\n+\n+\tkeys_pins: keys {\n+\t\tpins = \"GP_5_17\", \"GP_5_20\", \"GP_5_22\";\n+\t\tbias-pull-up;\n+\t};\n+\n+\tpwm1_pins: pwm1 {\n+\t\tgroups = \"pwm1_a\";\n+\t\tfunction = \"pwm1\";\n+\t};\n+\n+\tpwm2_pins: pwm2 {\n+\t\tgroups = \"pwm2_a\";\n+\t\tfunction = \"pwm2\";\n+\t};\n+\n+\tscif1_pins: scif1 {\n+\t\tgroups = \"scif1_data_a\", \"scif1_ctrl\";\n+\t\tfunction = \"scif1\";\n+\t};\n+\n+\tscif2_pins: scif2 {\n+\t\tgroups = \"scif2_data_a\";\n+\t\tfunction = \"scif2\";\n+\t};\n+\n+\tscif_clk_pins: scif_clk {\n+\t\tgroups = \"scif_clk_a\";\n+\t\tfunction = \"scif_clk\";\n+\t};\n+\n+\tsdhi0_pins: sd0 {\n+\t\tgroups = \"sdhi0_data4\", \"sdhi0_ctrl\";\n+\t\tfunction = \"sdhi0\";\n+\t\tpower-source = <3300>;\n+\t};\n+\n+\tsdhi0_pins_uhs: sd0_uhs {\n+\t\tgroups = \"sdhi0_data4\", \"sdhi0_ctrl\";\n+\t\tfunction = \"sdhi0\";\n+\t\tpower-source = <1800>;\n+\t};\n+\n+\tsdhi2_pins: sd2 {\n+\t\tgroups = \"sdhi2_data8\", \"sdhi2_ctrl\", \"sdhi2_ds\";\n+\t\tfunction = \"sdhi2\";\n+\t\tpower-source = <1800>;\n+\t};\n+\n+\tsound_pins: sound {\n+\t\tgroups = \"ssi01239_ctrl\", \"ssi0_data\", \"ssi1_data_a\";\n+\t\tfunction = \"ssi\";\n+\t};\n+\n+\tsound_clk_pins: sound_clk {\n+\t\tgroups = \"audio_clk_a_a\", \"audio_clk_b_a\", \"audio_clk_c_a\",\n+\t\t\t \"audio_clkout_a\", \"audio_clkout3_a\";\n+\t\tfunction = \"audio_clk\";\n+\t};\n+\n+\tusb0_pins: usb0 {\n+\t\tgroups = \"usb0\";\n+\t\tfunction = \"usb0\";\n+\t};\n+\n+\tusb1_pins: usb1 {\n+\t\tmux {\n+\t\t\tgroups = \"usb1\";\n+\t\t\tfunction = \"usb1\";\n+\t\t};\n+\n+\t\tovc {\n+\t\t\tpins = \"GP_6_27\";\n+\t\t\tbias-pull-up;\n+\t\t};\n+\n+\t\tpwen {\n+\t\t\tpins = \"GP_6_26\";\n+\t\t\tbias-pull-down;\n+\t\t};\n+\t};\n+};\n+\n+&pwm1 {\n+\tpinctrl-0 = <&pwm1_pins>;\n+\tpinctrl-names = \"default\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+&pwm2 {\n+\tpinctrl-0 = <&pwm2_pins>;\n+\tpinctrl-names = \"default\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+&rcar_sound {\n+\tpinctrl-0 = <&sound_pins>, <&sound_clk_pins>;\n+\tpinctrl-names = \"default\";\n+\n+\t/* Single DAI */\n+\t#sound-dai-cells = <0>;\n+\n+\t/* audio_clkout0/1/2/3 */\n+\t#clock-cells = <1>;\n+\tclock-frequency = <12288000 11289600>;\n+\n+\tstatus = \"okay\";\n+\n+\t/* update <audio_clk_b> to <cs2500> */\n+\tclocks = <&cpg CPG_MOD 1005>,\n+\t\t <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,\n+\t\t <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,\n+\t\t <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,\n+\t\t <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,\n+\t\t <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,\n+\t\t <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,\n+\t\t <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,\n+\t\t <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,\n+\t\t <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,\n+\t\t <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,\n+\t\t <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,\n+\t\t <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,\n+\t\t <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,\n+\t\t <&audio_clk_a>, <&cs2500>,\n+\t\t <&audio_clk_c>,\n+\t\t <&cpg CPG_MOD 922>;\n+\n+\tports {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\trsnd_port0: port {\n+\t\t\trsnd_endpoint0: endpoint {\n+\t\t\t\tremote-endpoint = <&ak4619_endpoint>;\n+\t\t\t\tdai-format = \"left_j\";\n+\t\t\t\tbitclock-master = <&rsnd_endpoint0>;\n+\t\t\t\tframe-master = <&rsnd_endpoint0>;\n+\t\t\t\tplayback = <&ssi0>, <&src0>, <&dvc0>;\n+\t\t\t\tcapture = <&ssi1>, <&src1>, <&dvc1>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&rwdt {\n+\ttimeout-sec = <60>;\n+\tstatus = \"okay\";\n+};\n+\n+&scif1 {\n+\tpinctrl-0 = <&scif1_pins>;\n+\tpinctrl-names = \"default\";\n+\n+\tuart-has-rtscts;\n+\t/* Please only enable hscif1 or scif1 */\n+\t/* status = \"okay\"; */\n+};\n+\n+&scif2 {\n+\tpinctrl-0 = <&scif2_pins>;\n+\tpinctrl-names = \"default\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+&scif_clk {\n+\tclock-frequency = <14745600>;\n+};\n+\n+&sdhi0 {\n+\tpinctrl-0 = <&sdhi0_pins>;\n+\tpinctrl-1 = <&sdhi0_pins_uhs>;\n+\tpinctrl-names = \"default\", \"state_uhs\";\n+\n+\tvmmc-supply = <&vcc_sdhi0>;\n+\tvqmmc-supply = <&vccq_sdhi0>;\n+\tcd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;\n+\twp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;\n+\tbus-width = <4>;\n+\tsd-uhs-sdr50;\n+\tsd-uhs-sdr104;\n+\tstatus = \"okay\";\n+};\n+\n+&sdhi2 {\n+\t/* used for on-board 8bit eMMC */\n+\tpinctrl-0 = <&sdhi2_pins>;\n+\tpinctrl-1 = <&sdhi2_pins>;\n+\tpinctrl-names = \"default\", \"state_uhs\";\n+\n+\tiommus = <&ipmmu_ds1 34>;\n+\n+\tvmmc-supply = <®_3p3v>;\n+\tvqmmc-supply = <®_1p8v>;\n+\tbus-width = <8>;\n+\tmmc-hs200-1_8v;\n+\tno-sd;\n+\tno-sdio;\n+\tnon-removable;\n+\tfixed-emmc-driver-type = <1>;\n+\tfull-pwr-cycle-in-suspend;\n+\tstatus = \"okay\";\n+};\n+\n+&ssi1 {\n+\tshared-pin;\n+};\n+\n+&usb_extal_clk {\n+\tclock-frequency = <50000000>;\n+};\n+\n+&usb2_phy0 {\n+\tpinctrl-0 = <&usb0_pins>;\n+\tpinctrl-names = \"default\";\n+\n+\tvbus-supply = <&vbus0_usb2>;\n+\tstatus = \"okay\";\n+};\n+\n+&usb2_phy1 {\n+\tpinctrl-0 = <&usb1_pins>;\n+\tpinctrl-names = \"default\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+&vin0 {\n+\tstatus = \"okay\";\n+};\n+\n+&vin1 {\n+\tstatus = \"okay\";\n+};\n+\n+&vin2 {\n+\tstatus = \"okay\";\n+};\n+\n+&vin3 {\n+\tstatus = \"okay\";\n+};\n+\n+&vin4 {\n+\tstatus = \"okay\";\n+};\n+\n+&vin5 {\n+\tstatus = \"okay\";\n+};\n+\n+&vin6 {\n+\tstatus = \"okay\";\n+};\n+\n+&vin7 {\n+\tstatus = \"okay\";\n+};\n+\n+&vspb {\n+\tstatus = \"okay\";\n+};\n+\n+&vspi0 {\n+\tstatus = \"okay\";\n+};\ndiff --git a/arch/arm/dts/r8a779md.dtsi b/arch/arm/dts/r8a779md.dtsi\nnew file mode 100644\nindex 00000000000..7e0f5fe4cd4\n--- /dev/null\n+++ b/arch/arm/dts/r8a779md.dtsi\n@@ -0,0 +1,48 @@\n+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+/*\n+ * Device Tree Source for the R-Car M3Le (R8A779MD) SoC\n+ *\n+ * Copyright (C) 2025-2026 Renesas Electronics Corp.\n+ */\n+\n+#include \"r8a77965.dtsi\"\n+\n+/ {\n+\tcompatible = \"renesas,r8a779md\", \"renesas,r8a77965\";\n+};\n+\n+/delete-node/ &csi20;\n+/delete-node/ &drif00;\n+/delete-node/ &drif01;\n+/delete-node/ &drif10;\n+/delete-node/ &drif11;\n+/delete-node/ &drif20;\n+/delete-node/ &drif21;\n+/delete-node/ &drif30;\n+/delete-node/ &drif31;\n+/delete-node/ &hdmi0;\n+/delete-node/ &mlp;\n+/delete-node/ &pciec1;\n+/delete-node/ &sata;\n+/delete-node/ &sdhi3;\n+/delete-node/ &usb3_peri0;\n+/delete-node/ &usb3_phy0;\n+/delete-node/ &vin0csi20;\n+/delete-node/ &vin1csi20;\n+/delete-node/ &vin2csi20;\n+/delete-node/ &vin3csi20;\n+/delete-node/ &vin4csi20;\n+/delete-node/ &vin5csi20;\n+/delete-node/ &vin6csi20;\n+/delete-node/ &vin7csi20;\n+/delete-node/ &xhci0;\n+\n+&du {\n+\tcompatible = \"renesas,du-r8a779md\";\n+\trenesas,cmms = <&cmm0>, <&cmm3>;\n+\trenesas,vsps = <&vspd0 0>, <&vspd1 0>;\n+\n+\tports {\n+\t\t/delete-node/ port@1;\n+\t};\n+};\ndiff --git a/arch/arm/mach-renesas/Kconfig.rcar3 b/arch/arm/mach-renesas/Kconfig.rcar3\nindex 8479875178d..6bed7684fb8 100644\n--- a/arch/arm/mach-renesas/Kconfig.rcar3\n+++ b/arch/arm/mach-renesas/Kconfig.rcar3\n@@ -164,12 +164,20 @@ config TARGET_ULCB\n \thelp\n \t Support for Renesas R-Car Gen3 ULCB platform\n \n+config TARGET_GEIST\n+\tbool \"Geist board\"\n+\timply R8A77965\n+\timply SYS_MALLOC_F\n+\thelp\n+\t Support for Renesas R-Car Gen3 Geist platform\n+\n endchoice\n \n source \"board/renesas/condor/Kconfig\"\n source \"board/renesas/draak/Kconfig\"\n source \"board/renesas/eagle/Kconfig\"\n source \"board/renesas/ebisu/Kconfig\"\n+source \"board/renesas/geist/Kconfig\"\n source \"board/renesas/salvator-x/Kconfig\"\n source \"board/renesas/ulcb/Kconfig\"\n source \"board/renesas/v3hsk/Kconfig\"\ndiff --git a/arch/arm/mach-renesas/cpu_info.c b/arch/arm/mach-renesas/cpu_info.c\nindex f040d732a51..42183e2daa5 100644\n--- a/arch/arm/mach-renesas/cpu_info.c\n+++ b/arch/arm/mach-renesas/cpu_info.c\n@@ -114,6 +114,8 @@ int arch_misc_init(void)\n \n int print_cpuinfo(void)\n {\n+\tconst uintptr_t pfc_base = 0xe6060000;\n+\tvoid __iomem *rcar_m3nm3l_ident = (void __iomem *)pfc_base + 0x800;\n \tint i = renesas_cpuinfo_idx();\n \n \tif (renesas_cpuinfo[i].cpu_type == RENESAS_CPU_TYPE_R8A7796 &&\n@@ -123,6 +125,17 @@ int print_cpuinfo(void)\n \t\treturn 0;\n \t}\n \n+\t/*\n+\t * M3Le PRR ID is the same as M3N , but PFC register 0x800 reads 0\n+\t * on M3N and 1 on M3Le. Use this to discern M3Le from M3N .\n+\t */\n+\tif (renesas_cpuinfo[i].cpu_type == RENESAS_CPU_TYPE_R8A77965 &&\n+\t readl(rcar_m3nm3l_ident) == 1) {\n+\t\tprintf(\"CPU: Renesas Electronics R8A779MD rev %d.%d\\n\",\n+\t\t renesas_get_cpu_rev_integer(), renesas_get_cpu_rev_fraction());\n+\t\treturn 0;\n+\t}\n+\n \tprintf(\"CPU: Renesas Electronics %s rev %d.%d\\n\",\n \t\tget_cpu_name(i), renesas_get_cpu_rev_integer(),\n \t\trenesas_get_cpu_rev_fraction());\ndiff --git a/board/renesas/geist/Kconfig b/board/renesas/geist/Kconfig\nnew file mode 100644\nindex 00000000000..da36be0942f\n--- /dev/null\n+++ b/board/renesas/geist/Kconfig\n@@ -0,0 +1,15 @@\n+if TARGET_GEIST\n+\n+config SYS_SOC\n+\tdefault \"renesas\"\n+\n+config SYS_BOARD\n+\tdefault \"geist\"\n+\n+config SYS_VENDOR\n+\tdefault \"renesas\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"geist\"\n+\n+endif\ndiff --git a/board/renesas/geist/Makefile b/board/renesas/geist/Makefile\nnew file mode 100644\nindex 00000000000..3e33c91e9e7\n--- /dev/null\n+++ b/board/renesas/geist/Makefile\n@@ -0,0 +1,9 @@\n+#\n+# Copyright (C) 2025-2026 Renesas Electronics Corporation\n+#\n+# SPDX-License-Identifier: GPL-2.0-only\n+#\n+\n+ifndef CONFIG_XPL_BUILD\n+obj-y\t+= geist.o\n+endif\ndiff --git a/board/renesas/geist/geist.c b/board/renesas/geist/geist.c\nnew file mode 100644\nindex 00000000000..09241aed14c\n--- /dev/null\n+++ b/board/renesas/geist/geist.c\n@@ -0,0 +1,36 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * This file is Geist board support.\n+ *\n+ * Copyright (C) 2025-2026 Renesas Electronics Corporation\n+ */\n+\n+#include <asm/io.h>\n+#include <asm/arch/rcar-mstp.h>\n+#include <asm/arch/renesas.h>\n+#include <init.h>\n+\n+#define HSUSB_MSTP704\t\tBIT(4)\t/* HSUSB */\n+\n+/* HSUSB block registers */\n+#define HSUSB_REG_LPSTS\t\t\t0xE6590102\n+#define HSUSB_REG_LPSTS_SUSPM_NORMAL\tBIT(14)\n+#define HSUSB_REG_UGCTRL2\t\t0xE6590184\n+#define HSUSB_REG_UGCTRL2_USB0SEL\t0x30\n+#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI\t0x10\n+\n+int board_init(void)\n+{\n+\t/* USB1 pull-up */\n+\tsetbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);\n+\n+\t/* Configure the HSUSB block */\n+\tmstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);\n+\t/* Choice USB0SEL */\n+\tclrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,\n+\t\t\tHSUSB_REG_UGCTRL2_USB0SEL_EHCI);\n+\t/* low power status */\n+\tsetbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);\n+\n+\treturn 0;\n+}\ndiff --git a/configs/r8a779md_geist_defconfig b/configs/r8a779md_geist_defconfig\nnew file mode 100644\nindex 00000000000..2d25690354b\n--- /dev/null\n+++ b/configs/r8a779md_geist_defconfig\n@@ -0,0 +1,75 @@\n+#include <configs/renesas_rcar3.config>\n+\n+# CONFIG_OF_UPSTREAM is not set\n+\n+CONFIG_ARM=y\n+CONFIG_ARCH_RENESAS=y\n+CONFIG_RCAR_GEN3=y\n+CONFIG_COUNTER_FREQUENCY=16666666\n+CONFIG_ARCH_CPU_INIT=y\n+CONFIG_ENV_SIZE=0x20000\n+CONFIG_ENV_OFFSET=0xFFFE0000\n+CONFIG_DEFAULT_DEVICE_TREE=\"r8a779md-geist\"\n+CONFIG_SPL_TEXT_BASE=0xe6338000\n+CONFIG_TARGET_GEIST=y\n+CONFIG_SPL_HAVE_INIT_STACK=y\n+CONFIG_SPL_STACK=0xe6304000\n+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y\n+CONFIG_SPL_BSS_START_ADDR=0xe633f000\n+CONFIG_SPL_BSS_MAX_SIZE=0x1000\n+CONFIG_PCI=y\n+CONFIG_SYS_MONITOR_BASE=0x00000000\n+# CONFIG_EFI_UNICODE_CAPITALIZATION is not set\n+# CONFIG_BOOTSTD is not set\n+CONFIG_USE_BOOTARGS=y\n+CONFIG_USE_BOOTCOMMAND=y\n+CONFIG_BOOTCOMMAND=\"setexpr dloadaddr ${loadaddr} + 0x200000 && setexpr dloadaddr ${dloadaddr} \\\\\\\\& 0xffc00000 && setexpr kloadaddr ${dloadaddr} + 0x200000 && tftp ${dloadaddr} Image-r8a779md-geist.dtb && tftp ${kloadaddr} Image && booti ${kloadaddr} - ${dloadaddr}\"\n+CONFIG_DEFAULT_FDT_FILE=\"r8a779md-geist.dtb\"\n+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set\n+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10\n+CONFIG_CMD_DFU=y\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_PCI=y\n+CONFIG_CMD_USB=y\n+CONFIG_CMD_USB_MASS_STORAGE=y\n+CONFIG_DM_USB_GADGET=y\n+CONFIG_MULTI_DTB_FIT_LZO=y\n+CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y\n+CONFIG_OF_DTB_PROPS_REMOVE=y\n+CONFIG_OF_REMOVE_PROPS=\"dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus\"\n+CONFIG_ENV_IS_IN_MMC=y\n+CONFIG_ENV_RELOC_GD_ENV_ADDR=y\n+CONFIG_ENV_MMC_EMMC_HW_PARTITION=2\n+CONFIG_DFU_TFTP=y\n+CONFIG_DFU_RAM=y\n+CONFIG_DFU_SF=y\n+CONFIG_SYS_I2C_RCAR_IIC=y\n+CONFIG_MISC=y\n+CONFIG_I2C_EEPROM=y\n+CONFIG_SYS_I2C_EEPROM_ADDR=0x70\n+CONFIG_MMC_IO_VOLTAGE=y\n+CONFIG_MMC_UHS_SUPPORT=y\n+CONFIG_MMC_HS400_SUPPORT=y\n+CONFIG_RENESAS_SDHI=y\n+CONFIG_DM_MTD=y\n+CONFIG_SPI_FLASH_SPANSION=y\n+CONFIG_PHY_MICREL=y\n+CONFIG_PHY_MICREL_KSZ90X1=y\n+CONFIG_DM_ETH_PHY=y\n+CONFIG_RENESAS_RAVB=y\n+CONFIG_NVME_PCI=y\n+CONFIG_PCI_REGION_MULTI_ENTRY=y\n+CONFIG_PCI_RCAR_GEN3=y\n+CONFIG_SYSINFO=y\n+CONFIG_TEE=y\n+CONFIG_OPTEE=y\n+CONFIG_USB=y\n+CONFIG_USB_EHCI_HCD=y\n+CONFIG_USB_EHCI_GENERIC=y\n+CONFIG_USB_GADGET=y\n+CONFIG_USB_GADGET_MANUFACTURER=\"Renesas\"\n+CONFIG_USB_GADGET_VENDOR_NUM=0x045b\n+CONFIG_USB_GADGET_PRODUCT_NUM=0x023c\n+CONFIG_USB_GADGET_DOWNLOAD=y\n+CONFIG_USB_RENESAS_USBHS=y\n+CONFIG_USB_STORAGE=y\ndiff --git a/include/configs/geist.h b/include/configs/geist.h\nnew file mode 100644\nindex 00000000000..3f7e2e913ed\n--- /dev/null\n+++ b/include/configs/geist.h\n@@ -0,0 +1,18 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/*\n+ * This file is Geist board configuration.\n+ *\n+ * Copyright (C) 2025-2026 Renesas Electronics Corporation\n+ */\n+\n+#ifndef __GEIST_H\n+#define __GEIST_H\n+\n+#include \"rcar-gen3-common.h\"\n+\n+/* Environment in eMMC, at the end of 2nd \"boot sector\" */\n+\n+#define CFG_SYS_FLASH_BANKS_LIST\t{ 0x08000000 }\n+#define CFG_SYS_WRITE_SWAPPED_DATA\n+\n+#endif /* __GEIST_H */\n", "prefixes": [] }