Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2224857/?format=api
{ "id": 2224857, "url": "http://patchwork.ozlabs.org/api/patches/2224857/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260418223320.51330-9-mohamed@unpredictable.fr/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260418223320.51330-9-mohamed@unpredictable.fr>", "list_archive_url": null, "date": "2026-04-18T22:32:50", "name": "[08/38] whpx: i386: kernel-irqchip=off fixes", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "43c129a3bf01c246b07be19f74fa0e2a66f092e5", "submitter": { "id": 91318, "url": "http://patchwork.ozlabs.org/api/people/91318/?format=api", "name": "Mohamed Mediouni", "email": "mohamed@unpredictable.fr" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260418223320.51330-9-mohamed@unpredictable.fr/mbox/", "series": [ { "id": 500475, "url": "http://patchwork.ozlabs.org/api/series/500475/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500475", "date": "2026-04-18T22:32:54", "name": "WHPX x86 updates for QEMU 11.1", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500475/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224857/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224857/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=cFlL6npO;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fymqm6rrxz1yGt\n\tfor <incoming@patchwork.ozlabs.org>; Sun, 19 Apr 2026 08:38:28 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wEEEZ-000696-G8; Sat, 18 Apr 2026 18:33:51 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <mohamed@unpredictable.fr>)\n id 1wEEEU-00067D-DK\n for qemu-devel@nongnu.org; Sat, 18 Apr 2026 18:33:46 -0400", "from p-east2-cluster3-host12-snip4-8.eps.apple.com ([57.103.77.189]\n helo=outbound.st.icloud.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <mohamed@unpredictable.fr>)\n id 1wEEES-0004tQ-Py\n for qemu-devel@nongnu.org; Sat, 18 Apr 2026 18:33:46 -0400", "from outbound.st.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-east-1a-100-percent-1 (Postfix) with ESMTPS id\n AAF2E180022F; Sat, 18 Apr 2026 22:33:40 +0000 (UTC)", "from localhost.localdomain (unknown [17.42.251.67])\n by p00-icloudmta-asmtp-us-east-1a-100-percent-1 (Postfix) with ESMTPSA id\n 3C29A1800208; Sat, 18 Apr 2026 22:33:38 +0000 (UTC)" ], "Dkim-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1776551623; x=1779143623;\n bh=Dqy8GVOg6Vy5Bj3rQXQsRJvMspD1oQZRo/6wY+UsQGM=;\n h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme;\n b=cFlL6npOtaoMArzOJrhzsRLJ55oWJVe7VuNbkGuccfhQlCwVcAFE2c7G3ShrR+oVm7E4//klcIAAiR8En3sNt+1prGjmYG9OfscEzdE8wY0OPCFtg0a/zGzrrRztijw+GInfZoaxE6pRmO0MSYX6diKAcKwDikhD8972iqBb8SQG5PBPU5o5rhQ2oWa/cbXmaMk551WW+bLmz79GMw5ECE+uBMCzIGh+ah4BDCtC1kmn4AQ9TJ2OthNBdT4R0/FIWmZAKtxJAQ7zIHNqS1SDFRDI3vn2CYYUyDSoJ25B7vJ1O2rOdvqbqjcGfeQNNpwrvpxUMFHwreB6q3M11EQlVQ==", "mail-alias-created-date": "1752046281608", "From": "Mohamed Mediouni <mohamed@unpredictable.fr>", "To": "qemu-devel@nongnu.org", "Cc": "Mohamed Mediouni <mohamed@unpredictable.fr>,\n \"Michael S. Tsirkin\" <mst@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>,\n Zhao Liu <zhao1.liu@intel.com>, Pedro Barbuda <pbarbuda@microsoft.com>,\n Roman Bolshakov <rbolshakov@ddn.com>, qemu-arm@nongnu.org,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>,\n Peter Maydell <peter.maydell@linaro.org>, Wei Liu <wei.liu@kernel.org>,\n Phil Dennis-Jordan <phil@philjordan.eu>", "Subject": "[PATCH 08/38] whpx: i386: kernel-irqchip=off fixes", "Date": "Sun, 19 Apr 2026 00:32:50 +0200", "Message-ID": "<20260418223320.51330-9-mohamed@unpredictable.fr>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260418223320.51330-1-mohamed@unpredictable.fr>", "References": "<20260418223320.51330-1-mohamed@unpredictable.fr>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDE4MDIyOCBTYWx0ZWRfX/w2avdAHS4Bz\n T5RKAAP+wETEhoSOr8q5wDfbgHXqLcySOGCIQISVgtPX7inLJ0Lrh31E93b39T66XqILyk5NDEr\n CkZqW9IujQpnip3w9SMQy0kAF2DCFQ9q/C/Qteo7noXm2SeGlQocgYkRp3uNeS+xy7uYsYoPVvh\n nU1DZfpLCPG08qC8DbSsyEvH/f1LPlXr5dwu/ATFGPBe3MoD3M90uJw9JrLN9JV85do7Gf4s1bj\n xS26lX9pNUzach8POXzkawMulpG7nEPe53uqofKvNNQw5mRtXn4QV7RVY7OhBY9SGbUO/ccJgwi\n 4yZjp7ZXeIbo5CvL9V24Dqt3XWPspilXsEbTD6eqpvJeClKl/dd5yYammE4DYI=", "X-Authority-Info-Out": "v=2.4 cv=UqJu9uwB c=1 sm=1 tr=0 ts=69e406c6\n cx=c_apl:c_pps:t_out a=YrL12D//S6tul8v/L+6tKg==:117\n a=YrL12D//S6tul8v/L+6tKg==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=gP1GEkNOX-MqffGxZ4oA:9", "X-Proofpoint-GUID": "0umByWHxODrtxuxgPX1rsvpRfg6LA3aB", "X-Proofpoint-ORIG-GUID": "0umByWHxODrtxuxgPX1rsvpRfg6LA3aB", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-18_06,2026-04-17_04,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=notspam policy=default score=0 malwarescore=0\n mlxlogscore=999 phishscore=0 spamscore=0\n clxscore=1030 mlxscore=0\n lowpriorityscore=0 bulkscore=0 suspectscore=0 adultscore=0 classifier=spam\n authscore=0 adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000\n definitions=main-2604180228", "Received-SPF": "pass client-ip=57.103.77.189;\n envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This was really... quite broken. After fixing this,\nWindows boots with kernel-irqchip=off.\n\nSigned-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>\n---\n include/system/whpx-common.h | 1 +\n target/i386/whpx/whpx-all.c | 43 +++++-------------------------------\n 2 files changed, 7 insertions(+), 37 deletions(-)", "diff": "diff --git a/include/system/whpx-common.h b/include/system/whpx-common.h\nindex 04289afd97..3406c20fec 100644\n--- a/include/system/whpx-common.h\n+++ b/include/system/whpx-common.h\n@@ -4,6 +4,7 @@\n \n struct AccelCPUState {\n bool window_registered;\n+ int window_priority;\n bool interruptable;\n bool ready_for_pic_interrupt;\n uint64_t tpr;\ndiff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex 53b59a98b9..1d99003a4a 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -22,6 +22,8 @@\n #include \"qemu/main-loop.h\"\n #include \"hw/core/boards.h\"\n #include \"hw/intc/ioapic.h\"\n+#include \"hw/intc/i8259.h\"\n+#include \"hw/i386/x86.h\"\n #include \"hw/i386/apic_internal.h\"\n #include \"qemu/error-report.h\"\n #include \"qapi/error.h\"\n@@ -371,28 +373,6 @@ static int whpx_set_tsc(CPUState *cpu)\n return 0;\n }\n \n-/*\n- * The CR8 register in the CPU is mapped to the TPR register of the APIC,\n- * however, they use a slightly different encoding. Specifically:\n- *\n- * APIC.TPR[bits 7:4] = CR8[bits 3:0]\n- *\n- * This mechanism is described in section 10.8.6.1 of Volume 3 of Intel 64\n- * and IA-32 Architectures Software Developer's Manual.\n- *\n- * The functions below translate the value of CR8 to TPR and vice versa.\n- */\n-\n-static uint64_t whpx_apic_tpr_to_cr8(uint64_t tpr)\n-{\n- return tpr >> 4;\n-}\n-\n-static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8)\n-{\n- return cr8 << 4;\n-}\n-\n void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n {\n struct whpx_state *whpx = &whpx_global;\n@@ -421,7 +401,7 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n v86 = (env->eflags & VM_MASK);\n r86 = !(env->cr[0] & CR0_PE_MASK);\n \n- vcpu->tpr = whpx_apic_tpr_to_cr8(cpu_get_apic_tpr(x86_cpu->apic_state));\n+ vcpu->tpr = cpu_get_apic_tpr(x86_cpu->apic_state);\n vcpu->apic_base = cpu_get_apic_base(x86_cpu->apic_state);\n \n idx = 0;\n@@ -692,17 +672,6 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n hr);\n }\n \n- if (whpx_irqchip_in_kernel()) {\n- /*\n- * Fetch the TPR value from the emulated APIC. It may get overwritten\n- * below with the value from CR8 returned by\n- * WHvGetVirtualProcessorRegisters().\n- */\n- whpx_apic_get(x86_cpu->apic_state);\n- vcpu->tpr = whpx_apic_tpr_to_cr8(\n- cpu_get_apic_tpr(x86_cpu->apic_state));\n- }\n-\n idx = 0;\n \n /* Indexes for first 16 registers match between HV and QEMU definitions */\n@@ -751,7 +720,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n tpr = vcxt.values[idx++].Reg64;\n if (tpr != vcpu->tpr) {\n vcpu->tpr = tpr;\n- cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(tpr));\n+ cpu_set_apic_tpr(x86_cpu->apic_state, tpr);\n }\n \n /* 8 Debug Registers - Skipped */\n@@ -1690,7 +1659,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n }\n \n /* Sync the TPR to the CR8 if was modified during the intercept */\n- tpr = whpx_apic_tpr_to_cr8(cpu_get_apic_tpr(x86_cpu->apic_state));\n+ tpr = cpu_get_apic_tpr(x86_cpu->apic_state);\n if (tpr != vcpu->tpr) {\n vcpu->tpr = tpr;\n reg_values[reg_count].Reg64 = tpr;\n@@ -1737,7 +1706,7 @@ static void whpx_vcpu_post_run(CPUState *cpu)\n if (vcpu->tpr != tpr) {\n vcpu->tpr = tpr;\n bql_lock();\n- cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(vcpu->tpr));\n+ cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr);\n bql_unlock();\n }\n \n", "prefixes": [ "08/38" ] }