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GET /api/patches/2224767/?format=api
{ "id": 2224767, "url": "http://patchwork.ozlabs.org/api/patches/2224767/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260418-pfuze100-v1-1-80d2a96dd927@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260418-pfuze100-v1-1-80d2a96dd927@nxp.com>", "list_archive_url": null, "date": "2026-04-18T12:37:32", "name": "[1/4] power: regulator: pfuze100: Fix min_uV usage", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5d57726c127f070f20e4426b41d569a18022a2fb", "submitter": { "id": 80723, "url": "http://patchwork.ozlabs.org/api/people/80723/?format=api", "name": "Peng Fan", "email": "peng.fan@oss.nxp.com" }, "delegate": { "id": 12423, "url": "http://patchwork.ozlabs.org/api/users/12423/?format=api", "username": "Jaehoon", "first_name": "Jaehoon", "last_name": "Chung", "email": "jh80.chung@samsung.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260418-pfuze100-v1-1-80d2a96dd927@nxp.com/mbox/", "series": [ { "id": 500437, "url": "http://patchwork.ozlabs.org/api/series/500437/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=500437", "date": "2026-04-18T12:37:31", "name": "power: regulator: various fix for pfuze100", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500437/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224767/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224767/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", 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b=yEVGBTbzT6mRQFykcQ4B+PHs0FHyfRbpQakx/GRa6gsvlBN7TqupiXNTtAqHkVSVLY0KYq00ScY7i3DLD7VXlh9Xkh9hMFbt2jKkelrWQrkytTpI1Ubt4rbLBjECvfQYfzGNL2a8uy/BRRLbBN5fwHdmevq7UacPkMnHmpd5366m9TJ4tG9x7G5tGLR8C8JbizsDQ8b759ZS8U25lXouxGMuf7lY8wwW4WPBlXaoNVVqWZ+22kN54tXleofBwah3xfzb5ZLnnZzQSH+cBwXTK/xyYsNpgWaTcz5tL4qKumScNTMzbLEf+ziUzTHskEaVx+fRrbY4nEr5GoEAyBY6pw==", "From": "\"Peng Fan (OSS)\" <peng.fan@oss.nxp.com>", "Date": "Sat, 18 Apr 2026 20:37:32 +0800", "Subject": "[PATCH 1/4] power: regulator: pfuze100: Fix min_uV usage", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260418-pfuze100-v1-1-80d2a96dd927@nxp.com>", "References": "<20260418-pfuze100-v1-0-80d2a96dd927@nxp.com>", "In-Reply-To": "<20260418-pfuze100-v1-0-80d2a96dd927@nxp.com>", "To": "u-boot@lists.denx.de", "Cc": "uboot-imx@nxp.com, Jaehoon Chung <jh80.chung@samsung.com>,\n Tom Rini <trini@konsulko.com>, Peng Fan <peng.fan@nxp.com>", "X-Mailer": "b4 0.14.3", "X-ClientProxiedBy": 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"X-OriginatorOrg": "oss.nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 761860ef-b6f1-44d0-e3f8-08de9d3c9806", "X-MS-Exchange-CrossTenant-AuthSource": "PAXPR04MB8459.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Apr 2026 11:21:10.8634 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n mbCFFtI7uDaxmvKmnD6R4KTD6eJFVO/ZROzyt3II8pgm1df1Mj4PkiVi7T5ONfc3zHMQLjY789AXoOaT9w2SVQ==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "GVXPR04MB10756", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Peng Fan <peng.fan@nxp.com>\n\nregulator-min-microvolt in device tree is not always match the minimal\nvoltage in the pmic datasheet, direclty using the min value from device\ntree as base may cause wrong voltage settings being written.\n\nDirectly use the min_uV from datasheet to avoid wrong settings.\n\nSigned-off-by: Peng Fan <peng.fan@nxp.com>\n---\n drivers/power/regulator/pfuze100.c | 87 +++++++++++++++++++++-----------------\n 1 file changed, 48 insertions(+), 39 deletions(-)", "diff": "diff --git a/drivers/power/regulator/pfuze100.c b/drivers/power/regulator/pfuze100.c\nindex f864b1d8834..f055c610ad1 100644\n--- a/drivers/power/regulator/pfuze100.c\n+++ b/drivers/power/regulator/pfuze100.c\n@@ -19,6 +19,7 @@\n * @name: Identify name for the regulator.\n * @type: Indicates the regulator type.\n * @uV_step: Voltage increase for each selector.\n+ * @min_uV: Indicates the minimal voltage supported.\n * @vsel_reg: Register for adjust regulator voltage for normal.\n * @vsel_mask: Mask bit for setting regulator voltage for normal.\n * @stby_reg: Register for adjust regulator voltage for standby.\n@@ -30,6 +31,7 @@ struct pfuze100_regulator_desc {\n \tchar *name;\n \tenum regulator_type type;\n \tunsigned int uV_step;\n+\tunsigned int min_uV;\n \tunsigned int vsel_reg;\n \tunsigned int vsel_mask;\n \tunsigned int stby_reg;\n@@ -54,11 +56,12 @@ struct pfuze100_regulator_plat {\n \t\t.voltage\t=\t(vol),\t\t\t\t\\\n \t}\n \n-#define PFUZE100_SW_REG(_name, base, step)\t\t\t\t\\\n+#define PFUZE100_SW_REG(_name, base, step, min)\t\t\t\t\\\n \t{\t\t\t\t\t\t\t\t\\\n \t\t.name\t\t=\t#_name,\t\t\t\t\\\n \t\t.type\t\t=\tREGULATOR_TYPE_BUCK,\t\t\\\n \t\t.uV_step\t=\t(step),\t\t\t\t\\\n+\t\t.min_uV\t\t=\t(min),\t\t\t\t\\\n \t\t.vsel_reg\t=\t(base) + PFUZE100_VOL_OFFSET,\t\\\n \t\t.vsel_mask\t=\t0x3F,\t\t\t\t\\\n \t\t.stby_reg\t=\t(base) + PFUZE100_STBY_OFFSET,\t\\\n@@ -84,32 +87,35 @@ struct pfuze100_regulator_plat {\n \t\t.volt_table\t=\t(voltages),\t\t\t\\\n \t}\n \n-#define PFUZE100_VGEN_REG(_name, base, step)\t\t\t\t\\\n+#define PFUZE100_VGEN_REG(_name, base, step, min)\t\t\t\\\n \t{\t\t\t\t\t\t\t\t\\\n \t\t.name\t\t=\t#_name,\t\t\t\t\\\n \t\t.type\t\t=\tREGULATOR_TYPE_LDO,\t\t\\\n \t\t.uV_step\t=\t(step),\t\t\t\t\\\n+\t\t.min_uV\t\t=\t(min),\t\t\t\t\\\n \t\t.vsel_reg\t=\t(base),\t\t\t\t\\\n \t\t.vsel_mask\t=\t0xF,\t\t\t\t\\\n \t\t.stby_reg\t=\t(base),\t\t\t\t\\\n \t\t.stby_mask\t=\t0x20,\t\t\t\t\\\n \t}\n \n-#define PFUZE3000_VCC_REG(_name, base, step)\t\t\t\t\\\n+#define PFUZE3000_VCC_REG(_name, base, step, min)\t\t\t\\\n \t{\t\t\t\t\t\t\t\t\\\n \t\t.name\t\t=\t#_name,\t\t\t\t\\\n \t\t.type\t\t=\tREGULATOR_TYPE_LDO,\t\t\\\n \t\t.uV_step\t=\t(step),\t\t\t\t\\\n+\t\t.min_uV\t\t=\t(min),\t\t\t\t\\\n \t\t.vsel_reg\t=\t(base),\t\t\t\t\\\n \t\t.vsel_mask\t=\t0x3,\t\t\t\t\\\n \t\t.stby_reg\t=\t(base),\t\t\t\t\\\n \t\t.stby_mask\t=\t0x20,\t\t\t\t\\\n }\n \n-#define PFUZE3000_SW1_REG(_name, base, step)\t\t\t\t\\\n+#define PFUZE3000_SW1_REG(_name, base, step, min)\t\t\t\\\n \t{\t\t\t\t\t\t\t\t\\\n \t\t.name\t\t=\t#_name,\t\t\t\t\\\n \t\t.type\t\t=\tREGULATOR_TYPE_BUCK,\t\t\\\n+\t\t.min_uV\t\t=\t(min),\t\t\t\t\\\n \t\t.uV_step\t=\t(step),\t\t\t\t\\\n \t\t.vsel_reg\t=\t(base) + PFUZE100_VOL_OFFSET,\t\\\n \t\t.vsel_mask\t=\t0x1F,\t\t\t\t\\\n@@ -128,11 +134,12 @@ struct pfuze100_regulator_plat {\n \t\t.stby_mask\t=\t0x7,\t\t\t\t\\\n \t}\n \n-#define PFUZE3000_SW3_REG(_name, base, step)\t\t\t\t\\\n+#define PFUZE3000_SW3_REG(_name, base, step, min)\t\t\t\\\n \t{\t\t\t\t\t\t\t\t\\\n \t\t.name\t\t=\t#_name,\t\t\t\t\\\n \t\t.type\t\t=\tREGULATOR_TYPE_BUCK,\t\t\\\n \t\t.uV_step\t=\t(step),\t\t\t\t\\\n+\t\t.min_uV\t\t=\t(min),\t\t\t\t\\\n \t\t.vsel_reg\t=\t(base) + PFUZE100_VOL_OFFSET,\t\\\n \t\t.vsel_mask\t=\t0xF,\t\t\t\t\\\n \t\t.stby_reg\t=\t(base) + PFUZE100_STBY_OFFSET,\t\\\n@@ -157,55 +164,55 @@ static unsigned int pfuze3000_sw2lo[] = {\n \n /* PFUZE100 */\n static struct pfuze100_regulator_desc pfuze100_regulators[] = {\n-\tPFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000),\n-\tPFUZE100_SW_REG(sw1c, PFUZE100_SW1CVOL, 25000),\n-\tPFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000),\n-\tPFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000),\n-\tPFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000),\n-\tPFUZE100_SW_REG(sw4, PFUZE100_SW4VOL, 25000),\n+\tPFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000, 300000),\n+\tPFUZE100_SW_REG(sw1c, PFUZE100_SW1CVOL, 25000, 300000),\n+\tPFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000, 400000),\n+\tPFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000, 400000),\n+\tPFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000, 400000),\n+\tPFUZE100_SW_REG(sw4, PFUZE100_SW4VOL, 25000, 400000),\n \tPFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst),\n \tPFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),\n \tPFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000),\n-\tPFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000),\n-\tPFUZE100_VGEN_REG(vgen2, PFUZE100_VGEN2VOL, 50000),\n-\tPFUZE100_VGEN_REG(vgen3, PFUZE100_VGEN3VOL, 100000),\n-\tPFUZE100_VGEN_REG(vgen4, PFUZE100_VGEN4VOL, 100000),\n-\tPFUZE100_VGEN_REG(vgen5, PFUZE100_VGEN5VOL, 100000),\n-\tPFUZE100_VGEN_REG(vgen6, PFUZE100_VGEN6VOL, 100000),\n+\tPFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000, 800000),\n+\tPFUZE100_VGEN_REG(vgen2, PFUZE100_VGEN2VOL, 50000, 1800000),\n+\tPFUZE100_VGEN_REG(vgen3, PFUZE100_VGEN3VOL, 100000, 1800000),\n+\tPFUZE100_VGEN_REG(vgen4, PFUZE100_VGEN4VOL, 100000, 1800000),\n+\tPFUZE100_VGEN_REG(vgen5, PFUZE100_VGEN5VOL, 100000, 1800000),\n+\tPFUZE100_VGEN_REG(vgen6, PFUZE100_VGEN6VOL, 100000, 1800000),\n };\n \n /* PFUZE200 */\n static struct pfuze100_regulator_desc pfuze200_regulators[] = {\n-\tPFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000),\n-\tPFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000),\n-\tPFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000),\n-\tPFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000),\n+\tPFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000, 300000),\n+\tPFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000, 400000),\n+\tPFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000, 400000),\n+\tPFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000, 400000),\n \tPFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst),\n \tPFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),\n \tPFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000),\n-\tPFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000),\n-\tPFUZE100_VGEN_REG(vgen2, PFUZE100_VGEN2VOL, 50000),\n-\tPFUZE100_VGEN_REG(vgen3, PFUZE100_VGEN3VOL, 100000),\n-\tPFUZE100_VGEN_REG(vgen4, PFUZE100_VGEN4VOL, 100000),\n-\tPFUZE100_VGEN_REG(vgen5, PFUZE100_VGEN5VOL, 100000),\n-\tPFUZE100_VGEN_REG(vgen6, PFUZE100_VGEN6VOL, 100000),\n+\tPFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000, 800000),\n+\tPFUZE100_VGEN_REG(vgen2, PFUZE100_VGEN2VOL, 50000, 800000),\n+\tPFUZE100_VGEN_REG(vgen3, PFUZE100_VGEN3VOL, 100000, 1800000),\n+\tPFUZE100_VGEN_REG(vgen4, PFUZE100_VGEN4VOL, 100000, 1800000),\n+\tPFUZE100_VGEN_REG(vgen5, PFUZE100_VGEN5VOL, 100000, 1800000),\n+\tPFUZE100_VGEN_REG(vgen6, PFUZE100_VGEN6VOL, 100000, 1800000),\n };\n \n /* PFUZE3000 */\n static struct pfuze100_regulator_desc pfuze3000_regulators[] = {\n-\tPFUZE3000_SW1_REG(sw1a, PFUZE100_SW1ABVOL, 25000),\n-\tPFUZE3000_SW1_REG(sw1b, PFUZE100_SW1CVOL, 25000),\n+\tPFUZE3000_SW1_REG(sw1a, PFUZE100_SW1ABVOL, 25000, 700000),\n+\tPFUZE3000_SW1_REG(sw1b, PFUZE100_SW1CVOL, 25000, 700000),\n \tPFUZE100_SWB_REG(sw2, PFUZE100_SW2VOL, 0x7, 50000, pfuze3000_sw2lo),\n-\tPFUZE3000_SW3_REG(sw3, PFUZE100_SW3AVOL, 50000),\n+\tPFUZE3000_SW3_REG(sw3, PFUZE100_SW3AVOL, 50000, 900000),\n \tPFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst),\n \tPFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze3000_vsnvs),\n \tPFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000),\n-\tPFUZE100_VGEN_REG(vldo1, PFUZE100_VGEN1VOL, 100000),\n-\tPFUZE100_VGEN_REG(vldo2, PFUZE100_VGEN2VOL, 50000),\n-\tPFUZE3000_VCC_REG(vccsd, PFUZE100_VGEN3VOL, 150000),\n-\tPFUZE3000_VCC_REG(v33, PFUZE100_VGEN4VOL, 150000),\n-\tPFUZE100_VGEN_REG(vldo3, PFUZE100_VGEN5VOL, 100000),\n-\tPFUZE100_VGEN_REG(vldo4, PFUZE100_VGEN6VOL, 100000),\n+\tPFUZE100_VGEN_REG(vldo1, PFUZE100_VGEN1VOL, 100000, 1800000),\n+\tPFUZE100_VGEN_REG(vldo2, PFUZE100_VGEN2VOL, 50000, 800000),\n+\tPFUZE3000_VCC_REG(vccsd, PFUZE100_VGEN3VOL, 150000, 2850000),\n+\tPFUZE3000_VCC_REG(v33, PFUZE100_VGEN4VOL, 150000, 2850000),\n+\tPFUZE100_VGEN_REG(vldo3, PFUZE100_VGEN5VOL, 100000, 1800000),\n+\tPFUZE100_VGEN_REG(vldo4, PFUZE100_VGEN6VOL, 100000, 1800000),\n };\n \n #define MODE(_id, _val, _name) { \\\n@@ -436,7 +443,7 @@ static int pfuze100_regulator_enable(struct udevice *dev, int op, bool *enable)\n static int pfuze100_regulator_val(struct udevice *dev, int op, int *uV)\n {\n \tint i;\n-\tint val;\n+\tint val, min_uV;\n \tstruct pfuze100_regulator_plat *plat = dev_get_plat(dev);\n \tstruct pfuze100_regulator_desc *desc = plat->desc;\n \tstruct dm_regulator_uclass_plat *uc_pdata =\n@@ -461,7 +468,8 @@ static int pfuze100_regulator_val(struct udevice *dev, int op, int *uV)\n \t\t\tif (val < 0)\n \t\t\t\treturn val;\n \t\t\tval &= desc->vsel_mask;\n-\t\t\t*uV = uc_pdata->min_uV + (int)val * desc->uV_step;\n+\t\t\tmin_uV = desc->min_uV ?: uc_pdata->min_uV;\n+\t\t\t*uV = min_uV + (int)val * desc->uV_step;\n \t\t}\n \n \t\treturn 0;\n@@ -487,9 +495,10 @@ static int pfuze100_regulator_val(struct udevice *dev, int op, int *uV)\n \t\t\tdebug(\"Need to provide min_uV in dts.\\n\");\n \t\t\treturn -EINVAL;\n \t\t}\n+\t\tmin_uV = desc->min_uV ?: uc_pdata->min_uV;\n \t\treturn pmic_clrsetbits(dev->parent, desc->vsel_reg,\n \t\t\t\t desc->vsel_mask,\n-\t\t\t\t (*uV - uc_pdata->min_uV) / desc->uV_step);\n+\t\t\t\t (*uV - min_uV) / desc->uV_step);\n \t}\n \n \treturn 0;\n", "prefixes": [ "1/4" ] }