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GET /api/patches/2224454/?format=api
{ "id": 2224454, "url": "http://patchwork.ozlabs.org/api/patches/2224454/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260417122213.147529-4-uros.stajic@htecgroup.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417122213.147529-4-uros.stajic@htecgroup.com>", "list_archive_url": null, "date": "2026-04-17T12:25:18", "name": "[v7,3/7] gpio: Add GPIO driver for Intel EG20T", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "afdcb9074a0d1b580fcbee97a01d00d36e3b264b", "submitter": { "id": 90991, "url": "http://patchwork.ozlabs.org/api/people/90991/?format=api", "name": "Uros Stajic", "email": "uros.stajic@htecgroup.com" }, "delegate": { "id": 20174, "url": "http://patchwork.ozlabs.org/api/users/20174/?format=api", "username": "Andes", "first_name": "Andes", "last_name": "", "email": "uboot@andestech.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260417122213.147529-4-uros.stajic@htecgroup.com/mbox/", "series": [ { "id": 500329, "url": "http://patchwork.ozlabs.org/api/series/500329/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=500329", "date": "2026-04-17T12:23:32", "name": "riscv: Add support for P8700 platform on Boston board", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/500329/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224454/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224454/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=htecgroup.com header.i=@htecgroup.com\n header.a=rsa-sha256 header.s=selector1 header.b=f9d9EgAo;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-OriginatorOrg": "htecgroup.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "PA3PR09MB8140.eurprd09.prod.outlook.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 89bb30cd-c9f5-416b-9c36-08de9c7c6376", "X-MS-Exchange-CrossTenant-originalarrivaltime": "17 Apr 2026 12:25:18.9333 (UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "9f85665b-7efd-4776-9dfe-b6bfda2565ee", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n Oy/HvTM0V+cnIuVGg44czQX5LotBi13fKZVb3kRBT43sES1L/9EV9Fw0A3K8L3xQwt1WCZhRzCnUYhmdNzzdtE9TV8MNtnT+W6sF/MESYNM=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DB9PR09MB6861", "X-Mailman-Approved-At": "Fri, 17 Apr 2026 14:43:59 +0200", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Chao-ying Fu <cfu@mips.com>\n\nAdd a GPIO driver for the Intel EG20T Platform Controller Hub, which\nexposes a set of 12 GPIOs via PCI MMIO.\n\nThe driver implements basic GPIO operations (input/output direction,\nvalue read/write, and function query) using the U-Boot driver model\ninfrastructure. It maps the required BAR1 region via `dm_pci_map_bar`\nand uses internal registers to control pin state and direction.\n\nThis driver is required for platforms using EG20T, such as P8700-based\nsystems, to access GPIOs through the standard U-Boot DM GPIO framework.\n\nSigned-off-by: Chao-ying Fu <cfu@mips.com>\nSigned-off-by: Uros Stajic <uros.stajic@htecgroup.com>\n---\n board/mips/boston-riscv/MAINTAINERS | 1 +\n drivers/gpio/Kconfig | 7 ++\n drivers/gpio/Makefile | 1 +\n drivers/gpio/eg20t-gpio.c | 141 ++++++++++++++++++++++++++++\n 4 files changed, 150 insertions(+)\n create mode 100644 drivers/gpio/eg20t-gpio.c", "diff": "diff --git a/board/mips/boston-riscv/MAINTAINERS b/board/mips/boston-riscv/MAINTAINERS\nindex d03491d0f0c..8b95f53ab32 100644\n--- a/board/mips/boston-riscv/MAINTAINERS\n+++ b/board/mips/boston-riscv/MAINTAINERS\n@@ -7,3 +7,4 @@ F:\tarch/riscv/cpu/p8700/\n F:\tarch/riscv/include/asm/arch-p8700/\n F:\tconfigs/boston-p8700_defconfig\n F:\tarch/riscv/dts/boston-p8700.dts\n+F:\tdrivers/gpio/eg20t-gpio.c\ndiff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig\nindex 0b5466b39b8..94d77c0e6a6 100644\n--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -762,4 +762,11 @@ config MPFS_GPIO\n \thelp\n \t\tEnable to support the GPIO driver on Polarfire SoC\n \n+config EG20T_GPIO\n+ bool \"Intel EG20T GPIO driver\"\n+ depends on DM_GPIO && PCI\n+ help\n+ Enable this to support the GPIO controller found in the Intel EG20T\n+ Platform Controller Hub.\n+\n endif\ndiff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile\nindex 863557e45ce..729723bfe48 100644\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -82,3 +82,4 @@ obj-$(CONFIG_GPIO_SCMI)\t\t+= gpio_scmi.o\n obj-$(CONFIG_$(PHASE_)ADP5585_GPIO)\t+= adp5585_gpio.o\n obj-$(CONFIG_RZG2L_GPIO)\t+= rzg2l-gpio.o\n obj-$(CONFIG_MPFS_GPIO)\t+= mpfs_gpio.o\n+obj-$(CONFIG_EG20T_GPIO)\t+= eg20t-gpio.o\ndiff --git a/drivers/gpio/eg20t-gpio.c b/drivers/gpio/eg20t-gpio.c\nnew file mode 100644\nindex 00000000000..18dc5214c43\n--- /dev/null\n+++ b/drivers/gpio/eg20t-gpio.c\n@@ -0,0 +1,141 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright (C) 2016 Imagination Technologies\n+ */\n+\n+#include <dm.h>\n+#include <errno.h>\n+#include <log.h>\n+#include <pci.h>\n+#include <asm/io.h>\n+#include <asm/gpio.h>\n+\n+enum {\n+\tREG_IEN\t\t= 0x00,\n+\tREG_ISTATUS\t= 0x04,\n+\tREG_IDISP\t= 0x08,\n+\tREG_ICLR\t= 0x0c,\n+\tREG_IMASK\t= 0x10,\n+\tREG_IMASKCLR\t= 0x14,\n+\tREG_PO\t\t= 0x18,\n+\tREG_PI\t\t= 0x1c,\n+\tREG_PM\t\t= 0x20,\n+};\n+\n+struct eg20t_gpio_priv {\n+\tvoid *base;\n+};\n+\n+static int eg20t_gpio_get_value(struct udevice *dev, unsigned int offset)\n+{\n+\tstruct eg20t_gpio_priv *priv = dev_get_priv(dev);\n+\tu32 pm, pval;\n+\n+\tpm = readl(priv->base + REG_PM);\n+\tif ((pm >> offset) & 0x1)\n+\t\tpval = readl(priv->base + REG_PO);\n+\telse\n+\t\tpval = readl(priv->base + REG_PI);\n+\n+\treturn (pval >> offset) & 0x1;\n+}\n+\n+static int eg20t_gpio_set_value(struct udevice *dev, unsigned int offset,\n+\t\t\t\tint value)\n+{\n+\tstruct eg20t_gpio_priv *priv = dev_get_priv(dev);\n+\tu32 po;\n+\n+\tpo = readl(priv->base + REG_PO);\n+\tif (value)\n+\t\tpo |= 1 << offset;\n+\telse\n+\t\tpo &= ~(1 << offset);\n+\twritel(po, priv->base + REG_PO);\n+\n+\treturn 0;\n+}\n+\n+static int eg20t_gpio_direction_input(struct udevice *dev, unsigned int offset)\n+{\n+\tstruct eg20t_gpio_priv *priv = dev_get_priv(dev);\n+\tu32 pm;\n+\n+\tpm = readl(priv->base + REG_PM);\n+\tpm &= ~(1 << offset);\n+\twritel(pm, priv->base + REG_PM);\n+\n+\treturn 0;\n+}\n+\n+static int eg20t_gpio_direction_output(struct udevice *dev, unsigned int offset,\n+\t\t\t\t int value)\n+{\n+\tstruct eg20t_gpio_priv *priv = dev_get_priv(dev);\n+\tu32 pm;\n+\n+\tpm = readl(priv->base + REG_PM);\n+\tpm |= 1 << offset;\n+\twritel(pm, priv->base + REG_PM);\n+\n+\treturn eg20t_gpio_set_value(dev, offset, value);\n+}\n+\n+static int eg20t_gpio_get_function(struct udevice *dev, unsigned int offset)\n+{\n+\tstruct eg20t_gpio_priv *priv = dev_get_priv(dev);\n+\tu32 pm;\n+\n+\tpm = readl(priv->base + REG_PM);\n+\tif ((pm >> offset) & 0x1)\n+\t\treturn GPIOF_OUTPUT;\n+\n+\treturn GPIOF_INPUT;\n+}\n+\n+static const struct dm_gpio_ops eg20t_gpio_ops = {\n+\t.direction_input\t= eg20t_gpio_direction_input,\n+\t.direction_output\t= eg20t_gpio_direction_output,\n+\t.get_value\t\t= eg20t_gpio_get_value,\n+\t.set_value\t\t= eg20t_gpio_set_value,\n+\t.get_function\t\t= eg20t_gpio_get_function,\n+};\n+\n+static int eg20t_gpio_probe(struct udevice *dev)\n+{\n+\tstruct eg20t_gpio_priv *priv = dev_get_priv(dev);\n+\tstruct gpio_dev_priv *uc_priv = dev->uclass_priv_;\n+\n+\tpriv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, 0, 0,\n+\t\t\t\t PCI_REGION_TYPE, PCI_REGION_MEM);\n+\tif (!priv->base) {\n+\t\tdebug(\"failed to map GPIO registers\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tuc_priv->gpio_count = 12;\n+\tuc_priv->bank_name = \"eg20t\";\n+\n+\treturn 0;\n+}\n+\n+static const struct udevice_id eg20t_gpio_ids[] = {\n+\t{ .compatible = \"intel,eg20t-gpio\" },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(eg20t_gpio) = {\n+\t.name\t= \"eg20t-gpio\",\n+\t.id\t= UCLASS_GPIO,\n+\t.of_match = eg20t_gpio_ids,\n+\t.probe\t= eg20t_gpio_probe,\n+\t.priv_auto = sizeof(struct eg20t_gpio_priv),\n+\t.ops\t= &eg20t_gpio_ops,\n+};\n+\n+static struct pci_device_id eg20t_gpio_supported[] = {\n+\t{ PCI_VENDOR_ID_INTEL, 0x8803 },\n+\t{ },\n+};\n+\n+U_BOOT_PCI_DEVICE(eg20t_gpio, eg20t_gpio_supported);\n", "prefixes": [ "v7", "3/7" ] }