Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2224404/?format=api
{ "id": 2224404, "url": "http://patchwork.ozlabs.org/api/patches/2224404/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417105618.3621-22-magnuskulke@linux.microsoft.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417105618.3621-22-magnuskulke@linux.microsoft.com>", "list_archive_url": null, "date": "2026-04-17T10:56:05", "name": "[21/34] target/i386/mshv: migrate MTRR MSRs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7f9202af57db4d946560ce390922d7bd83053616", "submitter": { "id": 90753, "url": "http://patchwork.ozlabs.org/api/people/90753/?format=api", "name": "Magnus Kulke", "email": "magnuskulke@linux.microsoft.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417105618.3621-22-magnuskulke@linux.microsoft.com/mbox/", "series": [ { "id": 500310, "url": "http://patchwork.ozlabs.org/api/series/500310/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500310", "date": "2026-04-17T10:55:44", "name": "Add migration support to the MSHV accelerator", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500310/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224404/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224404/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=iT45tgHu;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxsMQ1j74z1yD3\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 Apr 2026 20:59:14 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wDgtk-00036i-4i; Fri, 17 Apr 2026 06:58:08 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <magnuskulke@linux.microsoft.com>)\n id 1wDgtX-0002es-Pd\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 06:57:57 -0400", "from linux.microsoft.com ([13.77.154.182])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <magnuskulke@linux.microsoft.com>) id 1wDgtU-0001hK-VB\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 06:57:54 -0400", "from DESKTOP-TUU1E5L.fritz.box (p5086d620.dip0.t-ipconnect.de\n [80.134.214.32])\n by linux.microsoft.com (Postfix) with ESMTPSA id CAEDA20B7128;\n Fri, 17 Apr 2026 03:57:38 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com CAEDA20B7128", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1776423461;\n bh=y23U10OHhRRPCOKznJ7K98y1+BJGjXnGiGrs7LPC2Jo=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=iT45tgHu82o/vNt+YxSiFHyX/GkHQw+W6JsL+W0ZLYNQQoE1m2eHqAhuZ86M8rzga\n NtLZiXBNuAfKuxpukA+pRE/n3otCARSNzJ2uvc3gTP/jQdd7jCllPoX56fLMpxmlbY\n 9rhH1PkR1zPzq5kT9m/mqAazOIRhDJTpnB1OnSFE=", "From": "Magnus Kulke <magnuskulke@linux.microsoft.com>", "To": "qemu-devel@nongnu.org", "Cc": "kvm@vger.kernel.org, Magnus Kulke <magnuskulke@microsoft.com>,\n Wei Liu <liuwe@microsoft.com>, \"Michael S. Tsirkin\" <mst@redhat.com>,\n\t=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,\n Zhao Liu <zhao1.liu@intel.com>,\n Richard Henderson <richard.henderson@linaro.org>,\n Paolo Bonzini <pbonzini@redhat.com>, Wei Liu <wei.liu@kernel.org>,\n Magnus Kulke <magnuskulke@linux.microsoft.com>,\n Alex Williamson <alex@shazbot.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n Marcelo Tosatti <mtosatti@redhat.com>", "Subject": "[PATCH 21/34] target/i386/mshv: migrate MTRR MSRs", "Date": "Fri, 17 Apr 2026 12:56:05 +0200", "Message-Id": "<20260417105618.3621-22-magnuskulke@linux.microsoft.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260417105618.3621-1-magnuskulke@linux.microsoft.com>", "References": "<20260417105618.3621-1-magnuskulke@linux.microsoft.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=13.77.154.182;\n envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com", "X-Spam_score_int": "-42", "X-Spam_score": "-4.3", "X-Spam_bar": "----", "X-Spam_report": "(-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This change roundtrips memory access/caching MSRs. The mapping scheme\nis a bit more elaborate on these, so we have added a special handling\ninstead of individual entries in the MSR mapping table.\n\nSigned-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com>\n---\n target/i386/mshv/msr.c | 136 ++++++++++++++++++++++++++++++++++++++---\n 1 file changed, 129 insertions(+), 7 deletions(-)", "diff": "diff --git a/target/i386/mshv/msr.c b/target/i386/mshv/msr.c\nindex 0ecd864458..b26375e4c2 100644\n--- a/target/i386/mshv/msr.c\n+++ b/target/i386/mshv/msr.c\n@@ -79,6 +79,10 @@ static const MshvMsrEnvMap msr_env_map[] = {\n { HV_X64_MSR_SIMP, HV_REGISTER_SIMP,\n offsetof(CPUX86State, msr_hv_synic_msg_page) },\n \n+ /* MTRR default type */\n+ { IA32_MSR_MTRR_DEF_TYPE, HV_X64_REGISTER_MSR_MTRR_DEF_TYPE,\n+ offsetof(CPUX86State, mtrr_deftype) },\n+\n /* Other */\n \n /* TODO: find out processor features that correlate to unsupported MSRs. */\n@@ -90,6 +94,98 @@ static const MshvMsrEnvMap msr_env_map[] = {\n offsetof(CPUX86State, spec_ctrl) },\n };\n \n+/*\n+ * The assocs have to be set according to this schema:\n+ * 8 entries for 0-7 mtrr_base\n+ * 8 entries for mtrr_mask 0-7\n+ * 11 entries for 1 x 64k, 2 x 16k, 8 x 4k fixed MTRR\n+ * 27 total entries\n+ */\n+\n+#define MSHV_MTRR_MSR_COUNT 27\n+#define MSHV_MSR_TOTAL_COUNT (ARRAY_SIZE(msr_env_map) + MSHV_MTRR_MSR_COUNT)\n+\n+static void store_in_env_mtrr_phys(CPUState *cpu,\n+ const struct hv_register_assoc *assocs,\n+ size_t n_assocs)\n+{\n+ X86CPU *x86_cpu = X86_CPU(cpu);\n+ CPUX86State *env = &x86_cpu->env;\n+ size_t i, fixed_offset;\n+ hv_register_name hv_name;\n+ uint64_t base, mask;\n+\n+ assert(n_assocs == MSHV_MTRR_MSR_COUNT);\n+\n+ for (i = 0; i < MSR_MTRRcap_VCNT; i++) {\n+ hv_name = HV_X64_REGISTER_MSR_MTRR_PHYS_BASE0 + i;\n+ assert(assocs[i].name == hv_name);\n+ hv_name = HV_X64_REGISTER_MSR_MTRR_PHYS_MASK0 + i;\n+ assert(assocs[i + MSR_MTRRcap_VCNT].name == hv_name);\n+\n+ base = assocs[i].value.reg64;\n+ mask = assocs[i + MSR_MTRRcap_VCNT].value.reg64;\n+ env->mtrr_var[i].base = base;\n+ env->mtrr_var[i].mask = mask;\n+ }\n+\n+ /* fixed 1x 64, 2x 16, 8x 4 kB */\n+ fixed_offset = MSR_MTRRcap_VCNT * 2;\n+ for (i = 0; i < 11; i++) {\n+ hv_name = HV_X64_REGISTER_MSR_MTRR_FIX64K00000 + i;\n+ assert(assocs[fixed_offset + i].name == hv_name);\n+ env->mtrr_fixed[i] = assocs[fixed_offset + i].value.reg64;\n+ }\n+}\n+\n+/*\n+ * The assocs have to be set according to this schema:\n+ * 8 entries for 0-7 mtrr_base\n+ * 8 entries for mtrr_mask 0-7\n+ * 11 entries for 1 x 64k, 2 x 16k, 8 x 4k fixed MTRR\n+ * 27 total entries\n+ */\n+static void load_from_env_mtrr_phys(const CPUState *cpu,\n+ struct hv_register_assoc *assocs,\n+ size_t n_assocs)\n+{\n+ X86CPU *x86_cpu = X86_CPU(cpu);\n+ CPUX86State *env = &x86_cpu->env;\n+ size_t i, fixed_offset;\n+ uint64_t base, mask, fixed_value;\n+ hv_register_name base_name, mask_name, fixed_name;\n+ hv_register_assoc *assoc;\n+\n+ assert(n_assocs == MSHV_MTRR_MSR_COUNT);\n+\n+ for (i = 0; i < MSR_MTRRcap_VCNT; i++) {\n+ base = env->mtrr_var[i].base;\n+ mask = env->mtrr_var[i].mask;\n+\n+ base_name = HV_X64_REGISTER_MSR_MTRR_PHYS_BASE0 + i;\n+ mask_name = HV_X64_REGISTER_MSR_MTRR_PHYS_MASK0 + i;\n+\n+ assoc = &assocs[i];\n+ assoc->name = base_name;\n+ assoc->value.reg64 = base;\n+\n+ assoc = &assocs[i + MSR_MTRRcap_VCNT];\n+ assoc->name = mask_name;\n+ assoc->value.reg64 = mask;\n+ }\n+\n+ /* fixed 1x 64, 2x 16, 8x 4 kB */\n+ fixed_offset = MSR_MTRRcap_VCNT * 2;\n+ for (i = 0; i < 11; i++) {\n+ fixed_name = HV_X64_REGISTER_MSR_MTRR_FIX64K00000 + i;\n+ fixed_value = env->mtrr_fixed[i];\n+\n+ assoc = &assocs[fixed_offset + i];\n+ assoc->name = fixed_name;\n+ assoc->value.reg64 = fixed_value;\n+ }\n+}\n+\n int mshv_init_msrs(const CPUState *cpu)\n {\n int ret;\n@@ -131,8 +227,9 @@ static void store_in_env(CPUState *cpu, const struct hv_register_assoc *assocs,\n union hv_register_value hv_value;\n ptrdiff_t offset;\n uint32_t hv_name;\n+ size_t mtrr_index;\n \n- assert(n_assocs <= (ARRAY_SIZE(msr_env_map)));\n+ assert(n_assocs <= MSHV_MSR_TOTAL_COUNT);\n \n for (i = 0, j = 0; i < ARRAY_SIZE(msr_env_map); i++) {\n hv_name = assocs[j].name;\n@@ -146,17 +243,38 @@ static void store_in_env(CPUState *cpu, const struct hv_register_assoc *assocs,\n MSHV_ENV_FIELD(env, offset) = hv_value.reg64;\n j++;\n }\n+\n+ mtrr_index = j;\n+ store_in_env_mtrr_phys(cpu, &assocs[mtrr_index], MSHV_MTRR_MSR_COUNT);\n }\n \n static void set_hv_name_in_assocs(struct hv_register_assoc *assocs,\n size_t n_assocs)\n {\n size_t i;\n+ size_t mtrr_offset, mtrr_fixed_offset;\n+ hv_register_name hv_name;\n+\n+ assert(n_assocs == MSHV_MSR_TOTAL_COUNT);\n \n- assert(n_assocs == ARRAY_SIZE(msr_env_map));\n for (i = 0; i < ARRAY_SIZE(msr_env_map); i++) {\n assocs[i].name = msr_env_map[i].hv_name;\n }\n+\n+ mtrr_offset = ARRAY_SIZE(msr_env_map);\n+ for (i = 0; i < MSR_MTRRcap_VCNT; i++) {\n+ hv_name = HV_X64_REGISTER_MSR_MTRR_PHYS_BASE0 + i;\n+ assocs[mtrr_offset + i].name = hv_name;\n+ hv_name = HV_X64_REGISTER_MSR_MTRR_PHYS_MASK0 + i;\n+ assocs[mtrr_offset + MSR_MTRRcap_VCNT + i].name = hv_name;\n+ }\n+\n+ /* fixed 1x 64, 2x 16, 8x 4 kB */\n+ mtrr_fixed_offset = mtrr_offset + MSR_MTRRcap_VCNT * 2;\n+ for (i = 0; i < 11; i++) {\n+ hv_name = HV_X64_REGISTER_MSR_MTRR_FIX64K00000 + i;\n+ assocs[mtrr_fixed_offset + i].name = hv_name;\n+ }\n }\n \n static bool msr_supported(uint32_t name)\n@@ -181,8 +299,8 @@ static bool msr_supported(uint32_t name)\n int mshv_get_msrs(CPUState *cpu)\n {\n int ret = 0;\n- size_t n_assocs = ARRAY_SIZE(msr_env_map);\n- struct hv_register_assoc assocs[ARRAY_SIZE(msr_env_map)];\n+ size_t n_assocs = MSHV_MSR_TOTAL_COUNT;\n+ struct hv_register_assoc assocs[MSHV_MSR_TOTAL_COUNT];\n size_t i, j;\n uint32_t name;\n \n@@ -223,8 +341,9 @@ static void load_from_env(const CPUState *cpu, struct hv_register_assoc *assocs,\n CPUX86State *env = &x86_cpu->env;\n ptrdiff_t offset;\n union hv_register_value *hv_value;\n+ size_t mtrr_offset;\n \n- assert(n_assocs == ARRAY_SIZE(msr_env_map));\n+ assert(n_assocs == MSHV_MSR_TOTAL_COUNT);\n \n for (i = 0; i < ARRAY_SIZE(msr_env_map); i++) {\n mapping = &msr_env_map[i];\n@@ -233,12 +352,15 @@ static void load_from_env(const CPUState *cpu, struct hv_register_assoc *assocs,\n hv_value = &assocs[i].value;\n hv_value->reg64 = MSHV_ENV_FIELD(env, offset);\n }\n+\n+ mtrr_offset = ARRAY_SIZE(msr_env_map);\n+ load_from_env_mtrr_phys(cpu, &assocs[mtrr_offset], MSHV_MTRR_MSR_COUNT);\n }\n \n int mshv_set_msrs(const CPUState *cpu)\n {\n- size_t n_assocs = ARRAY_SIZE(msr_env_map);\n- struct hv_register_assoc assocs[ARRAY_SIZE(msr_env_map)];\n+ size_t n_assocs = MSHV_MSR_TOTAL_COUNT;\n+ struct hv_register_assoc assocs[MSHV_MSR_TOTAL_COUNT];\n int ret;\n size_t i, j;\n \n", "prefixes": [ "21/34" ] }