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GET /api/patches/2224382/?format=api
{ "id": 2224382, "url": "http://patchwork.ozlabs.org/api/patches/2224382/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417105618.3621-3-magnuskulke@linux.microsoft.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417105618.3621-3-magnuskulke@linux.microsoft.com>", "list_archive_url": null, "date": "2026-04-17T10:55:46", "name": "[02/34] target/i386/mshv: use generic FPU/xcr0 state", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f6bbbfee343fddb08ea379ae843aa7c22b9c7821", "submitter": { "id": 90753, "url": "http://patchwork.ozlabs.org/api/people/90753/?format=api", "name": "Magnus Kulke", "email": "magnuskulke@linux.microsoft.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417105618.3621-3-magnuskulke@linux.microsoft.com/mbox/", "series": [ { "id": 500310, "url": "http://patchwork.ozlabs.org/api/series/500310/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500310", "date": "2026-04-17T10:55:44", "name": "Add migration support to the MSHV accelerator", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500310/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224382/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224382/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=WW6lXpiZ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxsKm4HBBz1yD3\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 Apr 2026 20:57:48 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wDgsG-0000KV-Be; Fri, 17 Apr 2026 06:56:36 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <magnuskulke@linux.microsoft.com>)\n id 1wDgsE-0000KI-MD\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 06:56:34 -0400", "from linux.microsoft.com ([13.77.154.182])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <magnuskulke@linux.microsoft.com>) id 1wDgsC-0001NJ-Ud\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 06:56:34 -0400", "from DESKTOP-TUU1E5L.fritz.box (p5086d620.dip0.t-ipconnect.de\n [80.134.214.32])\n by linux.microsoft.com (Postfix) with ESMTPSA id 08B5520B712B;\n Fri, 17 Apr 2026 03:56:28 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com 08B5520B712B", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1776423391;\n bh=YCyjkeVZjehmvMqQkFEvROL42xs/v9qbwCcFiaYqzZg=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=WW6lXpiZ5ztwWAzYMi8+dtuwB9y949MCfQCX38vw3l+U4W4YJ2SGBTAp855NjeSbD\n XhCStMIDj0zqzXoBfiMs84yW1P5ofQyvvAU/JLbI2EO67M1qIIu/YMZCRKc0AdKonQ\n 06xwyRay3IWObgsVJpGwL1w7Wca9b0tTJ/5gtE0c=", "From": "Magnus Kulke <magnuskulke@linux.microsoft.com>", "To": "qemu-devel@nongnu.org", "Cc": "kvm@vger.kernel.org, Magnus Kulke <magnuskulke@microsoft.com>,\n Wei Liu <liuwe@microsoft.com>, \"Michael S. Tsirkin\" <mst@redhat.com>,\n\t=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,\n Zhao Liu <zhao1.liu@intel.com>,\n Richard Henderson <richard.henderson@linaro.org>,\n Paolo Bonzini <pbonzini@redhat.com>, Wei Liu <wei.liu@kernel.org>,\n Magnus Kulke <magnuskulke@linux.microsoft.com>,\n Alex Williamson <alex@shazbot.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n Marcelo Tosatti <mtosatti@redhat.com>", "Subject": "[PATCH 02/34] target/i386/mshv: use generic FPU/xcr0 state", "Date": "Fri, 17 Apr 2026 12:55:46 +0200", "Message-Id": "<20260417105618.3621-3-magnuskulke@linux.microsoft.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260417105618.3621-1-magnuskulke@linux.microsoft.com>", "References": "<20260417105618.3621-1-magnuskulke@linux.microsoft.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=13.77.154.182;\n envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com", "X-Spam_score_int": "-42", "X-Spam_score": "-4.3", "X-Spam_bar": "----", "X-Spam_report": "(-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Instead of using an mshv-specific FPU state representation we switch to\nthe generic i386 representation of the registers.\n\nSigned-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com>\n---\n include/system/mshv_int.h | 15 +-------\n target/i386/mshv/mshv-cpu.c | 76 ++++++++++++++++++++++---------------\n 2 files changed, 47 insertions(+), 44 deletions(-)", "diff": "diff --git a/include/system/mshv_int.h b/include/system/mshv_int.h\nindex a142dd241a..e3d1867a77 100644\n--- a/include/system/mshv_int.h\n+++ b/include/system/mshv_int.h\n@@ -58,19 +58,6 @@ typedef struct MshvMsiControl {\n #define mshv_vcpufd(cpu) (cpu->accel->cpufd)\n \n /* cpu */\n-typedef struct MshvFPU {\n- uint8_t fpr[8][16];\n- uint16_t fcw;\n- uint16_t fsw;\n- uint8_t ftwx;\n- uint8_t pad1;\n- uint16_t last_opcode;\n- uint64_t last_ip;\n- uint64_t last_dp;\n- uint8_t xmm[16][16];\n- uint32_t mxcsr;\n- uint32_t pad2;\n-} MshvFPU;\n \n typedef enum MshvVmExit {\n MshvVmExitIgnore = 0,\n@@ -81,7 +68,7 @@ typedef enum MshvVmExit {\n void mshv_init_mmio_emu(void);\n int mshv_create_vcpu(int vm_fd, uint8_t vp_index, int *cpu_fd);\n void mshv_remove_vcpu(int vm_fd, int cpu_fd);\n-int mshv_configure_vcpu(const CPUState *cpu, const MshvFPU *fpu, uint64_t xcr0);\n+int mshv_configure_vcpu(const CPUState *cpu);\n int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message *msg, MshvVmExit *exit);\n int mshv_arch_load_regs(CPUState *cpu);\n int mshv_arch_store_regs(CPUState *cpu);\ndiff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c\nindex 9456e75277..78b218e596 100644\n--- a/target/i386/mshv/mshv-cpu.c\n+++ b/target/i386/mshv/mshv-cpu.c\n@@ -108,6 +108,9 @@ static enum hv_register_name FPU_REGISTER_NAMES[26] = {\n };\n \n static int set_special_regs(const CPUState *cpu);\n+static int get_generic_regs(CPUState *cpu,\n+ struct hv_register_assoc *assocs,\n+ size_t n_regs);\n \n static int translate_gva(const CPUState *cpu, uint64_t gva, uint64_t *gpa,\n uint64_t flags)\n@@ -717,48 +720,65 @@ static int set_special_regs(const CPUState *cpu)\n return 0;\n }\n \n-static int set_fpu(const CPUState *cpu, const struct MshvFPU *regs)\n+static int set_fpu(const CPUState *cpu)\n {\n struct hv_register_assoc assocs[ARRAY_SIZE(FPU_REGISTER_NAMES)];\n union hv_register_value *value;\n- size_t fp_i;\n union hv_x64_fp_control_status_register *ctrl_status;\n union hv_x64_xmm_control_status_register *xmm_ctrl_status;\n int ret;\n size_t n_regs = ARRAY_SIZE(FPU_REGISTER_NAMES);\n+ X86CPU *x86cpu = X86_CPU(cpu);\n+ CPUX86State *env = &x86cpu->env;\n+ size_t i, fp_i;\n+ bool valid;\n \n /* first 16 registers are xmm0-xmm15 */\n- for (size_t i = 0; i < 16; i++) {\n+ for (i = 0; i < 16; i++) {\n assocs[i].name = FPU_REGISTER_NAMES[i];\n value = &assocs[i].value;\n- memcpy(&value->reg128, ®s->xmm[i], 16);\n+ value->reg128.low_part = env->xmm_regs[i].ZMM_Q(0);\n+ value->reg128.high_part = env->xmm_regs[i].ZMM_Q(1);\n }\n \n /* next 8 registers are fp_mmx0-fp_mmx7 */\n- for (size_t i = 16; i < 24; i++) {\n- assocs[i].name = FPU_REGISTER_NAMES[i];\n+ for (i = 16; i < 24; i++) {\n fp_i = (i - 16);\n+ assocs[i].name = FPU_REGISTER_NAMES[i];\n value = &assocs[i].value;\n- memcpy(&value->reg128, ®s->fpr[fp_i], 16);\n+ value->fp.mantissa = env->fpregs[fp_i].d.low;\n+ value->fp.biased_exponent = env->fpregs[fp_i].d.high & 0x7FFF;\n+ value->fp.sign = (env->fpregs[fp_i].d.high >> 15) & 0x1;\n+ value->fp.reserved = 0;\n }\n \n /* last two registers are fp_control_status and xmm_control_status */\n assocs[24].name = FPU_REGISTER_NAMES[24];\n value = &assocs[24].value;\n ctrl_status = &value->fp_control_status;\n- ctrl_status->fp_control = regs->fcw;\n- ctrl_status->fp_status = regs->fsw;\n- ctrl_status->fp_tag = regs->ftwx;\n+\n+ ctrl_status->fp_control = env->fpuc;\n+ /* bits 11,12,13 are the top of stack pointer */\n+ ctrl_status->fp_status = (env->fpus & ~0x3800) | ((env->fpstt & 0x7) << 11);\n+\n+ ctrl_status->fp_tag = 0;\n+ for (i = 0; i < 8; i++) {\n+ valid = (env->fptags[i] == 0);\n+ if (valid) {\n+ ctrl_status->fp_tag |= (1u << i);\n+ }\n+ }\n+\n ctrl_status->reserved = 0;\n- ctrl_status->last_fp_op = regs->last_opcode;\n- ctrl_status->last_fp_rip = regs->last_ip;\n+ ctrl_status->last_fp_op = env->fpop;\n+ ctrl_status->last_fp_rip = env->fpip;\n \n assocs[25].name = FPU_REGISTER_NAMES[25];\n value = &assocs[25].value;\n xmm_ctrl_status = &value->xmm_control_status;\n- xmm_ctrl_status->xmm_status_control = regs->mxcsr;\n- xmm_ctrl_status->xmm_status_control_mask = 0;\n- xmm_ctrl_status->last_fp_rdp = regs->last_dp;\n+ xmm_ctrl_status->xmm_status_control = env->mxcsr;\n+ xmm_ctrl_status->xmm_status_control_mask = 0x0000ffff;\n+ xmm_ctrl_status->last_fp_rdp = env->fpdp;\n \n ret = mshv_set_generic_regs(cpu, assocs, n_regs);\n if (ret < 0) {\n@@ -769,12 +789,15 @@ static int set_fpu(const CPUState *cpu, const struct MshvFPU *regs)\n return 0;\n }\n \n-static int set_xc_reg(const CPUState *cpu, uint64_t xcr0)\n+static int set_xc_reg(const CPUState *cpu)\n {\n int ret;\n+ X86CPU *x86cpu = X86_CPU(cpu);\n+ CPUX86State *env = &x86cpu->env;\n+\n struct hv_register_assoc assoc = {\n .name = HV_X64_REGISTER_XFEM,\n- .value.reg64 = xcr0,\n+ .value.reg64 = env->xcr0,\n };\n \n ret = mshv_set_generic_regs(cpu, &assoc, 1);\n@@ -785,8 +808,7 @@ static int set_xc_reg(const CPUState *cpu, uint64_t xcr0)\n return 0;\n }\n \n-static int set_cpu_state(const CPUState *cpu, const MshvFPU *fpu_regs,\n- uint64_t xcr0)\n+static int set_cpu_state(const CPUState *cpu)\n {\n int ret;\n \n@@ -798,11 +820,11 @@ static int set_cpu_state(const CPUState *cpu, const MshvFPU *fpu_regs,\n if (ret < 0) {\n return ret;\n }\n- ret = set_fpu(cpu, fpu_regs);\n+ ret = set_fpu(cpu);\n if (ret < 0) {\n return ret;\n }\n- ret = set_xc_reg(cpu, xcr0);\n+ ret = set_xc_reg(cpu);\n if (ret < 0) {\n return ret;\n }\n@@ -951,8 +973,7 @@ static int setup_msrs(const CPUState *cpu)\n * CPUX86State *env = &x86cpu->env;\n * X86CPUTopoInfo *topo_info = &env->topo_info;\n */\n-int mshv_configure_vcpu(const CPUState *cpu, const struct MshvFPU *fpu,\n- uint64_t xcr0)\n+int mshv_configure_vcpu(const CPUState *cpu)\n {\n int ret;\n int cpu_fd = mshv_vcpufd(cpu);\n@@ -969,7 +990,7 @@ int mshv_configure_vcpu(const CPUState *cpu, const struct MshvFPU *fpu,\n return -1;\n }\n \n- ret = set_cpu_state(cpu, fpu, xcr0);\n+ ret = set_cpu_state(cpu);\n if (ret < 0) {\n error_report(\"failed to set cpu state\");\n return -1;\n@@ -986,14 +1007,9 @@ int mshv_configure_vcpu(const CPUState *cpu, const struct MshvFPU *fpu,\n \n static int put_regs(const CPUState *cpu)\n {\n- X86CPU *x86cpu = X86_CPU(cpu);\n- CPUX86State *env = &x86cpu->env;\n- MshvFPU fpu = {0};\n int ret;\n \n- memset(&fpu, 0, sizeof(fpu));\n-\n- ret = mshv_configure_vcpu(cpu, &fpu, env->xcr0);\n+ ret = mshv_configure_vcpu(cpu);\n if (ret < 0) {\n error_report(\"failed to configure vcpu\");\n return ret;\n", "prefixes": [ "02/34" ] }