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GET /api/patches/2224348/?format=api
{ "id": 2224348, "url": "http://patchwork.ozlabs.org/api/patches/2224348/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417100302.162260-4-djordje.todorovic@htecgroup.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417100302.162260-4-djordje.todorovic@htecgroup.com>", "list_archive_url": null, "date": "2026-04-17T10:03:11", "name": "[v7,3/6] target/riscv: Implement runtime data endianness via MSTATUS bits", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c8587abc5fc822e12904ee16da308660eabb9672", "submitter": { "id": 90738, "url": "http://patchwork.ozlabs.org/api/people/90738/?format=api", "name": "Djordje Todorovic", "email": "Djordje.Todorovic@htecgroup.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417100302.162260-4-djordje.todorovic@htecgroup.com/mbox/", "series": [ { "id": 500299, "url": "http://patchwork.ozlabs.org/api/series/500299/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500299", "date": "2026-04-17T10:03:08", "name": "Add RISC-V big-endian target support", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/500299/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224348/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224348/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=htecgroup.com header.i=@htecgroup.com\n header.a=rsa-sha256 header.s=selector1 header.b=nahxjx57;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=Oay11mJt144P7M4ouoSi8o0A0Ae8BlhXt3WQoUaRJI4=;\n b=HHnSxKCHkEGXqwGHJb2e3bhKASZM/Pir/QDNmAAeiYTeOhoIULygJHwL5ANAyydSsnLJ0OXt2RcaETaMYBWktvTWEottO1GVaop5TgF+Or1LNAyQ4u/9oPvhZhG0tIcxdGN7+6mVZUi1tLVlQsmDs5vftcOwCC4qqXWOnjrs9JoZP7B714DwOSzS2d9P4UmaUoOb7/eRO3Q+kBQab3PrP0BYC5SqIJYqbIcIl8fA3QCBlryCnVvFqJvoCo2kzfVX6kzhcX8J2kIZeqZOINlaYietPCfckBIyBEtnwZ9SscAFm93H7U4+ruJcqSypGKuuGP+o2CnZMJ0OOXjjH8B1FQ==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=htecgroup.com; dmarc=pass action=none\n header.from=htecgroup.com; dkim=pass header.d=htecgroup.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=htecgroup.com;\n s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=Oay11mJt144P7M4ouoSi8o0A0Ae8BlhXt3WQoUaRJI4=;\n b=nahxjx57r94U5ByrJxvxe4chcrrhdJ6ERW9VywMs+m096Fe318pcjhnCmWjiszEvFQi+oail+OSRtVo7Mt/rwtwNr8/VxT+GtUvd2c+FSly8EolWAxXR0M4jWxAWmmLRbgNPetnO3L+ojpQ0GciE58Ta6Lr0LqgJlF/ROh+P87gaYmfCs3V8f1zpUdJck2H8wx35teKOJUeLzEBsW30P8uep2HnxDPrAR7htwf3b6pFmnZ+Wvg9IjZZu9V5DA+g7LJTqIyLd8FYtk5PPLvIdVwATnsEIPoCdDgaDq2DlQtjEhhua+6iPt3bfABpgkw02LakLRCte5DmqugLwdaRSnA==", "From": "Djordje Todorovic <Djordje.Todorovic@htecgroup.com>", "To": "\"qemu-devel@nongnu.org\" <qemu-devel@nongnu.org>", "CC": "\"qemu-riscv@nongnu.org\" <qemu-riscv@nongnu.org>, \"cfu@mips.com\"\n <cfu@mips.com>, \"mst@redhat.com\" <mst@redhat.com>,\n \"marcel.apfelbaum@gmail.com\" <marcel.apfelbaum@gmail.com>,\n \"dbarboza@ventanamicro.com\" <dbarboza@ventanamicro.com>, \"philmd@linaro.org\"\n <philmd@linaro.org>, \"alistair23@gmail.com\" <alistair23@gmail.com>,\n \"thuth@redhat.com\" <thuth@redhat.com>, Djordje Todorovic\n <Djordje.Todorovic@htecgroup.com>", "Subject": "[PATCH v7 3/6] target/riscv: Implement runtime data endianness via\n MSTATUS bits", "Thread-Topic": "[PATCH v7 3/6] target/riscv: Implement runtime data endianness\n via MSTATUS bits", "Thread-Index": "AQHczlFlihUusYngh02OWnt1bDc+5A==", "Date": "Fri, 17 Apr 2026 10:03:11 +0000", "Message-ID": "<20260417100302.162260-4-djordje.todorovic@htecgroup.com>", "References": "<20260417100302.162260-1-djordje.todorovic@htecgroup.com>", "In-Reply-To": "<20260417100302.162260-1-djordje.todorovic@htecgroup.com>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "authentication-results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=htecgroup.com header.i=@htecgroup.com\n header.a=rsa-sha256 header.s=selector1 header.b=nahxjx57;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-OriginatorOrg": "htecgroup.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "PA2PR09MB7634.eurprd09.prod.outlook.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n d8b61dbd-ebb4-4183-2315-08de9c68886d", "X-MS-Exchange-CrossTenant-originalarrivaltime": "17 Apr 2026 10:03:11.2190 (UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "9f85665b-7efd-4776-9dfe-b6bfda2565ee", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n Msgjr/urgF7JDkFcGjYS704QoB1VpPhhK+fec4lEdA8JtI2StOXw/oOv3z9k3DypFWv3prakSqL+YkIAfEVIgrQavksLRA8o45qB0jcG9OQ=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM7PR09MB3736", "Received-SPF": "pass client-ip=2a01:111:f403:c200::1;\n envelope-from=Djordje.Todorovic@htecgroup.com;\n helo=DB3PR0202CU003.outbound.protection.outlook.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Make data accesses honour the MSTATUS MBE/SBE/UBE endianness bits\ninstead of being hardcoded to little-endian. A new helper,\nriscv_cpu_data_is_big_endian(), picks the bit corresponding to the\ncurrent privilege level (MBE for M, SBE for S, UBE for U). The\nexisting mo_endian_env() wrapper in internals.h now returns MO_BE or\nMO_LE based on that helper, so the hypervisor load/store helpers in\nop_helper.c pick up the runtime endianness automatically.\n\nOn the translator side, DisasContext gains a mo_endianness field\nholding MO_BE or MO_LE, which the generated load/store ops OR into\ntheir MemOp. The trivial mo_endian() wrapper is dropped and call\nsites reference ctx->mo_endianness directly.\n\nTB_FLAGS has no free bits, so the endianness is carried into the\ntranslator through bit 32 of cs_base (alongside misa_ext in bits\n0-25). This keys TBs correctly on the current data endianness. The\ncs_base comment in include/exec/translation-block.h is updated to\ndocument the RISC-V usage.\n\nInstruction fetches remain MO_LE unconditionally; RISC-V instructions\nare always little-endian per the ISA specification.\n\nSigned-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>\n---\n include/exec/translation-block.h | 3 +-\n target/riscv/cpu.h | 28 +++++++++++++++++++\n target/riscv/insn_trans/trans_rva.c.inc | 4 +--\n target/riscv/insn_trans/trans_rvd.c.inc | 4 +--\n target/riscv/insn_trans/trans_rvf.c.inc | 4 +--\n target/riscv/insn_trans/trans_rvi.c.inc | 8 +++---\n target/riscv/insn_trans/trans_rvzacas.c.inc | 4 +--\n target/riscv/insn_trans/trans_rvzalasr.c.inc | 4 +--\n target/riscv/insn_trans/trans_rvzce.c.inc | 4 +--\n target/riscv/insn_trans/trans_rvzfh.c.inc | 4 +--\n target/riscv/insn_trans/trans_rvzicfiss.c.inc | 4 +--\n target/riscv/insn_trans/trans_xmips.c.inc | 8 +++---\n target/riscv/insn_trans/trans_xthead.c.inc | 16 +++++------\n target/riscv/insn_trans/trans_zilsd.c.inc | 4 +--\n target/riscv/internals.h | 9 +-----\n target/riscv/tcg/tcg-cpu.c | 7 ++++-\n target/riscv/translate.c | 22 +++++----------\n 17 files changed, 78 insertions(+), 59 deletions(-)", "diff": "diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h\nindex 4f83d5bec9..66068c61a3 100644\n--- a/include/exec/translation-block.h\n+++ b/include/exec/translation-block.h\n@@ -64,7 +64,8 @@ struct TranslationBlock {\n * x86: the original user, the Code Segment virtual base,\n * arm: an extension of tb->flags,\n * s390x: instruction data for EXECUTE,\n- * sparc: the next pc of the instruction queue (for delay slots).\n+ * sparc: the next pc of the instruction queue (for delay slots),\n+ * riscv: misa_ext in bits 0-25, data endianness in bit 32.\n */\n uint64_t cs_base;\n \ndiff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 35d1f6362c..ef870d05b3 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -703,6 +703,12 @@ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1)\n FIELD(TB_FLAGS, PM_PMM, 29, 2)\n FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1)\n \n+/*\n+ * cs_base carries misa_ext (bits 0-25) plus additional flags.\n+ * Bit 32 is used for data endianness since TB_FLAGS has no free bits.\n+ */\n+#define TB_CSBASE_BIG_ENDIAN (1ULL << 32)\n+\n #ifdef TARGET_RISCV32\n #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)\n #else\n@@ -718,6 +724,28 @@ static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env)\n return &env_archcpu(env)->cfg;\n }\n \n+/*\n+ * Return true if data accesses are big-endian for the current privilege\n+ * level, based on the MSTATUS MBE/SBE/UBE bits.\n+ */\n+static inline bool riscv_cpu_data_is_big_endian(CPURISCVState *env)\n+{\n+#if defined(CONFIG_USER_ONLY)\n+ return false;\n+#else\n+ switch (env->priv) {\n+ case PRV_M:\n+ return env->mstatus & MSTATUS_MBE;\n+ case PRV_S:\n+ return env->mstatus & MSTATUS_SBE;\n+ case PRV_U:\n+ return env->mstatus & MSTATUS_UBE;\n+ default:\n+ g_assert_not_reached();\n+ }\n+#endif\n+}\n+\n #if !defined(CONFIG_USER_ONLY)\n static inline int cpu_address_mode(CPURISCVState *env)\n {\ndiff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc\nindex a7a3278d24..6597ae8bb7 100644\n--- a/target/riscv/insn_trans/trans_rva.c.inc\n+++ b/target/riscv/insn_trans/trans_rva.c.inc\n@@ -35,7 +35,7 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)\n TCGv src1;\n \n mop |= MO_ALIGN;\n- mop |= mo_endian(ctx);\n+ mop |= ctx->mo_endianness;\n \n decode_save_opc(ctx, 0);\n src1 = get_address(ctx, a->rs1, 0);\n@@ -65,7 +65,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)\n TCGLabel *l2 = gen_new_label();\n \n mop |= MO_ALIGN;\n- mop |= mo_endian(ctx);\n+ mop |= ctx->mo_endianness;\n \n decode_save_opc(ctx, 0);\n src1 = get_address(ctx, a->rs1, 0);\ndiff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc\nindex ffea0c2a1f..3b9a745520 100644\n--- a/target/riscv/insn_trans/trans_rvd.c.inc\n+++ b/target/riscv/insn_trans/trans_rvd.c.inc\n@@ -60,7 +60,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)\n } else {\n memop |= MO_ATOM_IFALIGN;\n }\n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n \n decode_save_opc(ctx, 0);\n addr = get_address(ctx, a->rs1, a->imm);\n@@ -85,7 +85,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)\n } else {\n memop |= MO_ATOM_IFALIGN;\n }\n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n \n decode_save_opc(ctx, 0);\n addr = get_address(ctx, a->rs1, a->imm);\ndiff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc\nindex 89fb0f604a..e935523c93 100644\n--- a/target/riscv/insn_trans/trans_rvf.c.inc\n+++ b/target/riscv/insn_trans/trans_rvf.c.inc\n@@ -48,7 +48,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)\n REQUIRE_FPU;\n REQUIRE_EXT(ctx, RVF);\n \n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n if (ctx->cfg_ptr->ext_zama16b) {\n memop |= MO_ATOM_WITHIN16;\n }\n@@ -71,7 +71,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)\n REQUIRE_FPU;\n REQUIRE_EXT(ctx, RVF);\n \n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n if (ctx->cfg_ptr->ext_zama16b) {\n memop |= MO_ATOM_WITHIN16;\n }\ndiff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc\nindex 2c82ae41a7..2de74fac3a 100644\n--- a/target/riscv/insn_trans/trans_rvi.c.inc\n+++ b/target/riscv/insn_trans/trans_rvi.c.inc\n@@ -392,7 +392,7 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)\n }\n } else {\n tcg_gen_qemu_ld_i128(t16, addrl, ctx->mem_idx, memop);\n- if (mo_endian(ctx) == MO_LE) {\n+ if (ctx->mo_endianness == MO_LE) {\n tcg_gen_extr_i128_i64(tl, th, t16);\n } else {\n tcg_gen_extr_i128_i64(th, tl, t16);\n@@ -409,7 +409,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)\n {\n bool out;\n \n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n if (ctx->cfg_ptr->ext_zama16b) {\n memop |= MO_ATOM_WITHIN16;\n }\n@@ -508,7 +508,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)\n tcg_gen_ext_tl_i64(tl, src2l);\n tcg_gen_ext_tl_i64(th, src2h);\n \n- if (mo_endian(ctx) == MO_LE) {\n+ if (ctx->mo_endianness == MO_LE) {\n tcg_gen_concat_i64_i128(t16, tl, th);\n } else {\n tcg_gen_concat_i64_i128(t16, th, tl);\n@@ -520,7 +520,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)\n \n static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)\n {\n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n if (ctx->cfg_ptr->ext_zama16b) {\n memop |= MO_ATOM_WITHIN16;\n }\ndiff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc b/target/riscv/insn_trans/trans_rvzacas.c.inc\nindex 8d94b83ce9..79bca1e957 100644\n--- a/target/riscv/insn_trans/trans_rvzacas.c.inc\n+++ b/target/riscv/insn_trans/trans_rvzacas.c.inc\n@@ -76,7 +76,7 @@ static bool gen_cmpxchg64(DisasContext *ctx, arg_atomic *a, MemOp mop)\n TCGv src1 = get_address(ctx, a->rs1, 0);\n TCGv_i64 src2 = get_gpr_pair(ctx, a->rs2);\n \n- mop |= mo_endian(ctx);\n+ mop |= ctx->mo_endianness;\n decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);\n tcg_gen_atomic_cmpxchg_i64(dest, src1, dest, src2, ctx->mem_idx, mop);\n \n@@ -121,7 +121,7 @@ static bool trans_amocas_q(DisasContext *ctx, arg_amocas_q *a)\n TCGv_i64 desth = get_gpr(ctx, a->rd == 0 ? 0 : a->rd + 1, EXT_NONE);\n MemOp memop = MO_ALIGN | MO_UO;\n \n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n tcg_gen_concat_i64_i128(src2, src2l, src2h);\n tcg_gen_concat_i64_i128(dest, destl, desth);\n decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);\ndiff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/insn_trans/trans_rvzalasr.c.inc\nindex 0f307affec..79b0b2c63b 100644\n--- a/target/riscv/insn_trans/trans_rvzalasr.c.inc\n+++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc\n@@ -29,7 +29,7 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memop)\n return false;\n }\n \n- memop |= MO_ALIGN | mo_endian(ctx);\n+ memop |= MO_ALIGN | ctx->mo_endianness;\n memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;\n \n tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);\n@@ -79,7 +79,7 @@ static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)\n return false;\n }\n \n- memop |= MO_ALIGN | mo_endian(ctx);\n+ memop |= MO_ALIGN | ctx->mo_endianness;\n memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;\n \n /* Add a memory barrier implied by RL (mandatory) and AQ (optional) */\ndiff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc\nindex 0d3ba40e52..71b4ca5473 100644\n--- a/target/riscv/insn_trans/trans_rvzce.c.inc\n+++ b/target/riscv/insn_trans/trans_rvzce.c.inc\n@@ -185,7 +185,7 @@ static bool gen_pop(DisasContext *ctx, arg_cmpp *a, bool ret, bool ret_val)\n \n tcg_gen_addi_tl(addr, sp, stack_adj - reg_size);\n \n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n for (i = X_Sn + 11; i >= 0; i--) {\n if (reg_bitmap & (1 << i)) {\n TCGv dest = dest_gpr(ctx, i);\n@@ -239,7 +239,7 @@ static bool trans_cm_push(DisasContext *ctx, arg_cm_push *a)\n \n tcg_gen_subi_tl(addr, sp, reg_size);\n \n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n for (i = X_Sn + 11; i >= 0; i--) {\n if (reg_bitmap & (1 << i)) {\n TCGv val = get_gpr(ctx, i, EXT_NONE);\ndiff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc\nindex 791ee51f65..f36b46c211 100644\n--- a/target/riscv/insn_trans/trans_rvzfh.c.inc\n+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc\n@@ -49,7 +49,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)\n REQUIRE_FPU;\n REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);\n \n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n decode_save_opc(ctx, 0);\n t0 = get_gpr(ctx, a->rs1, EXT_NONE);\n if (a->imm) {\n@@ -74,7 +74,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a)\n REQUIRE_FPU;\n REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);\n \n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n decode_save_opc(ctx, 0);\n t0 = get_gpr(ctx, a->rs1, EXT_NONE);\n if (a->imm) {\ndiff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc b/target/riscv/insn_trans/trans_rvzicfiss.c.inc\nindex 0b6ad57965..43f586dce9 100644\n--- a/target/riscv/insn_trans/trans_rvzicfiss.c.inc\n+++ b/target/riscv/insn_trans/trans_rvzicfiss.c.inc\n@@ -105,7 +105,7 @@ static bool trans_ssamoswap_w(DisasContext *ctx, arg_amoswap_w *a)\n decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);\n src1 = get_address(ctx, a->rs1, 0);\n \n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), memop);\n gen_set_gpr(ctx, a->rd, dest);\n return true;\n@@ -135,7 +135,7 @@ static bool trans_ssamoswap_d(DisasContext *ctx, arg_amoswap_w *a)\n decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);\n src1 = get_address(ctx, a->rs1, 0);\n \n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), memop);\n gen_set_gpr(ctx, a->rd, dest);\n return true;\ndiff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_trans/trans_xmips.c.inc\nindex c1a30156d3..1b9993a9b0 100644\n--- a/target/riscv/insn_trans/trans_xmips.c.inc\n+++ b/target/riscv/insn_trans/trans_xmips.c.inc\n@@ -47,7 +47,7 @@ static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a)\n /* Load Doubleword Pair. */\n static bool trans_ldp(DisasContext *ctx, arg_ldp *a)\n {\n- MemOp memop = MO_SQ | mo_endian(ctx);\n+ MemOp memop = MO_SQ | ctx->mo_endianness;\n \n REQUIRE_XMIPSLSP(ctx);\n REQUIRE_64_OR_128BIT(ctx);\n@@ -71,7 +71,7 @@ static bool trans_ldp(DisasContext *ctx, arg_ldp *a)\n /* Load Word Pair. */\n static bool trans_lwp(DisasContext *ctx, arg_lwp *a)\n {\n- MemOp memop = MO_SL | mo_endian(ctx);\n+ MemOp memop = MO_SL | ctx->mo_endianness;\n \n REQUIRE_XMIPSLSP(ctx);\n \n@@ -94,7 +94,7 @@ static bool trans_lwp(DisasContext *ctx, arg_lwp *a)\n /* Store Doubleword Pair. */\n static bool trans_sdp(DisasContext *ctx, arg_sdp *a)\n {\n- MemOp memop = MO_UQ | mo_endian(ctx);\n+ MemOp memop = MO_UQ | ctx->mo_endianness;\n \n REQUIRE_XMIPSLSP(ctx);\n REQUIRE_64_OR_128BIT(ctx);\n@@ -116,7 +116,7 @@ static bool trans_sdp(DisasContext *ctx, arg_sdp *a)\n /* Store Word Pair. */\n static bool trans_swp(DisasContext *ctx, arg_swp *a)\n {\n- MemOp memop = MO_SL | mo_endian(ctx);\n+ MemOp memop = MO_SL | ctx->mo_endianness;\n \n REQUIRE_XMIPSLSP(ctx);\n \ndiff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc\nindex f8b95c6498..f4e3051000 100644\n--- a/target/riscv/insn_trans/trans_xthead.c.inc\n+++ b/target/riscv/insn_trans/trans_xthead.c.inc\n@@ -349,7 +349,7 @@ static bool gen_fload_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,\n TCGv_i64 rd = cpu_fpr[a->rd];\n TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);\n \n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n tcg_gen_qemu_ld_i64(rd, addr, ctx->mem_idx, memop);\n if ((memop & MO_SIZE) == MO_32) {\n gen_nanbox_s(rd, rd);\n@@ -370,7 +370,7 @@ static bool gen_fstore_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,\n TCGv_i64 rd = cpu_fpr[a->rd];\n TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);\n \n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n tcg_gen_qemu_st_i64(rd, addr, ctx->mem_idx, memop);\n \n return true;\n@@ -570,7 +570,7 @@ static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,\n TCGv rd = dest_gpr(ctx, a->rd);\n TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);\n \n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop);\n tcg_gen_addi_tl(rs1, rs1, imm);\n gen_set_gpr(ctx, a->rd, rd);\n@@ -591,7 +591,7 @@ static bool gen_store_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,\n TCGv data = get_gpr(ctx, a->rd, EXT_NONE);\n TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);\n \n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);\n tcg_gen_addi_tl(rs1, rs1, imm);\n gen_set_gpr(ctx, a->rs1, rs1);\n@@ -747,7 +747,7 @@ static bool gen_load_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,\n TCGv rd = dest_gpr(ctx, a->rd);\n TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);\n \n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop);\n gen_set_gpr(ctx, a->rd, rd);\n \n@@ -765,7 +765,7 @@ static bool gen_store_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,\n TCGv data = get_gpr(ctx, a->rd, EXT_NONE);\n TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);\n \n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);\n \n return true;\n@@ -926,7 +926,7 @@ static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,\n addr1 = get_address(ctx, a->rs, imm);\n addr2 = get_address(ctx, a->rs, memop_size(memop) + imm);\n \n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n tcg_gen_qemu_ld_tl(t1, addr1, ctx->mem_idx, memop);\n tcg_gen_qemu_ld_tl(t2, addr2, ctx->mem_idx, memop);\n gen_set_gpr(ctx, a->rd1, t1);\n@@ -965,7 +965,7 @@ static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,\n addr1 = get_address(ctx, a->rs, imm);\n addr2 = get_address(ctx, a->rs, memop_size(memop) + imm);\n \n- memop |= mo_endian(ctx);\n+ memop |= ctx->mo_endianness;\n tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop);\n tcg_gen_qemu_st_tl(data2, addr2, ctx->mem_idx, memop);\n return true;\ndiff --git a/target/riscv/insn_trans/trans_zilsd.c.inc b/target/riscv/insn_trans/trans_zilsd.c.inc\nindex f50c52f22c..8068cc1aec 100644\n--- a/target/riscv/insn_trans/trans_zilsd.c.inc\n+++ b/target/riscv/insn_trans/trans_zilsd.c.inc\n@@ -30,7 +30,7 @@ static bool gen_load_i64(DisasContext *ctx, arg_ld *a)\n TCGv addr = get_address(ctx, a->rs1, a->imm);\n TCGv_i64 tmp = tcg_temp_new_i64();\n \n- tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_SQ | mo_endian(ctx));\n+ tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_SQ | ctx->mo_endianness);\n \n if (a->rd == 0) {\n return true;\n@@ -85,7 +85,7 @@ static bool gen_store_i64(DisasContext *ctx, arg_sd *a)\n } else {\n tcg_gen_concat_tl_i64(tmp, data_low, data_high);\n }\n- tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_SQ | mo_endian(ctx));\n+ tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_SQ | ctx->mo_endianness);\n \n return true;\n }\ndiff --git a/target/riscv/internals.h b/target/riscv/internals.h\nindex 460346dd6d..e2f0334da8 100644\n--- a/target/riscv/internals.h\n+++ b/target/riscv/internals.h\n@@ -64,14 +64,7 @@ static inline bool mmuidx_2stage(int mmu_idx)\n \n static inline MemOp mo_endian_env(CPURISCVState *env)\n {\n- /*\n- * A couple of bits in MSTATUS set the endianness:\n- * - MSTATUS_UBE (User-mode),\n- * - MSTATUS_SBE (Supervisor-mode),\n- * - MSTATUS_MBE (Machine-mode)\n- * but we don't implement that yet.\n- */\n- return MO_LE;\n+ return riscv_cpu_data_is_big_endian(env) ? MO_BE : MO_LE;\n }\n \n /* share data between vector helpers and decode code */\ndiff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex 3407191c22..d73b749bae 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -189,10 +189,15 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)\n flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env));\n flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext);\n \n+ uint64_t cs_base = env->misa_ext;\n+ if (riscv_cpu_data_is_big_endian(env)) {\n+ cs_base |= TB_CSBASE_BIG_ENDIAN;\n+ }\n+\n return (TCGTBCPUState){\n .pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc,\n .flags = flags,\n- .cs_base = env->misa_ext,\n+ .cs_base = cs_base,\n };\n }\n \ndiff --git a/target/riscv/translate.c b/target/riscv/translate.c\nindex 5df5b73849..9f538ba96d 100644\n--- a/target/riscv/translate.c\n+++ b/target/riscv/translate.c\n@@ -119,6 +119,8 @@ typedef struct DisasContext {\n bool fcfi_lp_expected;\n /* zicfiss extension, if shadow stack was enabled during TB gen */\n bool bcfi_enabled;\n+ /* Data endianness from MSTATUS UBE/SBE/MBE */\n+ MemOp mo_endianness;\n } DisasContext;\n \n static inline bool has_ext(DisasContext *ctx, uint32_t ext)\n@@ -126,18 +128,6 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)\n return ctx->misa_ext & ext;\n }\n \n-static inline MemOp mo_endian(DisasContext *ctx)\n-{\n- /*\n- * A couple of bits in MSTATUS set the endianness:\n- * - MSTATUS_UBE (User-mode),\n- * - MSTATUS_SBE (Supervisor-mode),\n- * - MSTATUS_MBE (Machine-mode)\n- * but we don't implement that yet.\n- */\n- return MO_LE;\n-}\n-\n #ifdef TARGET_RISCV32\n #define get_xl(ctx) MXL_RV32\n #elif defined(CONFIG_USER_ONLY)\n@@ -154,7 +144,7 @@ static inline MemOp mo_endian(DisasContext *ctx)\n #define get_address_xl(ctx) ((ctx)->address_xl)\n #endif\n \n-#define mxl_memop(ctx) ((get_xl(ctx) + 1) | mo_endian(ctx))\n+#define mxl_memop(ctx) ((get_xl(ctx) + 1) | (ctx)->mo_endianness)\n \n /* The word size for this machine mode. */\n static inline int __attribute__((unused)) get_xlen(DisasContext *ctx)\n@@ -1147,7 +1137,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,\n TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);\n MemOp size = mop & MO_SIZE;\n \n- mop |= mo_endian(ctx);\n+ mop |= ctx->mo_endianness;\n if (ctx->cfg_ptr->ext_zama16b && size >= MO_32) {\n mop |= MO_ATOM_WITHIN16;\n } else {\n@@ -1168,7 +1158,7 @@ static bool gen_cmpxchg(DisasContext *ctx, arg_atomic *a, MemOp mop)\n TCGv src1 = get_address(ctx, a->rs1, 0);\n TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);\n \n- mop |= mo_endian(ctx);\n+ mop |= ctx->mo_endianness;\n decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);\n tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop);\n \n@@ -1346,6 +1336,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)\n ctx->zero = tcg_constant_tl(0);\n ctx->virt_inst_excp = false;\n ctx->decoders = cpu->decoders;\n+ ctx->mo_endianness = (ctx->base.tb->cs_base & TB_CSBASE_BIG_ENDIAN)\n+ ? MO_BE : MO_LE;\n }\n \n static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)\n", "prefixes": [ "v7", "3/6" ] }