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GET /api/patches/2224344/?format=api
{ "id": 2224344, "url": "http://patchwork.ozlabs.org/api/patches/2224344/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417100302.162260-3-djordje.todorovic@htecgroup.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417100302.162260-3-djordje.todorovic@htecgroup.com>", "list_archive_url": null, "date": "2026-04-17T10:03:10", "name": "[v7,2/6] target/riscv: Add big-endian CPU property", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fe1158473d6e9518e12e8434efd14098a81b72dd", "submitter": { "id": 90738, "url": "http://patchwork.ozlabs.org/api/people/90738/?format=api", "name": "Djordje Todorovic", "email": "Djordje.Todorovic@htecgroup.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417100302.162260-3-djordje.todorovic@htecgroup.com/mbox/", "series": [ { "id": 500299, "url": "http://patchwork.ozlabs.org/api/series/500299/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500299", "date": "2026-04-17T10:03:08", "name": "Add RISC-V big-endian target support", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/500299/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224344/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224344/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=htecgroup.com header.i=@htecgroup.com\n header.a=rsa-sha256 header.s=selector1 header.b=sImdi8yn;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=gyJTcEOGqZbsM/+0V779RHADg7sXv4dYp7g8aLTJ4/0=;\n b=eyTGbnIabCzJdBWJf4jUu0nCGbsHJAHk/YmCgDGURXRr/K4b4ygK319kpXg+WbsYNtZls+GyB/r3itgA+GJx9mxS3qh9zZncdpvToAZDisNzpsLmYd2/3R4LaLpLFg9heoc+NA+oXDGegZNoUc/Teya7VJQaXqBoEai5ioLYMZigfaZD4UE+IZFKBdlc/7lP9RR5BpyngxlHjtN46rDpE5kXmarOSwc7Gs8Q0vpKCMx9c7eO6pA0WSFaPZl5arPWppKmsOcOPb1OhpIc7J8locmrQV6fE2KG3S1lC1vuhgJxlchGVHOznKj6QVaIdXbQxbw+ZIaNM8jcfSMaEsBZ+w==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=htecgroup.com; dmarc=pass action=none\n header.from=htecgroup.com; dkim=pass header.d=htecgroup.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=htecgroup.com;\n s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=gyJTcEOGqZbsM/+0V779RHADg7sXv4dYp7g8aLTJ4/0=;\n b=sImdi8ynPcTMjRpLj8gMAMJxtXFLIyBMRoeLGXEiWhz8BU7LGtMLn2aN0LK+0uh58t0gAMJTA2GJTJ2Fli7YtB1n8nufXtyMTkpuzWmrLahhsB6vwMAdLnB1y8Y74Urt8M5pgg+pGG3rfHFeGdvN/DyGc0okCB1Jb2VpFU0RjNaAyyJv0meWcX5MK7aFapwphuYz7mIwDtcBY79fRUEgaZrKGtPueL1aQ1ZPaHv9JnLrjI/HnHA0wVQpEDB5AmfkPEnmdBlhc1+UWrxD280bkCboYNOWF8EdQZVdSh4eC3BLimG0idXJA2JTSuHKhu2AHIyO1o906lRKPQDJHxJUdg==", "From": "Djordje Todorovic <Djordje.Todorovic@htecgroup.com>", "To": "\"qemu-devel@nongnu.org\" <qemu-devel@nongnu.org>", "CC": "\"qemu-riscv@nongnu.org\" <qemu-riscv@nongnu.org>, \"cfu@mips.com\"\n <cfu@mips.com>, \"mst@redhat.com\" <mst@redhat.com>,\n \"marcel.apfelbaum@gmail.com\" <marcel.apfelbaum@gmail.com>,\n \"dbarboza@ventanamicro.com\" <dbarboza@ventanamicro.com>, \"philmd@linaro.org\"\n <philmd@linaro.org>, \"alistair23@gmail.com\" <alistair23@gmail.com>,\n \"thuth@redhat.com\" <thuth@redhat.com>, Djordje Todorovic\n <Djordje.Todorovic@htecgroup.com>, Chao Liu <chao.liu.zevorn@gmail.com>", "Subject": "[PATCH v7 2/6] target/riscv: Add big-endian CPU property", "Thread-Topic": "[PATCH v7 2/6] target/riscv: Add big-endian CPU property", "Thread-Index": "AQHczlFlSjRd9usdwkWfBofvuRil5A==", "Date": "Fri, 17 Apr 2026 10:03:10 +0000", "Message-ID": "<20260417100302.162260-3-djordje.todorovic@htecgroup.com>", "References": "<20260417100302.162260-1-djordje.todorovic@htecgroup.com>", "In-Reply-To": "<20260417100302.162260-1-djordje.todorovic@htecgroup.com>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "authentication-results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=htecgroup.com header.i=@htecgroup.com\n header.a=rsa-sha256 header.s=selector1 header.b=sImdi8yn;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-OriginatorOrg": "htecgroup.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "PA2PR09MB7634.eurprd09.prod.outlook.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0bbda141-0cd9-4f07-4da0-08de9c688803", "X-MS-Exchange-CrossTenant-originalarrivaltime": "17 Apr 2026 10:03:10.5052 (UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "9f85665b-7efd-4776-9dfe-b6bfda2565ee", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n /T/f0nD3KCCBK/XQNRLJ/SQJiO6AVhyaPPhc9CL5ULCCHJLRu8UypcF79Hs3QHxDj8Eb2t48Zy5vvSQijW0hCW16BIEB6icmCMjk1r98yuI=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM7PR09MB3736", "Received-SPF": "pass client-ip=2a01:111:f403:c200::1;\n envelope-from=Djordje.Todorovic@htecgroup.com;\n helo=DB3PR0202CU003.outbound.protection.outlook.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add a \"big-endian\" boolean property to the RISC-V CPU configuration,\ndefaulting to false (little-endian). When enabled, this models a\nbig-endian-only RISC-V implementation as described in section 3.1.6.5\nof the RISC-V Privileged Specification (\"Memory Endianness\"), where\nthe MSTATUS MBE/SBE/UBE bits are hardwired to 1.\n\nThis is a static, per-CPU hardware configuration option, not a runtime\nswitch. It is intended for modeling RISC-V CPU variants whose data\nendianness is fixed to big-endian at the hardware level. Instructions\nremain little-endian regardless, per the RISC-V ISA specification.\n\nWhen cfg.big_endian is set, riscv_cpu_reset_hold() writes 1 into the\nMSTATUS UBE/SBE/MBE fields; otherwise it writes 0. The assignment is\ndone with set_field() so the reset value is deterministic on both\ncold and warm reset, rather than depending on the pre-reset state.\nThe MBE/SBE/UBE bits are not included in the writable mask of any\nmstatus/mstatush/sstatus CSR write path, so the value chosen at reset\neffectively hardwires them. The actual effect of those bits on data\naccesses, page-table walks and boot code is implemented by the\nsubsequent patches in this series.\n\nAlso update the disassembler comment to clarify that BFD_ENDIAN_LITTLE\nis correct because RISC-V instructions are always little-endian per\nthe ISA specification.\n\nNo upstream CPU currently defaults to big-endian; the property can be\nenabled from the command line, e.g.:\n\n -cpu <cpu>,big-endian=on\n\nSigned-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>\nReviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>\n---\n docs/system/target-riscv.rst | 24 ++++++++++++++++++++++++\n target/riscv/cpu.c | 11 ++++++-----\n target/riscv/cpu_cfg_fields.h.inc | 1 +\n 3 files changed, 31 insertions(+), 5 deletions(-)", "diff": "diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst\nindex 3ad5d1ddaf..7798184ebe 100644\n--- a/docs/system/target-riscv.rst\n+++ b/docs/system/target-riscv.rst\n@@ -95,3 +95,27 @@ the images they need.\n * ``-bios <file>``\n \n Tells QEMU to load the specified file as the firmware.\n+\n+RISC-V CPU endianness\n+---------------------\n+\n+The RISC-V ISA specifies that instruction fetches are always little-endian,\n+while data accesses can be either little-endian or big-endian under control\n+of the MSTATUS ``MBE``/``SBE``/``UBE`` bits (see section 3.1.6.5, \"Memory\n+Endianness\", in the RISC-V Privileged Specification).\n+\n+QEMU implements the full data-endianness behaviour described by those bits.\n+In addition, the RISC-V CPU object exposes a ``big-endian`` boolean property\n+which models a big-endian-only hardware implementation, where the\n+``MBE``/``SBE``/``UBE`` bits are hardwired to 1. When the property is set,\n+the CPU is reset with all three bits initialised to 1, so the guest starts\n+executing in big-endian data mode from the reset vector. The property is a\n+static, per-CPU hardware configuration option and is not meant to be toggled\n+at runtime.\n+\n+The property can be enabled from the command line, for example::\n+\n+ -cpu <cpu>,big-endian=on\n+\n+No upstream CPU model currently defaults to big-endian; the property is\n+provided so that big-endian-only RISC-V CPU variants can be modelled.\ndiff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex e56470a374..c39500cb3f 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -716,6 +716,9 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)\n env->mstatus = set_field(env->mstatus, MSTATUS_MDT, 1);\n }\n }\n+ env->mstatus = set_field(env->mstatus, MSTATUS_MBE, cpu->cfg.big_endian);\n+ env->mstatus = set_field(env->mstatus, MSTATUS_SBE, cpu->cfg.big_endian);\n+ env->mstatus = set_field(env->mstatus, MSTATUS_UBE, cpu->cfg.big_endian);\n env->mcause = 0;\n env->miclaim = MIP_SGEIP;\n env->pc = env->resetvec;\n@@ -803,11 +806,8 @@ static void riscv_cpu_disas_set_info(const CPUState *s, disassemble_info *info)\n info->target_info = &cpu->cfg;\n \n /*\n- * A couple of bits in MSTATUS set the endianness:\n- * - MSTATUS_UBE (User-mode),\n- * - MSTATUS_SBE (Supervisor-mode),\n- * - MSTATUS_MBE (Machine-mode)\n- * but we don't implement that yet.\n+ * RISC-V instructions are always little-endian, regardless of the\n+ * data endianness configured via MSTATUS UBE/SBE/MBE bits.\n */\n info->endian = BFD_ENDIAN_LITTLE;\n \n@@ -2641,6 +2641,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {\n \n static const Property riscv_cpu_properties[] = {\n DEFINE_PROP_BOOL(\"debug\", RISCVCPU, cfg.debug, true),\n+ DEFINE_PROP_BOOL(\"big-endian\", RISCVCPU, cfg.big_endian, false),\n \n {.name = \"pmu-mask\", .info = &prop_pmu_mask},\n {.name = \"pmu-num\", .info = &prop_pmu_num}, /* Deprecated */\ndiff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc\nindex 70ec650abf..51436daabf 100644\n--- a/target/riscv/cpu_cfg_fields.h.inc\n+++ b/target/riscv/cpu_cfg_fields.h.inc\n@@ -154,6 +154,7 @@ BOOL_FIELD(ext_xmipscbop)\n BOOL_FIELD(ext_xmipscmov)\n BOOL_FIELD(ext_xmipslsp)\n \n+BOOL_FIELD(big_endian)\n BOOL_FIELD(mmu)\n BOOL_FIELD(pmp)\n BOOL_FIELD(debug)\n", "prefixes": [ "v7", "2/6" ] }