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GET /api/patches/2224176/?format=api
{ "id": 2224176, "url": "http://patchwork.ozlabs.org/api/patches/2224176/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260417024034.4046667-2-ycliang@andestech.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417024034.4046667-2-ycliang@andestech.com>", "list_archive_url": null, "date": "2026-04-17T02:40:32", "name": "[6/8] spi: atcspi200: Add data merge mode support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1f8a466974dba83f4281a9f91c06490a8e9c1549", "submitter": { "id": 79234, "url": "http://patchwork.ozlabs.org/api/people/79234/?format=api", "name": "Leo Yu-Chi Liang", "email": "ycliang@andestech.com" }, "delegate": { "id": 17739, "url": "http://patchwork.ozlabs.org/api/users/17739/?format=api", "username": "jagan", "first_name": "Jagannadha Sutradharudu", "last_name": "Teki", "email": "jagannadh.teki@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260417024034.4046667-2-ycliang@andestech.com/mbox/", "series": [ { "id": 500221, "url": "http://patchwork.ozlabs.org/api/series/500221/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=500221", "date": "2026-04-17T02:20:56", "name": "spi: atcspi200: Modernize driver and add spi-mem + data merge support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500221/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224176/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224176/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=fail (p=reject dis=none) header.from=andestech.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de; dmarc=fail (p=reject dis=none)\n header.from=andestech.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=ycliang@andestech.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxfJz6K1hz1yDF\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 Apr 2026 12:41:23 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 60497842BF;\n\tFri, 17 Apr 2026 04:41:09 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 8030384223; Fri, 17 Apr 2026 04:41:06 +0200 (CEST)", "from Atcsqr.andestech.com (exmail.andestech.com [60.248.187.195])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id F013F84228\n for <u-boot@lists.denx.de>; Fri, 17 Apr 2026 04:40:58 +0200 (CEST)", "from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134])\n by Atcsqr.andestech.com with ESMTP id 63H2edcp033481;\n Fri, 17 Apr 2026 10:40:39 +0800 (+08)\n (envelope-from ycliang@andestech.com)", "from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com\n (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 17 Apr\n 2026 10:40:39 +0800" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-1.9 required=5.0 tests=BAYES_00,\n RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,\n RCVD_IN_VALIDITY_RPBL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham\n autolearn_force=no version=3.4.2", "From": "Leo Yu-Chi Liang <ycliang@andestech.com>", "To": "<u-boot@lists.denx.de>", "CC": "Tom Rini <trini@konsulko.com>, Vignesh R <vigneshr@ti.com>, \"Takahiro\n Kuwano\" <takahiro.kuwano@infineon.com>, Jagan Teki\n <jagan@amarulasolutions.com>, <ycliang@andestech.com>", "Subject": "[PATCH 6/8] spi: atcspi200: Add data merge mode support", "Date": "Fri, 17 Apr 2026 10:40:32 +0800", "Message-ID": "<20260417024034.4046667-2-ycliang@andestech.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260417024034.4046667-1-ycliang@andestech.com>", "References": "<20260417024034.4046667-1-ycliang@andestech.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.0.15.183]", "X-ClientProxiedBy": "ATCPCS33.andestech.com (10.0.1.100) To\n ATCPCS34.andestech.com (10.0.1.134)", "X-DKIM-Results": "atcpcs34.andestech.com; dkim=none;", "X-DNSRBL": "", "X-MAIL": "Atcsqr.andestech.com 63H2edcp033481", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add CONFIG_ATCSPI200_SPI_DATA_MERGE option to enable 4-byte data\nmerge mode for the ATCSPI200 SPI controller. When enabled, each\nwrite to the data register transmits four bytes, and each read\nretrieves four bytes as a single word, improving throughput for\naligned transfers.\n\n- Add DATA_MERGE bit (bit 7) in format register\n- Add data_merge field to private data structure\n- Update TX/RX helpers to handle u32 access when data_merge is active\n- Dynamically enable/disable data merge based on transfer alignment\n (nbytes % 4 == 0) in both spi-mem exec_op and legacy xfer paths\n- Use IS_ENABLED() consistently for the Kconfig check\n- Add Kconfig entry with proper depends on ATCSPI200_SPI\n\nSigned-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>\n---\n drivers/spi/Kconfig | 9 ++++++\n drivers/spi/atcspi200_spi.c | 62 ++++++++++++++++++++++++++++++-------\n 2 files changed, 59 insertions(+), 12 deletions(-)", "diff": "diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig\nindex 4ff17617d99..f238b2c2534 100644\n--- a/drivers/spi/Kconfig\n+++ b/drivers/spi/Kconfig\n@@ -92,6 +92,15 @@ config ATCSPI200_SPI\n \t used to access the SPI flash on AE3XX and AE250 platforms embedding\n \t this Andestech IP core.\n \n+config ATCSPI200_SPI_DATA_MERGE\n+\tbool \"Enable ATCSPI200 data merge mode\"\n+\tdepends on ATCSPI200_SPI\n+\thelp\n+\t Enable data merge mode for the ATCSPI200 SPI controller.\n+\t When enabled, each write to the data register transmits four\n+\t bytes, and each read retrieves four bytes as a single word.\n+\t This improves throughput for aligned transfers.\n+\n config ATH79_SPI\n \tbool \"Atheros SPI driver\"\n \tdepends on ARCH_ATH79\ndiff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c\nindex cef0bb8188d..b743f80fb8d 100644\n--- a/drivers/spi/atcspi200_spi.c\n+++ b/drivers/spi/atcspi200_spi.c\n@@ -36,6 +36,7 @@\n /* FORMAT register fields */\n #define ADDR_LEN_MASK\t\tGENMASK(17, 16)\n #define DATA_LEN_MASK\t\tGENMASK(12, 8)\n+#define DATA_MERGE\t\tBIT(7)\n \n /* TCTRL register fields */\n #define TCTRL_CMD_EN\t\tBIT(30)\n@@ -89,6 +90,7 @@ struct atcspi200_priv {\n \tsize_t\t\ttran_len;\n \tvoid\t\t*din;\n \tconst void\t*dout;\n+\tbool\t\tdata_merge;\n \tunsigned int\tmax_transfer_length;\n };\n \n@@ -149,6 +151,10 @@ static int atcspi200_hw_claim_bus(struct atcspi200_priv *priv)\n \tpriv->cmd_len = 0;\n \tformat = priv->mode | FIELD_PREP(DATA_LEN_MASK, 8 - 1) |\n \t\t FIELD_PREP(ADDR_LEN_MASK, 3 - 1);\n+\tif (IS_ENABLED(CONFIG_ATCSPI200_SPI_DATA_MERGE)) {\n+\t\tformat |= DATA_MERGE;\n+\t\tpriv->data_merge = true;\n+\t}\n \tatcspi200_write(priv, ATCSPI200_REG_FORMAT, format);\n \tatcspi200_hw_set_speed(priv);\n \n@@ -182,20 +188,27 @@ static int atcspi200_hw_stop(struct atcspi200_priv *priv)\n \t\t\t\t SPIBSY, false, SPI_TIMEOUT_MS, false);\n }\n \n-static void atcspi200_tx_byte(struct atcspi200_priv *priv, const void *dout)\n+static void atcspi200_tx(struct atcspi200_priv *priv, const void *dout)\n {\n-\tatcspi200_write(priv, ATCSPI200_REG_DATA, *(u8 *)dout);\n+\tif (priv->data_merge)\n+\t\tatcspi200_write(priv, ATCSPI200_REG_DATA, *(u32 *)dout);\n+\telse\n+\t\tatcspi200_write(priv, ATCSPI200_REG_DATA, *(u8 *)dout);\n }\n \n-static void atcspi200_rx_byte(struct atcspi200_priv *priv, void *din)\n+static void atcspi200_rx(struct atcspi200_priv *priv, void *din)\n {\n-\t*(u8 *)din = (u8)atcspi200_read(priv, ATCSPI200_REG_DATA);\n+\tif (priv->data_merge)\n+\t\t*(u32 *)din = atcspi200_read(priv, ATCSPI200_REG_DATA);\n+\telse\n+\t\t*(u8 *)din = (u8)atcspi200_read(priv, ATCSPI200_REG_DATA);\n }\n \n static void atcspi200_pio_transfer(struct atcspi200_priv *priv,\n \t\t\t\t void *din, const void *dout,\n \t\t\t\t unsigned int len)\n {\n+\tunsigned int step = priv->data_merge ? 4 : 1;\n \tunsigned int tx_remain = dout ? len : 0;\n \tunsigned int rx_remain = din ? len : 0;\n \tunsigned long start = get_timer(0);\n@@ -205,15 +218,15 @@ static void atcspi200_pio_transfer(struct atcspi200_priv *priv,\n \t\tu32 status = atcspi200_read(priv, ATCSPI200_REG_STATUS);\n \n \t\tif (tx_remain && !(status & TXFFL)) {\n-\t\t\tatcspi200_tx_byte(priv, dout);\n-\t\t\tdout = (const u8 *)dout + 1;\n-\t\t\ttx_remain--;\n+\t\t\tatcspi200_tx(priv, dout);\n+\t\t\tdout = (const u8 *)dout + step;\n+\t\t\ttx_remain -= step;\n \t\t}\n \n \t\tif (rx_remain && (status & RXFVE_MASK)) {\n-\t\t\tatcspi200_rx_byte(priv, din);\n-\t\t\tdin = (u8 *)din + 1;\n-\t\t\trx_remain--;\n+\t\t\tatcspi200_rx(priv, din);\n+\t\t\tdin = (u8 *)din + step;\n+\t\t\trx_remain -= step;\n \t\t}\n \t}\n \n@@ -232,6 +245,19 @@ static int atcspi200_hw_xfer(struct atcspi200_priv *priv,\n \tunsigned long data_len = bitlen / 8;\n \tint ret = 0;\n \n+\tif (IS_ENABLED(CONFIG_ATCSPI200_SPI_DATA_MERGE)) {\n+\t\tu32 format = atcspi200_read(priv, ATCSPI200_REG_FORMAT);\n+\n+\t\tif (data_len % 4 == 0) {\n+\t\t\tformat |= DATA_MERGE;\n+\t\t\tpriv->data_merge = true;\n+\t\t} else {\n+\t\t\tformat &= ~DATA_MERGE;\n+\t\t\tpriv->data_merge = false;\n+\t\t}\n+\t\tatcspi200_write(priv, ATCSPI200_REG_FORMAT, format);\n+\t}\n+\n \tmax_tran_len = priv->max_transfer_length;\n \tswitch (flags) {\n \tcase SPI_XFER_BEGIN:\n@@ -335,13 +361,25 @@ static int atcspi200_spi_mem_exec_op(struct spi_slave *slave,\n \tu32 format;\n \tint ret;\n \n+\tformat = atcspi200_read(priv, ATCSPI200_REG_FORMAT);\n+\n+\t/* Dynamically enable/disable data merge based on alignment */\n+\tif (IS_ENABLED(CONFIG_ATCSPI200_SPI_DATA_MERGE)) {\n+\t\tif (op->data.nbytes && (op->data.nbytes % 4 == 0)) {\n+\t\t\tformat |= DATA_MERGE;\n+\t\t\tpriv->data_merge = true;\n+\t\t} else {\n+\t\t\tformat &= ~DATA_MERGE;\n+\t\t\tpriv->data_merge = false;\n+\t\t}\n+\t}\n+\n \t/* Update address length in format register if needed */\n \tif (op->addr.nbytes) {\n-\t\tformat = atcspi200_read(priv, ATCSPI200_REG_FORMAT);\n \t\tformat &= ~ADDR_LEN_MASK;\n \t\tformat |= FIELD_PREP(ADDR_LEN_MASK, op->addr.nbytes - 1);\n-\t\tatcspi200_write(priv, ATCSPI200_REG_FORMAT, format);\n \t}\n+\tatcspi200_write(priv, ATCSPI200_REG_FORMAT, format);\n \n \t/* Set up transfer control for this operation */\n \tatcspi200_set_transfer_ctl(priv, op);\n", "prefixes": [ "6/8" ] }