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GET /api/patches/2224175/?format=api
{ "id": 2224175, "url": "http://patchwork.ozlabs.org/api/patches/2224175/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260417024034.4046667-3-ycliang@andestech.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417024034.4046667-3-ycliang@andestech.com>", "list_archive_url": null, "date": "2026-04-17T02:40:33", "name": "[7/8] mtd: spi-nor: Add Macronix MX25U quad-mode fixups", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c9679f0075039f452a60590ed0c578f3e01d7a47", "submitter": { "id": 79234, "url": "http://patchwork.ozlabs.org/api/people/79234/?format=api", "name": "Leo Yu-Chi Liang", "email": "ycliang@andestech.com" }, "delegate": { "id": 17739, "url": "http://patchwork.ozlabs.org/api/users/17739/?format=api", "username": "jagan", "first_name": "Jagannadha Sutradharudu", "last_name": "Teki", "email": "jagannadh.teki@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260417024034.4046667-3-ycliang@andestech.com/mbox/", "series": [ { "id": 500221, "url": "http://patchwork.ozlabs.org/api/series/500221/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=500221", "date": "2026-04-17T02:20:56", "name": "spi: atcspi200: Modernize driver and add spi-mem + data merge support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500221/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224175/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224175/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=fail (p=reject dis=none) header.from=andestech.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de; dmarc=fail (p=reject dis=none)\n header.from=andestech.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=ycliang@andestech.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxfJq4PDLz1yDF\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 Apr 2026 12:41:15 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id F2DFD84228;\n\tFri, 17 Apr 2026 04:41:07 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 44AF2842BF; Fri, 17 Apr 2026 04:41:06 +0200 (CEST)", "from Atcsqr.andestech.com (exmail.andestech.com [60.248.187.195])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id CF98C8422D\n for <u-boot@lists.denx.de>; Fri, 17 Apr 2026 04:41:03 +0200 (CEST)", "from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134])\n by Atcsqr.andestech.com with ESMTP id 63H2edcq033481;\n Fri, 17 Apr 2026 10:40:40 +0800 (+08)\n (envelope-from ycliang@andestech.com)", "from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com\n (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 17 Apr\n 2026 10:40:39 +0800" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-1.9 required=5.0 tests=BAYES_00,\n RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,\n RCVD_IN_VALIDITY_RPBL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham\n autolearn_force=no version=3.4.2", "From": "Leo Yu-Chi Liang <ycliang@andestech.com>", "To": "<u-boot@lists.denx.de>", "CC": "Tom Rini <trini@konsulko.com>, Vignesh R <vigneshr@ti.com>, \"Takahiro\n Kuwano\" <takahiro.kuwano@infineon.com>, Jagan Teki\n <jagan@amarulasolutions.com>, <ycliang@andestech.com>", "Subject": "[PATCH 7/8] mtd: spi-nor: Add Macronix MX25U quad-mode fixups", "Date": "Fri, 17 Apr 2026 10:40:33 +0800", "Message-ID": "<20260417024034.4046667-3-ycliang@andestech.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260417024034.4046667-1-ycliang@andestech.com>", "References": "<20260417024034.4046667-1-ycliang@andestech.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.0.15.183]", "X-ClientProxiedBy": "ATCPCS33.andestech.com (10.0.1.100) To\n ATCPCS34.andestech.com (10.0.1.134)", "X-DKIM-Results": "atcpcs34.andestech.com; dkim=none;", "X-DNSRBL": "", "X-MAIL": "Atcsqr.andestech.com 63H2edcq033481", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add quad mode (1-4-4) read and page program fixups for Macronix\nMX25U1635E and MX25U25635F SPI NOR flash chips. These chips do not\nproperly expose their quad capabilities via SFDP, requiring explicit\nfixup hooks.\n\nThe fixup enables SNOR_HWCAPS_READ_1_4_4 and SNOR_HWCAPS_PP_1_4_4\ncapabilities with the appropriate opcodes and protocols.\n\nBoth chips share the same fixup function since their quad mode\nconfiguration is identical.\n\nSigned-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>\n---\n drivers/mtd/spi/spi-nor-core.c | 25 ++++++++++++++++++++++---\n 1 file changed, 22 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c\nindex 937d79af64e..d8a073fef3f 100644\n--- a/drivers/mtd/spi/spi-nor-core.c\n+++ b/drivers/mtd/spi/spi-nor-core.c\n@@ -4248,6 +4248,21 @@ static struct spi_nor_fixups macronix_octal_fixups = {\n \t.post_sfdp = macronix_octal_post_sfdp_fixup,\n \t.late_init = macronix_octal_late_init,\n };\n+\n+static void macronix_quad_post_sfdp_fixup(struct spi_nor *nor,\n+\t\t\t\t\t struct spi_nor_flash_parameter *params)\n+{\n+\tparams->hwcaps.mask |= SNOR_HWCAPS_READ_1_4_4 | SNOR_HWCAPS_PP_1_4_4;\n+\tspi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_4_4],\n+\t\t\t\t 0, 8, SPINOR_OP_READ_1_4_4,\n+\t\t\t\t SNOR_PROTO_1_4_4);\n+\tspi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_4_4],\n+\t\t\t\tSPINOR_OP_PP_1_4_4, SNOR_PROTO_1_4_4);\n+}\n+\n+static struct spi_nor_fixups macronix_quad_fixups = {\n+\t.post_sfdp = macronix_quad_post_sfdp_fixup,\n+};\n #endif /* CONFIG_SPI_FLASH_MACRONIX */\n \n #if CONFIG_IS_ENABLED(SPI_FLASH_WINBOND)\n@@ -4544,9 +4559,13 @@ void spi_nor_set_fixups(struct spi_nor *nor)\n #endif\n \n #if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)\n-\tif (JEDEC_MFR(nor->info) == SNOR_MFR_MACRONIX &&\n-\t nor->info->flags & SPI_NOR_OCTAL_DTR_READ)\n-\t\tnor->fixups = ¯onix_octal_fixups;\n+\tif (JEDEC_MFR(nor->info) == SNOR_MFR_MACRONIX) {\n+\t\tif (nor->info->flags & SPI_NOR_OCTAL_DTR_READ)\n+\t\t\tnor->fixups = ¯onix_octal_fixups;\n+\t\telse if (!strcmp(nor->info->name, \"mx25u1635e\") ||\n+\t\t\t !strcmp(nor->info->name, \"mx25u25635f\"))\n+\t\t\tnor->fixups = ¯onix_quad_fixups;\n+\t}\n #endif /* SPI_FLASH_MACRONIX */\n \n #if CONFIG_IS_ENABLED(SPI_FLASH_WINBOND)\n", "prefixes": [ "7/8" ] }