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GET /api/patches/2224174/?format=api
{ "id": 2224174, "url": "http://patchwork.ozlabs.org/api/patches/2224174/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260417024034.4046667-1-ycliang@andestech.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417024034.4046667-1-ycliang@andestech.com>", "list_archive_url": null, "date": "2026-04-17T02:40:31", "name": "[5/8] spi: atcspi200: Add spi-mem framework support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "cd77686656a3fa4aa9014e00bff918c761569014", "submitter": { "id": 79234, "url": "http://patchwork.ozlabs.org/api/people/79234/?format=api", "name": "Leo Yu-Chi Liang", "email": "ycliang@andestech.com" }, "delegate": { "id": 17739, "url": "http://patchwork.ozlabs.org/api/users/17739/?format=api", "username": "jagan", "first_name": "Jagannadha Sutradharudu", "last_name": "Teki", "email": "jagannadh.teki@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260417024034.4046667-1-ycliang@andestech.com/mbox/", "series": [ { "id": 500221, "url": "http://patchwork.ozlabs.org/api/series/500221/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=500221", "date": "2026-04-17T02:20:56", "name": "spi: atcspi200: Modernize driver and add spi-mem + data merge support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500221/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224174/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224174/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=fail (p=reject dis=none) header.from=andestech.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de; dmarc=fail (p=reject dis=none)\n header.from=andestech.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=ycliang@andestech.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxfJg3tX0z1yDF\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 Apr 2026 12:41:07 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id AC46B84258;\n\tFri, 17 Apr 2026 04:41:04 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id E6B2E84223; Fri, 17 Apr 2026 04:41:03 +0200 (CEST)", "from Atcsqr.andestech.com (unknown [60.248.187.195])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 0F8D684223\n for <u-boot@lists.denx.de>; Fri, 17 Apr 2026 04:40:55 +0200 (CEST)", "from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134])\n by Atcsqr.andestech.com with ESMTP id 63H2edpU033480;\n Fri, 17 Apr 2026 10:40:39 +0800 (+08)\n (envelope-from ycliang@andestech.com)", "from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com\n (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 17 Apr\n 2026 10:40:38 +0800" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-1.1 required=5.0 tests=BAYES_00,\n RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,\n RCVD_IN_VALIDITY_RPBL_BLOCKED,RDNS_NONE,SPF_HELO_NONE,SPF_PASS\n autolearn=no autolearn_force=no version=3.4.2", "From": "Leo Yu-Chi Liang <ycliang@andestech.com>", "To": "<u-boot@lists.denx.de>", "CC": "Tom Rini <trini@konsulko.com>, Vignesh R <vigneshr@ti.com>, \"Takahiro\n Kuwano\" <takahiro.kuwano@infineon.com>, Jagan Teki\n <jagan@amarulasolutions.com>, <ycliang@andestech.com>", "Subject": "[PATCH 5/8] spi: atcspi200: Add spi-mem framework support", "Date": "Fri, 17 Apr 2026 10:40:31 +0800", "Message-ID": "<20260417024034.4046667-1-ycliang@andestech.com>", "X-Mailer": "git-send-email 2.34.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.0.15.183]", "X-ClientProxiedBy": "ATCPCS33.andestech.com (10.0.1.100) To\n ATCPCS34.andestech.com (10.0.1.134)", "X-DKIM-Results": "atcpcs34.andestech.com; dkim=none;", "X-DNSRBL": "", "X-MAIL": "Atcsqr.andestech.com 63H2edpU033480", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add spi_controller_mem_ops implementation to support SPI memory\noperations with single, dual, and quad modes:\n\n- Add atcspi200_spi_mem_exec_op() for executing SPI memory operations\n with proper command, address, dummy, and data phase handling\n- Add atcspi200_set_transfer_ctl() to configure the transfer control\n register for different bus widths and transfer modes\n- Add atcspi200_pio_transfer() as a shared PIO data pump used by both\n the spi-mem exec_op and legacy xfer paths\n- Add atcspi200_spi_adjust_op_size() to cap transfers to hardware max\n- Add new TCTRL field definitions for cmd/addr enable, address format,\n dual/quad mode, dummy count, and token enable\n- Add ADDR_LEN_MASK for configurable address length in format register\n- Wire spi_controller_mem_ops into dm_spi_ops.mem_ops\n- Simplify hw_start() for the legacy xfer path since cmd/addr handling\n is now done by the spi-mem framework for flash operations\n\nSigned-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>\n---\n drivers/spi/atcspi200_spi.c | 208 ++++++++++++++++++++++++++----------\n 1 file changed, 151 insertions(+), 57 deletions(-)", "diff": "diff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c\nindex 0e7f7b83081..cef0bb8188d 100644\n--- a/drivers/spi/atcspi200_spi.c\n+++ b/drivers/spi/atcspi200_spi.c\n@@ -11,6 +11,7 @@\n #include <dm/device_compat.h>\n #include <log.h>\n #include <spi.h>\n+#include <spi-mem.h>\n #include <time.h>\n #include <wait_bit.h>\n #include <asm/io.h>\n@@ -33,9 +34,13 @@\n #define ATCSPI200_REG_TIMING\t0x40\n \n /* FORMAT register fields */\n+#define ADDR_LEN_MASK\t\tGENMASK(17, 16)\n #define DATA_LEN_MASK\t\tGENMASK(12, 8)\n \n /* TCTRL register fields */\n+#define TCTRL_CMD_EN\t\tBIT(30)\n+#define TCTRL_ADDR_EN\t\tBIT(29)\n+#define TCTRL_ADDR_FMT\t\tBIT(28)\n #define TRAMODE_MASK\t\tGENMASK(27, 24)\n #define TRAMODE_WR_SYNC\t\tFIELD_PREP(TRAMODE_MASK, 0)\n #define TRAMODE_WO\t\tFIELD_PREP(TRAMODE_MASK, 1)\n@@ -47,7 +52,11 @@\n #define TRAMODE_NONE\t\tFIELD_PREP(TRAMODE_MASK, 7)\n #define TRAMODE_DW\t\tFIELD_PREP(TRAMODE_MASK, 8)\n #define TRAMODE_DR\t\tFIELD_PREP(TRAMODE_MASK, 9)\n+#define TCTRL_DUAL_QUAD_MASK\tGENMASK(23, 22)\n+#define TCTRL_TOKEN_EN\t\tBIT(21)\n #define WCNT_MASK\t\tGENMASK(20, 12)\n+#define TCTRL_TOKEN_VAL\t\tBIT(11)\n+#define TCTRL_DUMMY_CNT_MASK\tGENMASK(10, 9)\n #define RCNT_MASK\t\tGENMASK(8, 0)\n \n /* CTRL register fields */\n@@ -78,8 +87,8 @@ struct atcspi200_priv {\n \tu8\t\tcmd_buf[16];\n \tsize_t\t\tdata_len;\n \tsize_t\t\ttran_len;\n-\tu8\t\t*din;\n-\tu8\t\t*dout;\n+\tvoid\t\t*din;\n+\tconst void\t*dout;\n \tunsigned int\tmax_transfer_length;\n };\n \n@@ -138,7 +147,8 @@ static int atcspi200_hw_claim_bus(struct atcspi200_priv *priv)\n \t\treturn ret;\n \n \tpriv->cmd_len = 0;\n-\tformat = priv->mode | FIELD_PREP(DATA_LEN_MASK, 8 - 1);\n+\tformat = priv->mode | FIELD_PREP(DATA_LEN_MASK, 8 - 1) |\n+\t\t FIELD_PREP(ADDR_LEN_MASK, 3 - 1);\n \tatcspi200_write(priv, ATCSPI200_REG_FORMAT, format);\n \tatcspi200_hw_set_speed(priv);\n \n@@ -147,22 +157,15 @@ static int atcspi200_hw_claim_bus(struct atcspi200_priv *priv)\n \n static int atcspi200_hw_start(struct atcspi200_priv *priv)\n {\n-\tint i, olen = 0;\n-\tu32 tc;\n+\tu32 tc = 0;\n \n-\ttc = atcspi200_read(priv, ATCSPI200_REG_TCTRL);\n-\ttc &= ~(WCNT_MASK | RCNT_MASK | TRAMODE_MASK);\n-\n-\tif (priv->din && priv->cmd_len)\n-\t\ttc |= TRAMODE_WR;\n-\telse if (priv->din)\n+\tif (priv->din && !priv->dout)\n \t\ttc |= TRAMODE_RO;\n-\telse\n+\telse if (priv->dout && !priv->din)\n \t\ttc |= TRAMODE_WO;\n \n \tif (priv->dout)\n-\t\tolen = priv->tran_len;\n-\ttc |= FIELD_PREP(WCNT_MASK, priv->cmd_len + olen - 1);\n+\t\ttc |= FIELD_PREP(WCNT_MASK, priv->tran_len - 1);\n \n \tif (priv->din)\n \t\ttc |= FIELD_PREP(RCNT_MASK, priv->tran_len - 1);\n@@ -170,9 +173,6 @@ static int atcspi200_hw_start(struct atcspi200_priv *priv)\n \tatcspi200_write(priv, ATCSPI200_REG_TCTRL, tc);\n \tatcspi200_write(priv, ATCSPI200_REG_CMD, 1);\n \n-\tfor (i = 0; i < priv->cmd_len; i++)\n-\t\tatcspi200_write(priv, ATCSPI200_REG_DATA, priv->cmd_buf[i]);\n-\n \treturn 0;\n }\n \n@@ -192,19 +192,45 @@ static void atcspi200_rx_byte(struct atcspi200_priv *priv, void *din)\n \t*(u8 *)din = (u8)atcspi200_read(priv, ATCSPI200_REG_DATA);\n }\n \n+static void atcspi200_pio_transfer(struct atcspi200_priv *priv,\n+\t\t\t\t void *din, const void *dout,\n+\t\t\t\t unsigned int len)\n+{\n+\tunsigned int tx_remain = dout ? len : 0;\n+\tunsigned int rx_remain = din ? len : 0;\n+\tunsigned long start = get_timer(0);\n+\n+\twhile ((tx_remain || rx_remain) &&\n+\t get_timer(start) <= SPI_TIMEOUT_MS) {\n+\t\tu32 status = atcspi200_read(priv, ATCSPI200_REG_STATUS);\n+\n+\t\tif (tx_remain && !(status & TXFFL)) {\n+\t\t\tatcspi200_tx_byte(priv, dout);\n+\t\t\tdout = (const u8 *)dout + 1;\n+\t\t\ttx_remain--;\n+\t\t}\n+\n+\t\tif (rx_remain && (status & RXFVE_MASK)) {\n+\t\t\tatcspi200_rx_byte(priv, din);\n+\t\t\tdin = (u8 *)din + 1;\n+\t\t\trx_remain--;\n+\t\t}\n+\t}\n+\n+\tif (tx_remain || rx_remain)\n+\t\tdebug(\"%s: timeout, tx_remain=%u rx_remain=%u\\n\",\n+\t\t __func__, tx_remain, rx_remain);\n+}\n+\n static int atcspi200_hw_xfer(struct atcspi200_priv *priv,\n \t\t\t unsigned int bitlen, const void *data_out,\n \t\t\t void *data_in, unsigned long flags)\n {\n-\tunsigned int event;\n-\tconst void *dout = NULL;\n-\tvoid *din = NULL;\n-\tint num_blks, num_chunks, max_tran_len, tran_len;\n+\tunsigned int num_chunks, max_tran_len, tran_len;\n \tu8 *cmd_buf = priv->cmd_buf;\n \tsize_t cmd_len = priv->cmd_len;\n \tunsigned long data_len = bitlen / 8;\n \tint ret = 0;\n-\tunsigned long start;\n \n \tmax_tran_len = priv->max_transfer_length;\n \tswitch (flags) {\n@@ -218,19 +244,14 @@ static int atcspi200_hw_xfer(struct atcspi200_priv *priv,\n \t\tif (bitlen == 0)\n \t\t\treturn 0;\n \t\tpriv->data_len = data_len;\n-\t\tpriv->din = (u8 *)data_in;\n-\t\tpriv->dout = (u8 *)data_out;\n+\t\tpriv->din = data_in;\n+\t\tpriv->dout = data_out;\n \t\tbreak;\n \n \tcase SPI_XFER_BEGIN | SPI_XFER_END:\n-\t\tpriv->data_len = 0;\n-\t\tpriv->din = 0;\n-\t\tpriv->dout = 0;\n-\t\tcmd_len = priv->cmd_len = data_len;\n-\t\tmemcpy(cmd_buf, data_out, cmd_len);\n-\t\tdata_out = 0;\n-\t\tdata_len = 0;\n-\t\tatcspi200_hw_start(priv);\n+\t\tpriv->data_len = data_len;\n+\t\tpriv->din = data_in;\n+\t\tpriv->dout = data_out;\n \t\tbreak;\n \t}\n \n@@ -240,35 +261,11 @@ static int atcspi200_hw_xfer(struct atcspi200_priv *priv,\n \t\t data_in, data_len);\n \n \tnum_chunks = DIV_ROUND_UP(data_len, max_tran_len);\n-\tdin = data_in;\n-\tdout = data_out;\n \twhile (num_chunks--) {\n \t\ttran_len = min((size_t)data_len, (size_t)max_tran_len);\n \t\tpriv->tran_len = tran_len;\n-\t\tnum_blks = tran_len;\n-\t\tstart = get_timer(0);\n \t\tatcspi200_hw_start(priv);\n-\n-\t\twhile (num_blks) {\n-\t\t\tif (get_timer(start) > SPI_TIMEOUT_MS) {\n-\t\t\t\tdebug(\"spi_xfer: %s() timeout\\n\", __func__);\n-\t\t\t\tbreak;\n-\t\t\t}\n-\n-\t\t\tevent = atcspi200_read(priv, ATCSPI200_REG_STATUS);\n-\n-\t\t\tif ((event & TXEPTY) && data_out) {\n-\t\t\t\tatcspi200_tx_byte(priv, dout);\n-\t\t\t\tnum_blks--;\n-\t\t\t\tdout++;\n-\t\t\t}\n-\n-\t\t\tif ((event & RXFVE_MASK) && data_in) {\n-\t\t\t\tatcspi200_rx_byte(priv, din);\n-\t\t\t\tnum_blks--;\n-\t\t\t\tdin = (unsigned char *)din + 1;\n-\t\t\t}\n-\t\t}\n+\t\tatcspi200_pio_transfer(priv, priv->din, priv->dout, tran_len);\n \n \t\tdata_len -= tran_len;\n \t\tif (data_len) {\n@@ -288,6 +285,97 @@ static int atcspi200_hw_xfer(struct atcspi200_priv *priv,\n \treturn ret;\n }\n \n+static void atcspi200_set_transfer_ctl(struct atcspi200_priv *priv,\n+\t\t\t\t const struct spi_mem_op *op)\n+{\n+\tu32 tc = 0;\n+\n+\tif (op->cmd.nbytes)\n+\t\ttc |= TCTRL_CMD_EN;\n+\n+\tif (op->addr.nbytes) {\n+\t\ttc |= TCTRL_ADDR_EN;\n+\t\tif (op->addr.buswidth > 1)\n+\t\t\ttc |= TCTRL_ADDR_FMT;\n+\t}\n+\n+\tif (op->data.nbytes) {\n+\t\tif (op->data.buswidth == 2)\n+\t\t\ttc |= FIELD_PREP(TCTRL_DUAL_QUAD_MASK, 1);\n+\t\telse if (op->data.buswidth == 4)\n+\t\t\ttc |= FIELD_PREP(TCTRL_DUAL_QUAD_MASK, 2);\n+\n+\t\tif (op->data.dir == SPI_MEM_DATA_IN) {\n+\t\t\tif (op->dummy.nbytes) {\n+\t\t\t\ttc |= TRAMODE_DR;\n+\t\t\t\ttc |= FIELD_PREP(TCTRL_DUMMY_CNT_MASK,\n+\t\t\t\t\t\t op->dummy.nbytes - 1);\n+\t\t\t\tif (op->data.buswidth == 4)\n+\t\t\t\t\ttc |= TCTRL_TOKEN_EN;\n+\t\t\t} else {\n+\t\t\t\ttc |= TRAMODE_RO;\n+\t\t\t}\n+\t\t\ttc |= FIELD_PREP(RCNT_MASK, op->data.nbytes - 1);\n+\t\t} else {\n+\t\t\ttc |= TRAMODE_WO;\n+\t\t\ttc |= FIELD_PREP(WCNT_MASK, op->data.nbytes - 1);\n+\t\t}\n+\t} else {\n+\t\ttc |= TRAMODE_NONE;\n+\t}\n+\n+\tatcspi200_write(priv, ATCSPI200_REG_TCTRL, tc);\n+}\n+\n+static int atcspi200_spi_mem_exec_op(struct spi_slave *slave,\n+\t\t\t\t const struct spi_mem_op *op)\n+{\n+\tstruct udevice *bus = slave->dev->parent;\n+\tstruct atcspi200_priv *priv = dev_get_priv(bus);\n+\tu32 format;\n+\tint ret;\n+\n+\t/* Update address length in format register if needed */\n+\tif (op->addr.nbytes) {\n+\t\tformat = atcspi200_read(priv, ATCSPI200_REG_FORMAT);\n+\t\tformat &= ~ADDR_LEN_MASK;\n+\t\tformat |= FIELD_PREP(ADDR_LEN_MASK, op->addr.nbytes - 1);\n+\t\tatcspi200_write(priv, ATCSPI200_REG_FORMAT, format);\n+\t}\n+\n+\t/* Set up transfer control for this operation */\n+\tatcspi200_set_transfer_ctl(priv, op);\n+\n+\t/* Write address and command to hardware */\n+\tif (op->addr.nbytes)\n+\t\tatcspi200_write(priv, ATCSPI200_REG_ADDR, op->addr.val);\n+\tatcspi200_write(priv, ATCSPI200_REG_CMD, op->cmd.opcode);\n+\n+\t/* Transfer data via PIO */\n+\tif (op->data.nbytes) {\n+\t\tvoid *din = NULL;\n+\t\tconst void *dout = NULL;\n+\n+\t\tif (op->data.dir == SPI_MEM_DATA_IN)\n+\t\t\tdin = op->data.buf.in;\n+\t\telse\n+\t\t\tdout = op->data.buf.out;\n+\n+\t\tatcspi200_pio_transfer(priv, din, dout, op->data.nbytes);\n+\t}\n+\n+\tret = atcspi200_hw_stop(priv);\n+\n+\treturn ret;\n+}\n+\n+static int atcspi200_spi_adjust_op_size(struct spi_slave *slave,\n+\t\t\t\t\tstruct spi_mem_op *op)\n+{\n+\top->data.nbytes = min(op->data.nbytes, (unsigned int)MAX_TRANSFER_LEN);\n+\treturn 0;\n+}\n+\n static int atcspi200_spi_set_speed(struct udevice *bus, uint max_hz)\n {\n \tstruct atcspi200_priv *priv = dev_get_priv(bus);\n@@ -390,12 +478,18 @@ static int atcspi200_spi_of_to_plat(struct udevice *bus)\n \treturn 0;\n }\n \n+static const struct spi_controller_mem_ops atcspi200_spi_mem_ops = {\n+\t.exec_op = atcspi200_spi_mem_exec_op,\n+\t.adjust_op_size = atcspi200_spi_adjust_op_size,\n+};\n+\n static const struct dm_spi_ops atcspi200_spi_ops = {\n \t.claim_bus\t= atcspi200_spi_claim_bus,\n \t.release_bus\t= atcspi200_spi_release_bus,\n \t.xfer\t\t= atcspi200_spi_xfer,\n \t.set_speed\t= atcspi200_spi_set_speed,\n \t.set_mode\t= atcspi200_spi_set_mode,\n+\t.mem_ops\t= &atcspi200_spi_mem_ops,\n };\n \n static const struct udevice_id atcspi200_spi_ids[] = {\n", "prefixes": [ "5/8" ] }