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GET /api/patches/2224154/?format=api
{ "id": 2224154, "url": "http://patchwork.ozlabs.org/api/patches/2224154/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/492f57418f134cc402d249591293d9c44526ad53.1776381841.git.nicolinc@nvidia.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<492f57418f134cc402d249591293d9c44526ad53.1776381841.git.nicolinc@nvidia.com>", "list_archive_url": null, "date": "2026-04-16T23:28:38", "name": "[v3,09/11] iommu/arm-smmu-v3: Replace smmu with master in arm_smmu_inv", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "54941a5e558c73b35cee58ea3d00c0b445623d87", "submitter": { "id": 82183, "url": "http://patchwork.ozlabs.org/api/people/82183/?format=api", "name": "Nicolin Chen", "email": "nicolinc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/492f57418f134cc402d249591293d9c44526ad53.1776381841.git.nicolinc@nvidia.com/mbox/", "series": [ { "id": 500217, "url": "http://patchwork.ozlabs.org/api/series/500217/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=500217", "date": "2026-04-16T23:28:31", "name": "iommu/arm-smmu-v3: Quarantine device upon ATC invalidation timeout", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/500217/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224154/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224154/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-52669-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=YkXpY61a;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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pr=C", "From": "Nicolin Chen <nicolinc@nvidia.com>", "To": "Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, \"Joerg\n Roedel\" <joro@8bytes.org>, Bjorn Helgaas <bhelgaas@google.com>, \"Jason\n Gunthorpe\" <jgg@nvidia.com>", "CC": "\"Rafael J . Wysocki\" <rafael@kernel.org>, Len Brown <lenb@kernel.org>,\n\tPranjal Shrivastava <praan@google.com>, Mostafa Saleh <smostafa@google.com>,\n\tLu Baolu <baolu.lu@linux.intel.com>, Kevin Tian <kevin.tian@intel.com>,\n\t<linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>,\n\t<linux-kernel@vger.kernel.org>, <linux-acpi@vger.kernel.org>,\n\t<linux-pci@vger.kernel.org>, <vsethi@nvidia.com>, Shuai Xue\n\t<xueshuai@linux.alibaba.com>", "Subject": "[PATCH v3 09/11] iommu/arm-smmu-v3: Replace smmu with master in\n arm_smmu_inv", "Date": "Thu, 16 Apr 2026 16:28:38 -0700", "Message-ID": "\n <492f57418f134cc402d249591293d9c44526ad53.1776381841.git.nicolinc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<cover.1776381841.git.nicolinc@nvidia.com>", "References": "<cover.1776381841.git.nicolinc@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": 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"\n\t22WVXzQGPy5XueFSrvfNHR/liNT0Ghv1Ke71Y+IGCja1Joa+FkE1XfqYxsIqoz7Krhz0R4LixGPICGdl47zjFLqO/eNSGT3v6XA5bjaX+1R2WW2ge1346jPsRmxA+5NRYZjBONTaU6B58g/Uu6LQ8/YWZZy7xvRObEVFLUUe7BcaJB7CSS7LRYG1FPUcZ6RnJGotPSBxFNyx2fGHPHYocxSoeY3PDAXu2MbCWRp6+mZS/sxAvti9Ls6HPtdLZQH86g0mU6g6+JyvaA9QFxHDEoc1QACp1jsCAihfqgsiR1+i+5GKT4YR5AH8ZC6e+c+2XQMiHNQ3PpZcM1U+Xds8iMOyUAFQARbo8LF6ftqQYl3bYwevrGEdlyTREoxiAtyL1NYfY1SwreSzL3m1vEBTQkni94hzPvntbzndTFCfecQz2VubFpmIIsqGOCtAN1WMViwJtI7NzMAEMoazG8u7IM5XiRRiVvZ4hGkQMUR+TAAg+jYIFGJSGqgqKJ1QOMrJmxAGCduzCK1i0vAaTMlqW9is2URRhjglIWZ//3K63QZuyB6W7Sj2y/Mny49HKjibwQFUpS6+NltKIM/ZgzxQvD/XZp22SWhvXkP+hn2AEf3XlY5QqtJcsbdUpvVZxUlTVkB4Z7AF4Q4FnCJvRLnO/JKhytB4sQhy/xDxn5RqERp7S4zNBD1oPWeagKf3Z7atbNBftUk+GA2ziXgAsEBkfcnKTiXnMW7h7cAriHGAFxktxN6mvTKwOEM2/ggMPeNAkfFSZJpWO592cMlMlQGf3Q==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(1800799024)(36860700016)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\trQ7irSzsByIcC6YOTWeFY8quBzI6EeKK1cYdlghIFqgCJScMWYvSm9eInjHVq7yeQJ7TUnnZYrtjBDcsY8O1PL6ds9jdZR90XS0qTu5jk9eU7B125JFwvDNNUiYWyEWgUURiG9GKiLLtUMOm27YBHio6/uFim/ANPHw6m2zauVeHem5PUqdH+95nMPSiRVzmeRH6VbSwzxOx5BKemaDbnVvnuILyLHdjj3Tdb1ba8rGgxkKq68wiehymI52jA/9N7COQDBnhCaIv0CjOjgQ10JWuXMQiWCGHHa8v/z1T9pSL71fQGEPwnP7+UCE6kxdNAz8xyOCeZJUrcSR5Bn2NYrxbUoe7NjWVw30iPXun1swjXYM/T8Fd6f5rqZTzpjvQfzWyxid5uaRkhKKos6M1Ew5Bq2P75OVhJ78cpp8G8/a0gPcMwDZqH033si2ySWZR", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Apr 2026 23:29:55.7302\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a16bd79d-40c4-46d5-2faa-08de9c101162", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tCO1PEPF00012E7F.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH2PR12MB4215" }, "content": "Storing master allows to backtrack the master pointer from an invalidation\nentry, which will be useful when handling ATC invalidation time outs.\n\nNo functional changes.\n\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\n---\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 +-\n .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 34 +++++++++++--------\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 24 +++++++------\n 3 files changed, 33 insertions(+), 27 deletions(-)", "diff": "diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\nindex 1d72e5040ea97..26e0ee0bb5b45 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n@@ -662,7 +662,7 @@ enum arm_smmu_inv_type {\n };\n \n struct arm_smmu_inv {\n-\tstruct arm_smmu_device *smmu;\n+\tstruct arm_smmu_master *master;\n \tu8 type;\n \tu8 size_opcode;\n \tu8 nsize_opcode;\ndiff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c\nindex add671363c828..ef0c0bfe44206 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c\n@@ -653,39 +653,43 @@ static void arm_smmu_v3_invs_test_verify(struct kunit *test,\n \t}\n }\n \n+static struct arm_smmu_master invs_master = {\n+\t.smmu = &smmu,\n+};\n+\n static struct arm_smmu_invs invs1 = {\n \t.num_invs = 3,\n-\t.inv = { { .type = INV_TYPE_S2_VMID, .id = 1, },\n-\t\t { .type = INV_TYPE_S2_VMID_S1_CLEAR, .id = 1, },\n-\t\t { .type = INV_TYPE_ATS, .id = 3, }, },\n+\t.inv = { { .master = &invs_master, .type = INV_TYPE_S2_VMID, .id = 1, },\n+\t\t { .master = &invs_master, .type = INV_TYPE_S2_VMID_S1_CLEAR, .id = 1, },\n+\t\t { .master = &invs_master, .type = INV_TYPE_ATS, .id = 3, }, },\n };\n \n static struct arm_smmu_invs invs2 = {\n \t.num_invs = 3,\n-\t.inv = { { .type = INV_TYPE_S2_VMID, .id = 1, }, /* duplicated */\n-\t\t { .type = INV_TYPE_ATS, .id = 4, },\n-\t\t { .type = INV_TYPE_ATS, .id = 5, }, },\n+\t.inv = { { .master = &invs_master, .type = INV_TYPE_S2_VMID, .id = 1, }, /* dup */\n+\t\t { .master = &invs_master, .type = INV_TYPE_ATS, .id = 4, },\n+\t\t { .master = &invs_master, .type = INV_TYPE_ATS, .id = 5, }, },\n };\n \n static struct arm_smmu_invs invs3 = {\n \t.num_invs = 3,\n-\t.inv = { { .type = INV_TYPE_S2_VMID, .id = 1, }, /* duplicated */\n-\t\t { .type = INV_TYPE_ATS, .id = 5, }, /* recover a trash */\n-\t\t { .type = INV_TYPE_ATS, .id = 6, }, },\n+\t.inv = { { .master = &invs_master, .type = INV_TYPE_S2_VMID, .id = 1, }, /* dup */\n+\t\t { .master = &invs_master, .type = INV_TYPE_ATS, .id = 5, }, /* recover a trash */\n+\t\t { .master = &invs_master, .type = INV_TYPE_ATS, .id = 6, }, },\n };\n \n static struct arm_smmu_invs invs4 = {\n \t.num_invs = 3,\n-\t.inv = { { .type = INV_TYPE_ATS, .id = 10, .ssid = 1 },\n-\t\t { .type = INV_TYPE_ATS, .id = 10, .ssid = 3 },\n-\t\t { .type = INV_TYPE_ATS, .id = 12, .ssid = 1 }, },\n+\t.inv = { { .master = &invs_master, .type = INV_TYPE_ATS, .id = 10, .ssid = 1 },\n+\t\t { .master = &invs_master, .type = INV_TYPE_ATS, .id = 10, .ssid = 3 },\n+\t\t { .master = &invs_master, .type = INV_TYPE_ATS, .id = 12, .ssid = 1 }, },\n };\n \n static struct arm_smmu_invs invs5 = {\n \t.num_invs = 3,\n-\t.inv = { { .type = INV_TYPE_ATS, .id = 10, .ssid = 2 },\n-\t\t { .type = INV_TYPE_ATS, .id = 10, .ssid = 3 }, /* duplicate */\n-\t\t { .type = INV_TYPE_ATS, .id = 12, .ssid = 2 }, },\n+\t.inv = { { .master = &invs_master, .type = INV_TYPE_ATS, .id = 10, .ssid = 2 },\n+\t\t { .master = &invs_master, .type = INV_TYPE_ATS, .id = 10, .ssid = 3 }, /* dup */\n+\t\t { .master = &invs_master, .type = INV_TYPE_ATS, .id = 12, .ssid = 2 }, },\n };\n \n static void arm_smmu_v3_invs_test(struct kunit *test)\ndiff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\nindex f47943f860f3d..13f225f704e73 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n@@ -1092,8 +1092,9 @@ arm_smmu_invs_iter_next(struct arm_smmu_invs *invs, size_t next, size_t *idx)\n static int arm_smmu_inv_cmp(const struct arm_smmu_inv *inv_l,\n \t\t\t const struct arm_smmu_inv *inv_r)\n {\n-\tif (inv_l->smmu != inv_r->smmu)\n-\t\treturn cmp_int((uintptr_t)inv_l->smmu, (uintptr_t)inv_r->smmu);\n+\tif (inv_l->master->smmu != inv_r->master->smmu)\n+\t\treturn cmp_int((uintptr_t)inv_l->master->smmu,\n+\t\t\t (uintptr_t)inv_r->master->smmu);\n \tif (inv_l->type != inv_r->type)\n \t\treturn cmp_int(inv_l->type, inv_r->type);\n \tif (inv_l->id != inv_r->id)\n@@ -2650,22 +2651,22 @@ static void arm_smmu_inv_to_cmdq_batch(struct arm_smmu_inv *inv,\n \t\t\t\t unsigned long iova, size_t size,\n \t\t\t\t unsigned int granule)\n {\n-\tif (arm_smmu_inv_size_too_big(inv->smmu, size, granule)) {\n+\tif (arm_smmu_inv_size_too_big(inv->master->smmu, size, granule)) {\n \t\tcmd->opcode = inv->nsize_opcode;\n-\t\tarm_smmu_cmdq_batch_add(inv->smmu, cmds, cmd);\n+\t\tarm_smmu_cmdq_batch_add(inv->master->smmu, cmds, cmd);\n \t\treturn;\n \t}\n \n \tcmd->opcode = inv->size_opcode;\n-\tarm_smmu_cmdq_batch_add_range(inv->smmu, cmds, cmd, iova, size, granule,\n-\t\t\t\t inv->pgsize);\n+\tarm_smmu_cmdq_batch_add_range(inv->master->smmu, cmds, cmd, iova, size,\n+\t\t\t\t granule, inv->pgsize);\n }\n \n static inline bool arm_smmu_invs_end_batch(struct arm_smmu_inv *cur,\n \t\t\t\t\t struct arm_smmu_inv *next)\n {\n \t/* Changing smmu means changing command queue */\n-\tif (cur->smmu != next->smmu)\n+\tif (cur->master->smmu != next->master->smmu)\n \t\treturn true;\n \t/* The batch for S2 TLBI must be done before nested S1 ASIDs */\n \tif (cur->type != INV_TYPE_S2_VMID_S1_CLEAR &&\n@@ -2692,7 +2693,7 @@ static void __arm_smmu_domain_inv_range(struct arm_smmu_invs *invs,\n \t\tif (READ_ONCE(cur->users))\n \t\t\tbreak;\n \twhile (cur != end) {\n-\t\tstruct arm_smmu_device *smmu = cur->smmu;\n+\t\tstruct arm_smmu_device *smmu = cur->master->smmu;\n \t\tstruct arm_smmu_cmdq_ent cmd = {\n \t\t\t/*\n \t\t\t * Pick size_opcode to run arm_smmu_get_cmdq(). This can\n@@ -2721,7 +2722,8 @@ static void __arm_smmu_domain_inv_range(struct arm_smmu_invs *invs,\n \t\t\tbreak;\n \t\tcase INV_TYPE_S2_VMID_S1_CLEAR:\n \t\t\t/* CMDQ_OP_TLBI_S12_VMALL already flushed S1 entries */\n-\t\t\tif (arm_smmu_inv_size_too_big(cur->smmu, size, granule))\n+\t\t\tif (arm_smmu_inv_size_too_big(cur->master->smmu, size,\n+\t\t\t\t\t\t granule))\n \t\t\t\tbreak;\n \t\t\tcmd.tlbi.vmid = cur->id;\n \t\t\tarm_smmu_cmdq_batch_add(smmu, &cmds, &cmd);\n@@ -3246,7 +3248,7 @@ arm_smmu_master_build_inv(struct arm_smmu_master *master,\n {\n \tstruct arm_smmu_invs *build_invs = master->build_invs;\n \tstruct arm_smmu_inv *cur, inv = {\n-\t\t.smmu = master->smmu,\n+\t\t.master = master,\n \t\t.type = type,\n \t\t.id = id,\n \t\t.pgsize = pgsize,\n@@ -3478,7 +3480,7 @@ static void arm_smmu_inv_flush_iotlb_tag(struct arm_smmu_inv *inv)\n \t}\n \n \tcmd.opcode = inv->nsize_opcode;\n-\tarm_smmu_cmdq_issue_cmd_with_sync(inv->smmu, &cmd);\n+\tarm_smmu_cmdq_issue_cmd_with_sync(inv->master->smmu, &cmd);\n }\n \n /* Should be installed after arm_smmu_install_ste_for_dev() */\n", "prefixes": [ "v3", "09/11" ] }