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GET /api/patches/2224151/?format=api
{ "id": 2224151, "url": "http://patchwork.ozlabs.org/api/patches/2224151/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/5bf2e259f80696c498cb15f40452862e4b43a295.1776381841.git.nicolinc@nvidia.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<5bf2e259f80696c498cb15f40452862e4b43a295.1776381841.git.nicolinc@nvidia.com>", "list_archive_url": null, "date": "2026-04-16T23:28:33", "name": "[v3,04/11] iommu: Add __iommu_group_block_device helper", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a09c01e3c40509151a02613e63ebabf4df7dd311", "submitter": { "id": 82183, "url": "http://patchwork.ozlabs.org/api/people/82183/?format=api", "name": "Nicolin Chen", "email": "nicolinc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/5bf2e259f80696c498cb15f40452862e4b43a295.1776381841.git.nicolinc@nvidia.com/mbox/", "series": [ { "id": 500217, "url": "http://patchwork.ozlabs.org/api/series/500217/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=500217", "date": "2026-04-16T23:28:31", "name": "iommu/arm-smmu-v3: Quarantine device upon ATC invalidation timeout", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/500217/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224151/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224151/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-52664-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=uNgX+/qG;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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pr=C", "From": "Nicolin Chen <nicolinc@nvidia.com>", "To": "Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, \"Joerg\n Roedel\" <joro@8bytes.org>, Bjorn Helgaas <bhelgaas@google.com>, \"Jason\n Gunthorpe\" <jgg@nvidia.com>", "CC": "\"Rafael J . Wysocki\" <rafael@kernel.org>, Len Brown <lenb@kernel.org>,\n\tPranjal Shrivastava <praan@google.com>, Mostafa Saleh <smostafa@google.com>,\n\tLu Baolu <baolu.lu@linux.intel.com>, Kevin Tian <kevin.tian@intel.com>,\n\t<linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>,\n\t<linux-kernel@vger.kernel.org>, <linux-acpi@vger.kernel.org>,\n\t<linux-pci@vger.kernel.org>, <vsethi@nvidia.com>, Shuai Xue\n\t<xueshuai@linux.alibaba.com>", "Subject": "[PATCH v3 04/11] iommu: Add __iommu_group_block_device helper", "Date": "Thu, 16 Apr 2026 16:28:33 -0700", "Message-ID": "\n <5bf2e259f80696c498cb15f40452862e4b43a295.1776381841.git.nicolinc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<cover.1776381841.git.nicolinc@nvidia.com>", "References": "<cover.1776381841.git.nicolinc@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", 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"\n\tslhvTyDS+DerOFXQhC7YfgrFZZMYmw3E+8lGrYRckARHhcYVQdw7dwX1lWIcCY1xvpyP8rjof3aj4P4FsoPz7DC6X+MUC68LX/LRiv4fhitXOlIs2hf6uyAl4sKHUTbhR7ltcaZenAUuIRxmQkYVEMqInDYJPvnrUyU8EGqLoHGHr30XV8kl2izToXmiQAEa5BL7SEJvedns7erIYhF6A2TKn2M4v4hFhkiaDMb05H1HOKGV9qjxEe3BX20m243qchRwdGG6l/wOPWRc8HcEBLYj10Q3yWXNJYEArfkvBCZRM+gXaBfime4qSuZomydJKgFcz+05DE1xARddfM2RimS48q4APMVyvKpsbXP594pV/f/grVuqgxZ1sRLvV9BV3H+aEn42HfQZsPJQQq+dYBSX2hQGvOsKQ78qX8PkuAJ+4Mv6uQq4mBj93y4i6IlU2NjHXtvQERSwbIY1CF6BF9k71iCbDYZGQwcm5K//u6w4yBKh6preX3x52sIcTCVgjpdM0p+BHp71NbE70NWUFSEgOoNlcqvGV4b2CoCDvXNP3nMWgDAK/ebWa+4BriCAVP6awdgBXPDGW5Pe9sQnofLojpSrSF1HYrsrj0DlzBJaTSL7ewWNYTj/4SvbrMNdzb26NEQzmPzlUS89iNZvLFRJs01Nwx15xDWVZCXjZ47whCsI2oYw/MZNNTYb7o7F5XSUCbb64onoLOM+x6iU1OQGcheYO1vpUHcc6RvfLoVC2dYR+5RfcuHCC1RzvIfXaGuEvNumpmGSTlhGUeCaZg==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700016)(7416014)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\toN3rIlbDp1LkvW1b80soxbQZwmWCn2ca5fnBYNXNfkQ3Xh86dvFWR694PlYT47EMSrw+LUs9d6Ih/0GZCyaZQKLILgqscpC7/GozjXMN7b6amK/2dFumWfjyrvhcsNAwWlw8bz4moy/1CJhT9Z+gg3SiaE1Elb4kxHEmblA8O+ayS2Ui3ym1WtTjuCKJlQ7C3jGywxGtud3FgPl0RQSDUvrXX6GWzCIOVOByPEDMFCrqu/XtZqezSK2UznH5GRoqKxMu1Mm9hNd6CpkXwjxCJWoUcHMoLUgF6GlPeiU9uB8DDCCC2Dk7BUD7Z7o/PmIpuHD6eYwmVY5SRUIWyyO28dcBBSDUbNN0JZM/cjzahAHaPS5f3H/iTqhO1zML7gMTsPx0pc0218uYef0XfkdoskSZgoXaoZFaI52rnSTF4I1JI8EhgIpRZBMSlkvF05Pc", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Apr 2026 23:29:20.8575\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ef28d998-73b5-4a74-8462-08de9c0ffc9e", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tSJ1PEPF00002316.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB4354" }, "content": "Move the RID/PASID blocking routine into a separate helper, which will be\nreused by a new function to quarantine the device but does not bother the\ngdev->reset_depth counter.\n\nNo functional changes.\n\nSuggested-by: Kevin Tian <kevin.tian@intel.com>\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\n---\n drivers/iommu/iommu.c | 99 ++++++++++++++++++++++++-------------------\n 1 file changed, 56 insertions(+), 43 deletions(-)", "diff": "diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c\nindex df23ef0a26e6c..768ac728b4cc3 100644\n--- a/drivers/iommu/iommu.c\n+++ b/drivers/iommu/iommu.c\n@@ -3958,6 +3958,57 @@ int iommu_replace_group_handle(struct iommu_group *group,\n }\n EXPORT_SYMBOL_NS_GPL(iommu_replace_group_handle, \"IOMMUFD_INTERNAL\");\n \n+static int __iommu_group_block_device(struct iommu_group *group,\n+\t\t\t\t struct group_device *gdev)\n+{\n+\tunsigned long pasid;\n+\tvoid *entry;\n+\tint ret;\n+\n+\tlockdep_assert_held(&group->mutex);\n+\n+\t/* Device might be already blocked for a quarantine */\n+\tif (gdev->blocked)\n+\t\treturn 0;\n+\n+\tret = __iommu_group_alloc_blocking_domain(group);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Stage RID domain at blocking_domain while retaining group->domain */\n+\tif (group->domain != group->blocking_domain) {\n+\t\tret = __iommu_attach_device(group->blocking_domain, gdev->dev,\n+\t\t\t\t\t group->domain);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\t/*\n+\t * Update gdev->blocked upon the domain change, as it is used to return\n+\t * the correct domain in iommu_driver_get_domain_for_dev() that might be\n+\t * called in a set_dev_pasid callback function.\n+\t */\n+\tgdev->blocked = true;\n+\n+\t/*\n+\t * Stage PASID domains at blocking_domain while retaining pasid_array.\n+\t *\n+\t * The pasid_array is mostly fenced by group->mutex, except one reader\n+\t * in iommu_attach_handle_get(), so it's safe to read without xa_lock.\n+\t */\n+\tif (gdev->dev->iommu->max_pasids > 0) {\n+\t\txa_for_each_start(&group->pasid_array, pasid, entry, 1) {\n+\t\t\tstruct iommu_domain *pasid_dom =\n+\t\t\t\tpasid_array_entry_to_domain(entry);\n+\n+\t\t\tiommu_remove_dev_pasid(gdev->dev, pasid, pasid_dom);\n+\t\t}\n+\t}\n+\n+\tgroup->recovery_cnt++;\n+\treturn 0;\n+}\n+\n /**\n * pci_dev_reset_iommu_prepare() - Block IOMMU to prepare for a PCI device reset\n * @pdev: PCI device that is going to enter a reset routine\n@@ -3988,8 +4039,6 @@ int pci_dev_reset_iommu_prepare(struct pci_dev *pdev)\n {\n \tstruct iommu_group *group = pdev->dev.iommu_group;\n \tstruct group_device *gdev;\n-\tunsigned long pasid;\n-\tvoid *entry;\n \tint ret;\n \n \tif (!pci_ats_supported(pdev) || !dev_has_iommu(&pdev->dev))\n@@ -4003,50 +4052,14 @@ int pci_dev_reset_iommu_prepare(struct pci_dev *pdev)\n \n \tif (gdev->reset_depth++)\n \t\treturn 0;\n-\t/* Device might be already blocked for a quarantine */\n-\tif (gdev->blocked)\n-\t\treturn 0;\n-\n-\tret = __iommu_group_alloc_blocking_domain(group);\n-\tif (ret)\n-\t\tgoto err_depth;\n \n-\t/* Stage RID domain at blocking_domain while retaining group->domain */\n-\tif (group->domain != group->blocking_domain) {\n-\t\tret = __iommu_attach_device(group->blocking_domain, &pdev->dev,\n-\t\t\t\t\t group->domain);\n-\t\tif (ret)\n-\t\t\tgoto err_depth;\n-\t}\n-\n-\t/*\n-\t * Update gdev->blocked upon the domain change, as it is used to return\n-\t * the correct domain in iommu_driver_get_domain_for_dev() that might be\n-\t * called in a set_dev_pasid callback function.\n-\t */\n-\tgdev->blocked = true;\n-\n-\t/*\n-\t * Stage PASID domains at blocking_domain while retaining pasid_array.\n-\t *\n-\t * The pasid_array is mostly fenced by group->mutex, except one reader\n-\t * in iommu_attach_handle_get(), so it's safe to read without xa_lock.\n-\t */\n-\tif (pdev->dev.iommu->max_pasids > 0) {\n-\t\txa_for_each_start(&group->pasid_array, pasid, entry, 1) {\n-\t\t\tstruct iommu_domain *pasid_dom =\n-\t\t\t\tpasid_array_entry_to_domain(entry);\n-\n-\t\t\tiommu_remove_dev_pasid(&pdev->dev, pasid, pasid_dom);\n-\t\t}\n+\tret = __iommu_group_block_device(group, gdev);\n+\tif (ret) {\n+\t\tgdev->reset_depth--;\n+\t\treturn ret;\n \t}\n \n-\tgroup->recovery_cnt++;\n-\treturn ret;\n-\n-err_depth:\n-\tgdev->reset_depth--;\n-\treturn ret;\n+\treturn 0;\n }\n EXPORT_SYMBOL_GPL(pci_dev_reset_iommu_prepare);\n \n", "prefixes": [ "v3", "04/11" ] }