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GET /api/patches/2224147/?format=api
{ "id": 2224147, "url": "http://patchwork.ozlabs.org/api/patches/2224147/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/dc42b28c08606c29f6e30772a92cf9569910829f.1776381841.git.nicolinc@nvidia.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<dc42b28c08606c29f6e30772a92cf9569910829f.1776381841.git.nicolinc@nvidia.com>", "list_archive_url": null, "date": "2026-04-16T23:28:37", "name": "[v3,08/11] iommu/arm-smmu-v3: Mark ATC invalidate timeouts via lockless bitmap", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ca586e29dd86d6fd22396ff2581517adc78b876d", "submitter": { "id": 82183, "url": "http://patchwork.ozlabs.org/api/people/82183/?format=api", "name": "Nicolin Chen", "email": "nicolinc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/dc42b28c08606c29f6e30772a92cf9569910829f.1776381841.git.nicolinc@nvidia.com/mbox/", "series": [ { "id": 500217, "url": "http://patchwork.ozlabs.org/api/series/500217/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=500217", "date": "2026-04-16T23:28:31", "name": "iommu/arm-smmu-v3: Quarantine device upon ATC invalidation timeout", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/500217/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224147/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224147/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-52668-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=YuyH4+yg;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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pr=C", "From": "Nicolin Chen <nicolinc@nvidia.com>", "To": "Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, \"Joerg\n Roedel\" <joro@8bytes.org>, Bjorn Helgaas <bhelgaas@google.com>, \"Jason\n Gunthorpe\" <jgg@nvidia.com>", "CC": "\"Rafael J . Wysocki\" <rafael@kernel.org>, Len Brown <lenb@kernel.org>,\n\tPranjal Shrivastava <praan@google.com>, Mostafa Saleh <smostafa@google.com>,\n\tLu Baolu <baolu.lu@linux.intel.com>, Kevin Tian <kevin.tian@intel.com>,\n\t<linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>,\n\t<linux-kernel@vger.kernel.org>, <linux-acpi@vger.kernel.org>,\n\t<linux-pci@vger.kernel.org>, <vsethi@nvidia.com>, Shuai Xue\n\t<xueshuai@linux.alibaba.com>", "Subject": "[PATCH v3 08/11] iommu/arm-smmu-v3: Mark ATC invalidate timeouts via\n lockless bitmap", "Date": "Thu, 16 Apr 2026 16:28:37 -0700", "Message-ID": "\n <dc42b28c08606c29f6e30772a92cf9569910829f.1776381841.git.nicolinc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<cover.1776381841.git.nicolinc@nvidia.com>", "References": "<cover.1776381841.git.nicolinc@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SJ1PEPF00002315:EE_|DM4PR12MB7767:EE_", "X-MS-Office365-Filtering-Correlation-Id": "7e144c92-42d2-4ca5-4fc4-08de9c1008b9", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|7416014|376014|36860700016|82310400026|22082099003|18002099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n\tU2GQvC/BxKQrEe2zoHXu1C9EZVSK4MslMTGshFTRvVcV7Jt3cUbXoyiYg3hUIXZMFFQpZJsM8ad4X6krKbGauosZ67ypSMke8Rbs1rmKmMJCvxyu8BcvzK10vuztam/JV5xLoVV9SyWaENARB+42AIRJkON4xmV4w/+OdhDGjJ6bMciMsIGDVoQsE4tqHbCRXOp6/CP7NVtuRb1zavo+64R8f7qtpMIOAhIc7Iq8wUp2Jk2WoJ6BGkE2UNkx65cZfmJufqg9D8iYEFj7SwDfmQ3DZZn/FlyYujGjhthkZ6wA6YX2uO/BqOiSUjyCxKLDaiWVTwEtlr80yZyRsq5D8rNlsU/bFlTHe/EzIlONunyAutjSUXdXirRk3TKYqG62UIAn2AIIyc/odKYOfixSLIQHaaz006PFaTE8XkmyNhXoYjrncXVzJzYOiCxz3BbJSNQI8mI6rmQJovRfz5IpXoTOSQJ5XMbiXRsTKMrBb0regB4JBk8qCCurfmMjEcXv8CczRtCBn/a3xhndnqhFxwCcLW58CxYt31NsOcGjJQE2rcB5oVKhvaL4KZqZCSBWeW2A/ZIjtJ6weojXPLhVS1dwUtIGTR2tbqNT//LSiUh3nG0IdmTlqwdzqnamzwYPc9bQC5xNPiNFSokUZQHDMz5mAiPkU+0EYnGGXY8NkMwFh17apWSFA92NTfd5K1+OlQUhaUShGOb3fw8Mf+Jvg45fcmLdltQTm7w+EudkC2TRuwYMqqHOdfPyQH+Hl63m+xaQQ2Wc6u6NzJZmSqcuNQ==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(36860700016)(82310400026)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t6gNiJ/WSBj7fASdxqiYq4MFzwtHWbeppqP6Q0ppTKIIMQ9tIG16wZKaw6ZtRHPB2TEhUxCyyAo1umgzTx02GmY3E/RWP/Snu3FKPx6Kz03WDhJBc5X9DRHW/NolyxtP6xJPyO6zHvd4L6Gb3/2SnyqAP7sOM/nabCRHeCv67fGkEahEHVn9KHEqXa6cZj2yM9DsnOWUrQFuzWzuFJ+UevrTFnXtdMrejl0QRgtQZwmWGXGSQm/DfPdfnceWtiTnandP7TYsovJbPK44l3Bc5SfZcB70dK1Fo2vb0qmcywJaO8Oui5I/QIFSMexQ4vaEe0etOg1oMNa3B/knCnW6LCElk9TW1q2dIClsz5VpgINxqAEIk7lTQOC3zUqszOfMfo6lk4XUBEIAlHqlwM7kxuUbXs1cmd9kt6085PNdZwLgDmfDUIXu6t4GS4iXthspn", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Apr 2026 23:29:41.1687\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 7e144c92-42d2-4ca5-4fc4-08de9c1008b9", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tSJ1PEPF00002315.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB7767" }, "content": "An ATC invalidation timeout is a fatal error. While the SMMUv3 hardware is\naware of the timeout via a GERROR interrupt, the driver thread issuing the\ncommands lacks a direct mechanism to verify whether its specific batch was\nthe cause or not, as polling the CMD_SYNC status doesn't natively return a\nfailure code, making it very difficult to coordinate per-device recovery.\n\nIntroduce an atc_sync_timeouts bitmap in the cmdq structure to bridge this\ngap. When the ISR detects an ATC timeout, set the bit corresponding to the\nphysical CMDQ index of the faulting CMD_SYNC command.\n\nOn the issuer side, after polling completes (or times out), test and clear\nits dedicated bit. If set, return -EIO to trigger device quarantine.\n\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\n---\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 +\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 41 ++++++++++++++++++++-\n 2 files changed, 41 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\nindex ef42df4753ec4..1d72e5040ea97 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n@@ -633,6 +633,7 @@ struct arm_smmu_cmdq {\n \tatomic_long_t\t\t\t*valid_map;\n \tatomic_t\t\t\towner_prod;\n \tatomic_t\t\t\tlock;\n+\tunsigned long\t\t\t*atc_sync_timeouts;\n \tbool\t\t\t\t(*supports_cmd)(struct arm_smmu_cmdq_ent *ent);\n };\n \ndiff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\nindex f6901c5437edc..f47943f860f3d 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n@@ -445,7 +445,10 @@ void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu,\n \t\t * at the CMD_SYNC. Attempt to complete other pending commands\n \t\t * by repeating the CMD_SYNC, though we might well end up back\n \t\t * here since the ATC invalidation may still be pending.\n+\t\t *\n+\t\t * Mark the faulty batch in the bitmap for the issuer to match.\n \t\t */\n+\t\tset_bit(Q_IDX(&q->llq, cons), cmdq->atc_sync_timeouts);\n \t\treturn;\n \tcase CMDQ_ERR_CERROR_ILL_IDX:\n \tdefault:\n@@ -895,9 +898,40 @@ int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu,\n \n \t/* 5. If we are inserting a CMD_SYNC, we must wait for it to complete */\n \tif (sync) {\n+\t\tu32 sync_prod;\n+\n \t\tllq.prod = queue_inc_prod_n(&llq, n);\n+\t\tsync_prod = llq.prod;\n+\t\t/*\n+\t\t * If there is an unhandled ATC timeout, we will have no choice\n+\t\t * but to ignore it, since this was left on the ring buffer in\n+\t\t * the last round. And we certainly don't want it to affect the\n+\t\t * current issue.\n+\t\t */\n+\t\tclear_bit(Q_IDX(&llq, sync_prod), cmdq->atc_sync_timeouts);\n+\n \t\tret = arm_smmu_cmdq_poll_until_sync(smmu, cmdq, &llq);\n-\t\tif (ret) {\n+\n+\t\t/*\n+\t\t * Test atc_sync_timeouts first and see if there is ATC timeout\n+\t\t * resulted from this cmdlist. Return -EIO to separate from the\n+\t\t * ARM_SMMU_POLL_TIMEOUT_US software timeout.\n+\t\t *\n+\t\t * FIXME possible unhandled ATC invalidation timeout scenario:\n+\t\t * PCI Completion Timeout can be set to a range longer than the\n+\t\t * ARM_SMMU_POLL_TIMEOUT_US software timeout. -ETIMEDOUT can be\n+\t\t * returned by arm_smmu_cmdq_poll_until_sync() while ATC timeout\n+\t\t * might not be flagged on atc_sync_timeouts yet. In this case,\n+\t\t * we can hardly do anything here since the command queue HW is\n+\t\t * still pending on the ATC command.\n+\t\t */\n+\t\tif (test_and_clear_bit(Q_IDX(&llq, sync_prod),\n+\t\t\t\t cmdq->atc_sync_timeouts)) {\n+\t\t\tdev_err_ratelimited(smmu->dev,\n+\t\t\t\t\t \"CMD_SYNC for ATC_INV timeout at prod=0x%08x\\n\",\n+\t\t\t\t\t sync_prod);\n+\t\t\tret = -EIO;\n+\t\t} else if (ret) {\n \t\t\tdev_err_ratelimited(smmu->dev,\n \t\t\t\t\t \"CMD_SYNC timeout at 0x%08x [hwprod 0x%08x, hwcons 0x%08x]\\n\",\n \t\t\t\t\t llq.prod,\n@@ -4458,6 +4492,11 @@ int arm_smmu_cmdq_init(struct arm_smmu_device *smmu,\n \tif (!cmdq->valid_map)\n \t\treturn -ENOMEM;\n \n+\tcmdq->atc_sync_timeouts =\n+\t\tdevm_bitmap_zalloc(smmu->dev, nents, GFP_KERNEL);\n+\tif (!cmdq->atc_sync_timeouts)\n+\t\treturn -ENOMEM;\n+\n \treturn 0;\n }\n \n", "prefixes": [ "v3", "08/11" ] }