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GET /api/patches/2224145/?format=api
{ "id": 2224145, "url": "http://patchwork.ozlabs.org/api/patches/2224145/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/12a224061de4fff9e0725909fd0ba4e14996ff08.1776381841.git.nicolinc@nvidia.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<12a224061de4fff9e0725909fd0ba4e14996ff08.1776381841.git.nicolinc@nvidia.com>", "list_archive_url": null, "date": "2026-04-16T23:28:34", "name": "[v3,05/11] iommu: Change group->devices to RCU-protected list", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "734f8359c61ef6188a36fec7851bf51f6db31d1b", "submitter": { "id": 82183, "url": "http://patchwork.ozlabs.org/api/people/82183/?format=api", "name": "Nicolin Chen", "email": "nicolinc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/12a224061de4fff9e0725909fd0ba4e14996ff08.1776381841.git.nicolinc@nvidia.com/mbox/", "series": [ { "id": 500217, "url": "http://patchwork.ozlabs.org/api/series/500217/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=500217", "date": "2026-04-16T23:28:31", "name": "iommu/arm-smmu-v3: Quarantine device upon ATC invalidation timeout", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/500217/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224145/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224145/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-52665-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=QkkrE/iP;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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pr=C", "From": "Nicolin Chen <nicolinc@nvidia.com>", "To": "Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, \"Joerg\n Roedel\" <joro@8bytes.org>, Bjorn Helgaas <bhelgaas@google.com>, \"Jason\n Gunthorpe\" <jgg@nvidia.com>", "CC": "\"Rafael J . Wysocki\" <rafael@kernel.org>, Len Brown <lenb@kernel.org>,\n\tPranjal Shrivastava <praan@google.com>, Mostafa Saleh <smostafa@google.com>,\n\tLu Baolu <baolu.lu@linux.intel.com>, Kevin Tian <kevin.tian@intel.com>,\n\t<linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>,\n\t<linux-kernel@vger.kernel.org>, <linux-acpi@vger.kernel.org>,\n\t<linux-pci@vger.kernel.org>, <vsethi@nvidia.com>, Shuai Xue\n\t<xueshuai@linux.alibaba.com>", "Subject": "[PATCH v3 05/11] iommu: Change group->devices to RCU-protected list", "Date": "Thu, 16 Apr 2026 16:28:34 -0700", "Message-ID": "\n <12a224061de4fff9e0725909fd0ba4e14996ff08.1776381841.git.nicolinc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<cover.1776381841.git.nicolinc@nvidia.com>", "References": "<cover.1776381841.git.nicolinc@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SJ1PEPF00002315:EE_|CH3PR12MB9217:EE_", "X-MS-Office365-Filtering-Correlation-Id": "b9d50827-81c4-45b4-9464-08de9c10012a", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|7416014|376014|36860700016|82310400026|1800799024|18002099003|56012099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n\tar4FtKo+QGeP4I7FLvChpx4QXC8eNBF9epcMYm87z17EnaygXXDt++8/5zUIice34ZaMhuGvn1SLlUj7M/MptD/cRMm250+kNjtJ6GZLHSuqW806asxmwPlfwXavRM80Ma+pMo94V/UT60GPLws/H3iIIzfrH9puWhEdjjeo6lzzUrEhVaCkePs/Dbp6VLfxplCRkLDjnJwjpr8ubP8F6lKY033MTwSF9LrTzpdLHJ/eRKPDR6xQRFHPz1YHd6e27zsdraW4Y/M5sDCbX9gBoWP5AMlm+8uEy2oMogxr3bCkAJLunp7Tl176bdBgZGp+hQZjKem+4sv+L/kvabjt1clj1mGm7UBWwvpU/6xa2uX7eC0/HidnpthgrJIdkhJ4A2fxYWVsso1wC29uBKt0BFvAZs0In3EAVyMxdP2qiGnWafl+JpJZkv+/6aJnGKl4Tl2paeHOgMVVBWRHz+5gn3GwIoH+EQa4qQnMxqRmrbaywed7trS4LTVsbYdtmKQUOexYrPCc6ukNLinB4RCAxBH3iDMWx2Uk6Z4p4S5Pwf5dCFLLz0d/hdj42WcIfgMzyi1Nnyqr2ZmYuMLxr8G7gxGJGpe9zKwn/jalKx3C4c2AkE7prkse70A+IvntHV5OdqbaEqDUxLM+wkSzgAQRcCo+Uk0nIQ4pUGEVDlaWW2+2QTxvQTw8+lLtpTmuVhv5Afdk9D//o19LPtI8hRDSz9vlKgxnRwZKbHhNP4ysGLUG+vd0VXRLtDtOMvqUj7SOlXzy4OSniVYWOJo6VlOvXQ==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700016)(82310400026)(1800799024)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tR+a7cUsTqsfN5ONYdFhoWchu2GHPlEpIqSX8M8EZCF27MxhuJYPVM7lpdv2m32CgAY0NHbOjZQPtpneiXVPvtPORpD3gJe3nBl6SRB4hQrHSQHdVKcrZK2HBM8VOqJ5hRnR/d5MMxry4LQ9a36fFIQ9E0D1ShLNkMrB7jYfEA5P+NDFbQ+bK19jOL/9dX7FuphzKSbT9VwVdJD3B1TriVOvQRQHLRkSP1eTdyPuzyZd5Rf4l92iHGrFevWzQpBwbFQFFfnIF5OQNuSs0iTpSo3lrtJpfrqJ8s4T67ePm9HFY6mcuejcfzESV6afRl9rJ1okRM/gS2sR2cE5XIDuEB8teqi75f3Ink3VesGJ4Rd/AmHZyBlXM8kNOUAP6meg+D7agk8upkIuTDz9ijlib73/GP087NEVFIqoD/W/MaVMSsaoC3BrMptYmiuX8yadj", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Apr 2026 23:29:28.4851\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b9d50827-81c4-45b4-9464-08de9c10012a", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tSJ1PEPF00002315.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR12MB9217" }, "content": "To allow lockless iterations of the group->devices list in an ISR context\nthat cannot hold the group->mutex, change the list to be RCU protected.\n\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\n---\n drivers/iommu/iommu.c | 16 +++++++++-------\n 1 file changed, 9 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c\nindex 768ac728b4cc3..d1be62a07904a 100644\n--- a/drivers/iommu/iommu.c\n+++ b/drivers/iommu/iommu.c\n@@ -84,18 +84,20 @@ struct group_device {\n \t */\n \tbool blocked;\n \tunsigned int reset_depth;\n+\tstruct rcu_head rcu;\n };\n \n /* Iterate over each struct group_device in a struct iommu_group */\n #define for_each_group_device(group, pos) \\\n-\tlist_for_each_entry(pos, &(group)->devices, list)\n+\tlist_for_each_entry_rcu(pos, &(group)->devices, list, \\\n+\t\t\t\tlockdep_is_held(&(group)->mutex))\n \n static struct group_device *__dev_to_gdev(struct device *dev)\n {\n \tstruct iommu_group *group = dev->iommu_group;\n \tstruct group_device *gdev;\n \n-\tlockdep_assert_held(&group->mutex);\n+\tlockdep_assert(lockdep_is_held(&group->mutex) || rcu_read_lock_held());\n \n \tfor_each_group_device(group, gdev) {\n \t\tif (gdev->dev == dev)\n@@ -666,7 +668,7 @@ static int __iommu_probe_device(struct device *dev, struct list_head *group_list\n \t * The gdev must be in the list before calling\n \t * iommu_setup_default_domain()\n \t */\n-\tlist_add_tail(&gdev->list, &group->devices);\n+\tlist_add_tail_rcu(&gdev->list, &group->devices);\n \tWARN_ON(group->default_domain && !group->domain);\n \tif (group->default_domain)\n \t\tiommu_create_device_direct_mappings(group->default_domain, dev);\n@@ -697,7 +699,7 @@ static int __iommu_probe_device(struct device *dev, struct list_head *group_list\n \treturn 0;\n \n err_remove_gdev:\n-\tlist_del(&gdev->list);\n+\tlist_del_rcu(&gdev->list);\n \t__iommu_group_free_device(group, gdev);\n err_put_group:\n \tiommu_deinit_device(dev);\n@@ -745,7 +747,7 @@ static void __iommu_group_free_device(struct iommu_group *group,\n \t\t\tgroup->domain != group->default_domain);\n \n \tkfree(grp_dev->name);\n-\tkfree(grp_dev);\n+\tkfree_rcu(grp_dev, rcu);\n }\n \n /* Remove the iommu_group from the struct device. */\n@@ -759,7 +761,7 @@ static void __iommu_group_remove_device(struct device *dev)\n \t\tif (device->dev != dev)\n \t\t\tcontinue;\n \n-\t\tlist_del(&device->list);\n+\t\tlist_del_rcu(&device->list);\n \t\t__iommu_group_free_device(group, device);\n \t\tif (dev_has_iommu(dev))\n \t\t\tiommu_deinit_device(dev);\n@@ -1335,7 +1337,7 @@ int iommu_group_add_device(struct iommu_group *group, struct device *dev)\n \tdev->iommu_group = group;\n \n \tmutex_lock(&group->mutex);\n-\tlist_add_tail(&gdev->list, &group->devices);\n+\tlist_add_tail_rcu(&gdev->list, &group->devices);\n \tmutex_unlock(&group->mutex);\n \treturn 0;\n }\n", "prefixes": [ "v3", "05/11" ] }