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GET /api/patches/2224108/?format=api
{ "id": 2224108, "url": "http://patchwork.ozlabs.org/api/patches/2224108/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260416200513.27100-2-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260416200513.27100-2-philmd@linaro.org>", "list_archive_url": null, "date": "2026-04-16T20:05:12", "name": "[v5,1/2] target/mips: Pass MemOpIdx argument to Linked Load/Store helpers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c35eaf3cda85d15ec9f19d4931d68b379d711aae", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260416200513.27100-2-philmd@linaro.org/mbox/", "series": [ { "id": 500201, "url": "http://patchwork.ozlabs.org/api/series/500201/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500201", "date": "2026-04-16T20:05:11", "name": "target/mips: Use probe_access_full() in Atomic Load/Store helpers", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/500201/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224108/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224108/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=SUSsVD69;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32c;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "In preparation of using the MemOp content in the next commit\n(thus stopping ignoring it), pass it as MemOpIdx.\n\nThe helper prototype declaration always took a TCGv_i32 as\nlast argument, correct that.\n\nRename the ignored 'mem_idx' argument on user emulation.\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n target/mips/helper.h | 4 ++--\n target/mips/tcg/ldst_helper.c | 5 ++++-\n target/mips/tcg/translate.c | 7 ++++---\n 3 files changed, 10 insertions(+), 6 deletions(-)", "diff": "diff --git a/target/mips/helper.h b/target/mips/helper.h\nindex e70a3942fac..10c6470514d 100644\n--- a/target/mips/helper.h\n+++ b/target/mips/helper.h\n@@ -10,9 +10,9 @@ DEF_HELPER_4(swl, void, env, tl, tl, int)\n DEF_HELPER_4(swr, void, env, tl, tl, int)\n \n #ifndef CONFIG_USER_ONLY\n-DEF_HELPER_3(ll, tl, env, tl, int)\n+DEF_HELPER_3(ll, tl, env, tl, i32)\n #ifdef TARGET_MIPS64\n-DEF_HELPER_3(lld, tl, env, tl, int)\n+DEF_HELPER_3(lld, tl, env, tl, i32)\n #endif\n #endif\n \ndiff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c\nindex 10319bf03a6..b725c6d0333 100644\n--- a/target/mips/tcg/ldst_helper.c\n+++ b/target/mips/tcg/ldst_helper.c\n@@ -30,8 +30,11 @@\n #ifndef CONFIG_USER_ONLY\n \n #define HELPER_LD_ATOMIC(name, insn, almask, do_cast) \\\n-target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \\\n+target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, \\\n+ uint32_t memop_idx) \\\n { \\\n+ MemOpIdx oi = memop_idx; \\\n+ unsigned mem_idx = get_mmuidx(oi); \\\n if (arg & almask) { \\\n if (!(env->hflags & MIPS_HFLAG_DM)) { \\\n env->CP0_BadVAddr = arg; \\\ndiff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c\nindex 6d4b6412d70..839bfe18bab 100644\n--- a/target/mips/tcg/translate.c\n+++ b/target/mips/tcg/translate.c\n@@ -1922,7 +1922,7 @@ FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd))\n /* load/store instructions. */\n #ifdef CONFIG_USER_ONLY\n #define OP_LD_ATOMIC(insn, memop) \\\n-static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \\\n+static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx_ignored, \\\n DisasContext *ctx) \\\n { \\\n TCGv t0 = tcg_temp_new(); \\\n@@ -1932,11 +1932,12 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \\\n tcg_gen_st_tl(ret, tcg_env, offsetof(CPUMIPSState, llval)); \\\n }\n #else\n-#define OP_LD_ATOMIC(insn, ignored_memop) \\\n+#define OP_LD_ATOMIC(insn, memop) \\\n static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \\\n DisasContext *ctx) \\\n { \\\n- gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); \\\n+ MemOpIdx oi = make_memop_idx(memop, mem_idx); \\\n+ gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(oi)); \\\n }\n #endif\n OP_LD_ATOMIC(ll, mo_endian(ctx) | MO_SL);\n", "prefixes": [ "v5", "1/2" ] }