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GET /api/patches/2223927/?format=api
{ "id": 2223927, "url": "http://patchwork.ozlabs.org/api/patches/2223927/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260416115134.1032155-1-kkartik@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260416115134.1032155-1-kkartik@nvidia.com>", "list_archive_url": null, "date": "2026-04-16T11:51:34", "name": "[v3] soc/tegra: pmc: Add PMC support for Tegra410", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a08d50211d90a9683a6543adbc8c7532ca79ac20", "submitter": { "id": 83016, "url": "http://patchwork.ozlabs.org/api/people/83016/?format=api", "name": "Kartik Rajput", "email": "kkartik@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260416115134.1032155-1-kkartik@nvidia.com/mbox/", "series": [ { "id": 500140, "url": "http://patchwork.ozlabs.org/api/series/500140/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=500140", "date": "2026-04-16T11:51:34", "name": "[v3] soc/tegra: pmc: Add PMC support for Tegra410", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/500140/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223927/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223927/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13773-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=BddX2gzC;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.232.135.74; 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pr=C", "From": "Kartik Rajput <kkartik@nvidia.com>", "To": "Thierry Reding <thierry.reding@kernel.org>, Jonathan Hunter\n\t<jonathanh@nvidia.com>, Christophe Leroy <chleroy@kernel.org>, Jiri Slaby\n\t<jirislaby@kernel.org>, Prathamesh Shete <pshete@nvidia.com>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>", "CC": "Kartik Rajput <kkartik@nvidia.com>", "Subject": "[PATCH v3] soc/tegra: pmc: Add PMC support for Tegra410", "Date": "Thu, 16 Apr 2026 17:21:34 +0530", "Message-ID": "<20260416115134.1032155-1-kkartik@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SN1PEPF0002529E:EE_|IA0PR12MB8906:EE_", "X-MS-Office365-Filtering-Correlation-Id": "5c3df78c-b8cd-49fa-b8ca-08de9bae8d03", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|376014|36860700016|82310400026|56012099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n\t4py77gEerzsKqX2nE+vOBNuglVTit24BgYSePEWoHJaodwz7VshQ9FhwgIwVtxUFSDzB57lEgSXbAm5SSs6iuJAgE9YSGH2ZH2wPS5KJ5mthxdSPKomT5HQb9O7cNtgJST2RxaN8chPEww/j1sz1VpKPd6UxsKeiNONu9Fq0QXLLI8YG3URRMyGt/qU4ScnAclag7fG1i2CNih7xhw+Jxv4eLFKNqUaPpzHDhV6NxiuxkHqdNJAMowEKCyTy/hnkT2Uf2gELLIsUKUZYbJtypaE4tzrl/BL7wlHHN4SwdCZ13PCCHCTQoqI7IMNCEzZofPpY8BwM/9knSFdsUzyRIYg+ArMvzwckoUmIYXsWnQe+bMpFCgAuI/cLqALe+ybwlUribzgH2nsPjSd/ct40vLPxxd1GfTF9QB5fe9GxpyWBHI+cHISC044QxfnlIzumbqqrcPab+yATwbugLQTotVqhpOuMihOzmtMZ2toitD/JSukVef4dmvtN3ep+HlymAyHMxZJU1gp8Kb7xZp2Tdjn6BNHphkZYdnRNPDqjVomb23+ZyCCHy5/Zj7qgpX+CvLidb5piuBjgxzVZbQCRhkjVUJLtbGgNzJ4A1N2H62TbtNOoWr05mMsSDM3EYoo8PQUPvGCRMY5kYxPpCkhsI0NO5mOO8sc8qVI4i4HXL5p+z3pIY6lVRu8AfQ7XtjhnW4ubEXFH+XyEGed8FyloDzljDjc9xDbgjMTPe9r4ibfBQFafJ1nKD9uoipc3+5SaWUe69OHgDKPjK5ceHtmG5Q==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700016)(82310400026)(56012099003)(18002099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t0/llqmI2zlYaa5zuQUSIGhE2P08FOxlIC8jH1zJ+TtH+JizADOAnjeBw+RTANbg4ZIYW2YSjWpAXn9XDZcWb5rWiRmu7kEec1CTAGrb6O9vLRhexm24nFa82oT7W/7j8BCndMX7EIfiEzNaI+6OsQBEtOMYLEn1/gr799dhUxw+f8q5hTyE+ECARW7IsxHMrGWOs+KatY7VCt2LaLsetBG0iuMDzER0T1sspA/ZJiANJT0WiconUT2yXUK2Q03pc5mJuK3ufK7WmSEFOGiLpP/lfR8522Yd/YOOr5KsgYZruHKOoocPnIuLjXiFhw3KsE7RQVoL2THRp1t/an/4L6pp9tcCcFHnYUEUx21PxS0COtdCCgosbxpG8B8MgjDbxa6EuueEsJTh3qlVo+eAankPfPZpOljQPEbHc6qs3/27T9us16ySWMTDP8ePD0UiO", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Apr 2026 11:51:52.4238\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5c3df78c-b8cd-49fa-b8ca-08de9bae8d03", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tSN1PEPF0002529E.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA0PR12MB8906" }, "content": "Tegra410 uses PMC driver only to retrieve system reset reason using PMC\nsysfs. Tegra410 uses ACPI to probe PMC, unlike device-tree boot it does\nnot use the early initialisation sequence.\n\nAdd PMC support for Tegra410, which uses the PMC driver to retrieve\nthe system reset reason via PMC sysfs.\n\nSigned-off-by: Kartik Rajput <kkartik@nvidia.com>\n---\nChanges in v3:\n\t* Remove unused entries from tegra410_pmc_soc.\nChanges in v2:\n\t* Updated commit message.\n---\n drivers/soc/tegra/pmc.c | 101 ++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 101 insertions(+)", "diff": "diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c\nindex 2ee6539d796a..f89de1969946 100644\n--- a/drivers/soc/tegra/pmc.c\n+++ b/drivers/soc/tegra/pmc.c\n@@ -11,6 +11,7 @@\n \n #define pr_fmt(fmt) \"tegra-pmc: \" fmt\n \n+#include <linux/acpi.h>\n #include <linux/arm-smccc.h>\n #include <linux/clk.h>\n #include <linux/clk-provider.h>\n@@ -3117,12 +3118,30 @@ static void tegra_pmc_reset_suspend_mode(void *data)\n \tpmc->suspend_mode = TEGRA_SUSPEND_NOT_READY;\n }\n \n+static int tegra_pmc_acpi_probe(struct platform_device *pdev)\n+{\n+\tpmc->soc = device_get_match_data(&pdev->dev);\n+\tpmc->dev = &pdev->dev;\n+\n+\tpmc->base = devm_platform_ioremap_resource(pdev, 0);\n+\tif (IS_ERR(pmc->base))\n+\t\treturn PTR_ERR(pmc->base);\n+\n+\ttegra_pmc_reset_sysfs_init(pmc);\n+\tplatform_set_drvdata(pdev, pmc);\n+\n+\treturn 0;\n+}\n+\n static int tegra_pmc_probe(struct platform_device *pdev)\n {\n \tvoid __iomem *base;\n \tstruct resource *res;\n \tint err;\n \n+\tif (is_acpi_node(dev_fwnode(&pdev->dev)))\n+\t\treturn tegra_pmc_acpi_probe(pdev);\n+\n \t/*\n \t * Early initialisation should have configured an initial\n \t * register mapping and setup the soc data pointer. If these\n@@ -4783,6 +4802,81 @@ static const struct tegra_pmc_soc tegra264_pmc_soc = {\n \t.max_wake_vectors = 4,\n };\n \n+static const char * const tegra410_reset_sources[] = {\n+\t\"SYS_RESET_N\",\t\t/* 0x0 */\n+\t\"CSDC_RTC_XTAL\",\n+\t\"VREFRO_POWER_BAD\",\n+\t\"FMON_32K\",\n+\t\"FMON_OSC\",\n+\t\"POD_RTC\",\n+\t\"POD_IO\",\n+\t\"POD_PLUS_IO_SPLL\",\n+\t\"POD_PLUS_IO_VMON\",\t/* 0x8 */\n+\t\"POD_PLUS_SOC\",\n+\t\"VMON_PLUS_UV\",\n+\t\"VMON_PLUS_OV\",\n+\t\"FUSECRC_FAULT\",\n+\t\"OSC_FAULT\",\n+\t\"BPMP_BOOT_FAULT\",\n+\t\"SCPM_BPMP_CORE_CLK\",\n+\t\"SCPM_PSC_SE_CLK\",\t/* 0x10 */\n+\t\"VMON_SOC_MIN\",\n+\t\"VMON_SOC_MAX\",\n+\t\"NVJTAG_SEL_MONITOR\",\n+\t\"L0_RST_REQ_N\",\n+\t\"NV_THERM_FAULT\",\n+\t\"PSC_SW\",\n+\t\"POD_C2C_LPI_0\",\n+\t\"POD_C2C_LPI_1\",\t/* 0x18 */\n+\t\"BPMP_FMON\",\n+\t\"FMON_SPLL_OUT\",\n+\t\"L1_RST_REQ_N\",\n+\t\"OCP_RECOVERY\",\n+\t\"AO_WDT_POR\",\n+\t\"BPMP_WDT_POR\",\n+\t\"RAS_WDT_POR\",\n+\t\"TOP_0_WDT_POR\",\t/* 0x20 */\n+\t\"TOP_1_WDT_POR\",\n+\t\"TOP_2_WDT_POR\",\n+\t\"PSC_WDT_POR\",\n+\t\"OOBHUB_WDT_POR\",\n+\t\"MSS_SEQ_WDT_POR\",\n+\t\"SW_MAIN\",\n+\t\"L0L1_RST_OUT_N\",\n+\t\"HSM\",\t\t\t/* 0x28 */\n+\t\"CSITE_SW\",\n+\t\"AO_WDT_DBG\",\n+\t\"BPMP_WDT_DBG\",\n+\t\"RAS_WDT_DBG\",\n+\t\"TOP_0_WDT_DBG\",\n+\t\"TOP_1_WDT_DBG\",\n+\t\"TOP_2_WDT_DBG\",\n+\t\"PSC_WDT_DBG\",\t\t/* 0x30 */\n+\t\"TSC_0_WDT_DBG\",\n+\t\"TSC_1_WDT_DBG\",\n+\t\"OOBHUB_WDT_DBG\",\n+\t\"MSS_SEQ_WDT_DBG\",\n+\t\"L2_RST_REQ_N\",\n+\t\"L2_RST_OUT_N\",\n+\t\"SC7\"\n+};\n+\n+static const struct tegra_pmc_regs tegra410_pmc_regs = {\n+\t.rst_status = 0x8,\n+\t.rst_source_shift = 0x2,\n+\t.rst_source_mask = 0xfc,\n+\t.rst_level_shift = 0x0,\n+\t.rst_level_mask = 0x3,\n+};\n+\n+static const struct tegra_pmc_soc tegra410_pmc_soc = {\n+\t.regs = &tegra410_pmc_regs,\n+\t.reset_sources = tegra410_reset_sources,\n+\t.num_reset_sources = ARRAY_SIZE(tegra410_reset_sources),\n+\t.reset_levels = tegra186_reset_levels,\n+\t.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),\n+};\n+\n static const struct of_device_id tegra_pmc_match[] = {\n \t{ .compatible = \"nvidia,tegra264-pmc\", .data = &tegra264_pmc_soc },\n \t{ .compatible = \"nvidia,tegra234-pmc\", .data = &tegra234_pmc_soc },\n@@ -4797,6 +4891,12 @@ static const struct of_device_id tegra_pmc_match[] = {\n \t{ }\n };\n \n+static const struct acpi_device_id tegra_pmc_acpi_match[] = {\n+\t{ .id = \"NVDA2016\", .driver_data = (kernel_ulong_t)&tegra410_pmc_soc },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(acpi, tegra_pmc_acpi_match);\n+\n static void tegra_pmc_sync_state(struct device *dev)\n {\n \tstruct device_node *np, *child;\n@@ -4847,6 +4947,7 @@ static struct platform_driver tegra_pmc_driver = {\n \t\t.name = \"tegra-pmc\",\n \t\t.suppress_bind_attrs = true,\n \t\t.of_match_table = tegra_pmc_match,\n+\t\t.acpi_match_table = tegra_pmc_acpi_match,\n #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)\n \t\t.pm = &tegra_pmc_pm_ops,\n #endif\n", "prefixes": [ "v3" ] }