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GET /api/patches/2223917/?format=api
{ "id": 2223917, "url": "http://patchwork.ozlabs.org/api/patches/2223917/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/8e274a7a10a5aae23eb1250db0b4f4250c81f3ef.1776339451.git.matheus.bernardino@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<8e274a7a10a5aae23eb1250db0b4f4250c81f3ef.1776339451.git.matheus.bernardino@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-16T11:38:56", "name": "[v5,07/16] target/hexagon: add v68 HVX IEEE float min/max insns", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "eedb8320fc1770a74e8be8ded24d77926fa00c8d", "submitter": { "id": 90606, "url": "http://patchwork.ozlabs.org/api/people/90606/?format=api", "name": "Matheus Tavares Bernardino", "email": "matheus.bernardino@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/8e274a7a10a5aae23eb1250db0b4f4250c81f3ef.1776339451.git.matheus.bernardino@oss.qualcomm.com/mbox/", "series": [ { "id": 500137, "url": "http://patchwork.ozlabs.org/api/series/500137/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500137", "date": "2026-04-16T11:38:50", "name": "hexagon: add missing HVX float instructions", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/500137/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223917/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223917/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", 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"Cc": "richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com", "Subject": "[PATCH v5 07/16] target/hexagon: add v68 HVX IEEE float min/max insns", "Date": "Thu, 16 Apr 2026 04:38:56 -0700", "Message-Id": "\n <8e274a7a10a5aae23eb1250db0b4f4250c81f3ef.1776339451.git.matheus.bernardino@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.37.2", "In-Reply-To": "<cover.1776339451.git.matheus.bernardino@oss.qualcomm.com>", "References": "<cover.1776339451.git.matheus.bernardino@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-GUID": "8_cMysrQjUqyawERF-nTdw4oLMveHO1k", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDE2MDExMCBTYWx0ZWRfX8dmjNcC0u+Js\n 3PQUBpDqMxAbY73XHQj27DXXhcnPNZHidLUnGymEHFgOfmMpVpZVa6oFfgkksk/8MwMWR8sMksh\n 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definitions=2026-04-16_03,2026-04-13_04,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n impostorscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015\n priorityscore=1501 phishscore=0 bulkscore=0 adultscore=0 spamscore=0\n malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000\n definitions=main-2604160110", "Received-SPF": "pass client-ip=205.220.168.131;\n envelope-from=matheus.bernardino@oss.qualcomm.com;\n helo=mx0a-0031df01.pphosted.com", "X-Spam_score_int": "-27", "X-Spam_score": "-2.8", "X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add HVX IEEE floating-point min/max instructions:\n- vfmin_hf, vfmin_sf: IEEE floating-point minimum\n- vfmax_hf, vfmax_sf: IEEE floating-point maximum\n- vmax_hf, vmax_sf: qfloat IEEE maximum\n- vmin_hf, vmin_sf: qfloat IEEE minimum\n\nThe Hexagon qfloat variants are similar to the IEEE-754 ones, but they\nhandle NaN slightly differently. See comment on hvx_ieee_fp.h\n\nReviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>\nSigned-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>\n---\n target/hexagon/mmvec/hvx_ieee_fp.h | 6 +++\n target/hexagon/attribs_def.h.inc | 2 +\n target/hexagon/mmvec/hvx_ieee_fp.c | 50 ++++++++++++++++++++\n target/hexagon/hex_common.py | 1 +\n target/hexagon/imported/mmvec/encode_ext.def | 10 ++++\n target/hexagon/imported/mmvec/ext.idef | 36 +++++++++++++-\n 6 files changed, 104 insertions(+), 1 deletion(-)", "diff": "diff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_ieee_fp.h\nindex 75008deb3b..dff2fab14c 100644\n--- a/target/hexagon/mmvec/hvx_ieee_fp.h\n+++ b/target/hexagon/mmvec/hvx_ieee_fp.h\n@@ -15,4 +15,10 @@ float32 fp_mult_sf_hf(float16 a1, float16 a2, float_status *fp_status);\n float32 fp_vdmpy(float16 a1, float16 a2, float16 a3, float16 a4,\n float_status *fp_status);\n \n+/* Qfloat min/max treat +NaN as greater than +INF and -NaN as smaller than -INF */\n+float32 qf_max_sf(float32 a1, float32 a2, float_status *fp_status);\n+float32 qf_min_sf(float32 a1, float32 a2, float_status *fp_status);\n+float16 qf_max_hf(float16 a1, float16 a2, float_status *fp_status);\n+float16 qf_min_hf(float16 a1, float16 a2, float_status *fp_status);\n+\n #endif\ndiff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc\nindex d3c4bf6301..2d0fc7e9c0 100644\n--- a/target/hexagon/attribs_def.h.inc\n+++ b/target/hexagon/attribs_def.h.inc\n@@ -81,6 +81,7 @@ DEF_ATTRIB(CVI_SCATTER, \"CVI Scatter operation\", \"\", \"\")\n DEF_ATTRIB(CVI_SCATTER_RELEASE, \"CVI Store Release for scatter\", \"\", \"\")\n DEF_ATTRIB(CVI_TMP_DST, \"CVI instruction that doesn't write a register\", \"\", \"\")\n DEF_ATTRIB(CVI_SLOT23, \"Can execute in slot 2 or slot 3 (HVX)\", \"\", \"\")\n+DEF_ATTRIB(CVI_VA_2SRC, \"Execs on multimedia vector engine; requires two srcs\", \"\", \"\")\n \n DEF_ATTRIB(VTCM_ALLBANK_ACCESS, \"Allocates in all VTCM schedulers.\", \"\", \"\")\n \n@@ -179,6 +180,7 @@ DEF_ATTRIB(HVX_IEEE_FP_ACC, \"HVX IEEE FP accumulate instruction\", \"\", \"\")\n DEF_ATTRIB(HVX_IEEE_FP_OUT_16, \"HVX IEEE FP 16-bit output\", \"\", \"\")\n DEF_ATTRIB(HVX_IEEE_FP_OUT_32, \"HVX IEEE FP 32-bit output\", \"\", \"\")\n DEF_ATTRIB(CVI_VX_NO_TMP_LD, \"HVX multiply without tmp load\", \"\", \"\")\n+DEF_ATTRIB(HVX_FLT, \"This a floating point HVX instruction.\", \"\", \"\")\n \n /* Keep this as the last attribute: */\n DEF_ATTRIB(ZZ_LASTATTRIB, \"Last attribute in the file\", \"\", \"\")\ndiff --git a/target/hexagon/mmvec/hvx_ieee_fp.c b/target/hexagon/mmvec/hvx_ieee_fp.c\nindex 3367226998..2ae79a485a 100644\n--- a/target/hexagon/mmvec/hvx_ieee_fp.c\n+++ b/target/hexagon/mmvec/hvx_ieee_fp.c\n@@ -19,3 +19,53 @@ float32 fp_vdmpy(float16 a1, float16 a2, float16 a3, float16 a4,\n return float32_add(fp_mult_sf_hf(a1, a3, fp_status),\n fp_mult_sf_hf(a2, a4, fp_status), fp_status);\n }\n+\n+#define float32_is_pos_nan(X) (float32_is_any_nan(X) && !float32_is_neg(X))\n+#define float32_is_neg_nan(X) (float32_is_any_nan(X) && float32_is_neg(X))\n+#define float16_is_pos_nan(X) (float16_is_any_nan(X) && !float16_is_neg(X))\n+#define float16_is_neg_nan(X) (float16_is_any_nan(X) && float16_is_neg(X))\n+\n+/* Qfloat min/max treat +NaN as greater than +INF and -NaN as smaller than -INF */\n+float32 qf_max_sf(float32 a1, float32 a2, float_status *fp_status)\n+{\n+ if (float32_is_pos_nan(a1) || float32_is_neg_nan(a2)) {\n+ return a1;\n+ }\n+ if (float32_is_pos_nan(a2) || float32_is_neg_nan(a1)) {\n+ return a2;\n+ }\n+ return float32_max(a1, a2, fp_status);\n+}\n+\n+float32 qf_min_sf(float32 a1, float32 a2, float_status *fp_status)\n+{\n+ if (float32_is_pos_nan(a1) || float32_is_neg_nan(a2)) {\n+ return a2;\n+ }\n+ if (float32_is_pos_nan(a2) || float32_is_neg_nan(a1)) {\n+ return a1;\n+ }\n+ return float32_min(a1, a2, fp_status);\n+}\n+\n+float16 qf_max_hf(float16 a1, float16 a2, float_status *fp_status)\n+{\n+ if (float16_is_pos_nan(a1) || float16_is_neg_nan(a2)) {\n+ return a1;\n+ }\n+ if (float16_is_pos_nan(a2) || float16_is_neg_nan(a1)) {\n+ return a2;\n+ }\n+ return float16_max(a1, a2, fp_status);\n+}\n+\n+float16 qf_min_hf(float16 a1, float16 a2, float_status *fp_status)\n+{\n+ if (float16_is_pos_nan(a1) || float16_is_neg_nan(a2)) {\n+ return a2;\n+ }\n+ if (float16_is_pos_nan(a2) || float16_is_neg_nan(a1)) {\n+ return a1;\n+ }\n+ return float16_min(a1, a2, fp_status);\n+}\ndiff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py\nindex 9819201b50..168112c66f 100755\n--- a/target/hexagon/hex_common.py\n+++ b/target/hexagon/hex_common.py\n@@ -216,6 +216,7 @@ def need_env(tag):\n \"A_CVI_GATHER\" in attribdict[tag] or\n \"A_CVI_SCATTER\" in attribdict[tag] or\n \"A_HVX_IEEE_FP\" in attribdict[tag] or\n+ \"A_HVX_FLT\" in attribdict[tag] or\n \"A_IMPLICIT_WRITES_USR\" in attribdict[tag])\n \n \ndiff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/imported/mmvec/encode_ext.def\nindex 4ce87d09fd..d7f50db778 100644\n--- a/target/hexagon/imported/mmvec/encode_ext.def\n+++ b/target/hexagon/imported/mmvec/encode_ext.def\n@@ -823,4 +823,14 @@ DEF_ENC(V6_vsub_sf_hf,\"00011111100vvvvvPP1uuuuu101ddddd\")\n DEF_ENC(V6_vadd_hf_hf,\"00011111101vvvvvPP1uuuuu111ddddd\")\n DEF_ENC(V6_vsub_hf_hf,\"00011111011vvvvvPP1uuuuu000ddddd\")\n \n+/* IEEE FP min/max instructions */\n+DEF_ENC(V6_vfmin_hf,\"00011100011vvvvvPP1uuuuu000ddddd\")\n+DEF_ENC(V6_vfmin_sf,\"00011100011vvvvvPP1uuuuu001ddddd\")\n+DEF_ENC(V6_vfmax_hf,\"00011100011vvvvvPP1uuuuu010ddddd\")\n+DEF_ENC(V6_vfmax_sf,\"00011100011vvvvvPP1uuuuu011ddddd\")\n+DEF_ENC(V6_vmax_sf,\"00011111110vvvvvPP1uuuuu001ddddd\")\n+DEF_ENC(V6_vmin_sf,\"00011111110vvvvvPP1uuuuu010ddddd\")\n+DEF_ENC(V6_vmax_hf,\"00011111110vvvvvPP1uuuuu011ddddd\")\n+DEF_ENC(V6_vmin_hf,\"00011111110vvvvvPP1uuuuu100ddddd\")\n+\n #endif /* NO MMVEC */\ndiff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/imported/mmvec/ext.idef\nindex 14df8e4790..0e9cace203 100644\n--- a/target/hexagon/imported/mmvec/ext.idef\n+++ b/target/hexagon/imported/mmvec/ext.idef\n@@ -43,7 +43,9 @@\n EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA), \\\n DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n \n-\n+#define ITERATOR_INSN_ANY_SLOT_2SRC(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \\\n+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n \n #define ITERATOR_INSN2_ANY_SLOT(WIDTH,TAG,SYNTAX,SYNTAX2,DESCR,CODE) \\\n ITERATOR_INSN_ANY_SLOT(WIDTH,TAG,SYNTAX2,DESCR,CODE)\n@@ -3000,6 +3002,38 @@ ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vsub_sf_hf,\n VddV.v[1].sf[i] = float32_sub(f16_to_f32(VuV.hf[2*i+1]),\n f16_to_f32(VvV.hf[2*i+1]), &env->hvx_fp_status))\n \n+#define ITERATOR_INSN_IEEE_FP_16_32_LATE(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_16,A_HVX_IEEE_FP_OUT_32), \\\n+ DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n+\n+/* IEEE FP min/max instructions */\n+ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vfmin_hf, \"Vd32.hf=vfmin(Vu32.hf,Vv32.hf)\", \\\n+ \"Vector IEEE min: hf\", VdV.hf[i] = float16_min(VuV.hf[i], VvV.hf[i], \\\n+\t&env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vfmin_sf, \"Vd32.sf=vfmin(Vu32.sf,Vv32.sf)\", \\\n+ \"Vector IEEE min: sf\", VdV.sf[i] = float32_min(VuV.sf[i], VvV.sf[i], \\\n+\t&env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vfmax_hf, \"Vd32.hf=vfmax(Vu32.hf,Vv32.hf)\", \\\n+ \"Vector IEEE max: hf\", VdV.hf[i] = float16_max(VuV.hf[i], VvV.hf[i], \\\n+\t&env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vfmax_sf, \"Vd32.sf=vfmax(Vu32.sf,Vv32.sf)\", \\\n+ \"Vector IEEE max: sf\", VdV.sf[i] = float32_max(VuV.sf[i], VvV.sf[i], \\\n+\t&env->hvx_fp_status))\n+\n+ITERATOR_INSN_ANY_SLOT_2SRC(32,vmax_sf,\"Vd32.sf=vmax(Vu32.sf,Vv32.sf)\", \\\n+ \"Vector max of sf input\", VdV.sf[i] = qf_max_sf(VuV.sf[i], VvV.sf[i], \\\n+\t&env->hvx_fp_status))\n+ITERATOR_INSN_ANY_SLOT_2SRC(32,vmin_sf,\"Vd32.sf=vmin(Vu32.sf,Vv32.sf)\", \\\n+ \"Vector min of sf input\", VdV.sf[i] = qf_min_sf(VuV.sf[i], VvV.sf[i], \\\n+\t&env->hvx_fp_status))\n+ITERATOR_INSN_ANY_SLOT_2SRC(16,vmax_hf,\"Vd32.hf=vmax(Vu32.hf,Vv32.hf)\", \\\n+ \"Vector max of hf input\", VdV.hf[i] = qf_max_hf(VuV.hf[i], VvV.hf[i], \\\n+\t&env->hvx_fp_status))\n+ITERATOR_INSN_ANY_SLOT_2SRC(16,vmin_hf,\"Vd32.hf=vmin(Vu32.hf,Vv32.hf)\", \\\n+ \"Vector min of hf input\", VdV.hf[i] = qf_min_hf(VuV.hf[i], VvV.hf[i], \\\n+\t&env->hvx_fp_status))\n+\n /******************************************************************************\n DEBUG Vector/Register Printing\n ******************************************************************************/\n", "prefixes": [ "v5", "07/16" ] }