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GET /api/patches/2223915/?format=api
{ "id": 2223915, "url": "http://patchwork.ozlabs.org/api/patches/2223915/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1fe4b8a0fcae6705a591b1b5131e28f6d8062eed.1776339451.git.matheus.bernardino@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1fe4b8a0fcae6705a591b1b5131e28f6d8062eed.1776339451.git.matheus.bernardino@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-16T11:38:51", "name": "[v5,02/16] target/hexagon: fix incorrect/too-permissive HVX encodings", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "97569ab9c624c31f26962cdf193fd72b5d956685", "submitter": { "id": 90606, "url": "http://patchwork.ozlabs.org/api/people/90606/?format=api", "name": "Matheus Tavares Bernardino", "email": "matheus.bernardino@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1fe4b8a0fcae6705a591b1b5131e28f6d8062eed.1776339451.git.matheus.bernardino@oss.qualcomm.com/mbox/", "series": [ { "id": 500137, "url": "http://patchwork.ozlabs.org/api/series/500137/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500137", "date": "2026-04-16T11:38:50", "name": "hexagon: add missing HVX float instructions", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/500137/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223915/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223915/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", 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"qemu-devel@nongnu.org", "Cc": "richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com", "Subject": "[PATCH v5 02/16] target/hexagon: fix incorrect/too-permissive HVX\n encodings", "Date": "Thu, 16 Apr 2026 04:38:51 -0700", "Message-Id": "\n <1fe4b8a0fcae6705a591b1b5131e28f6d8062eed.1776339451.git.matheus.bernardino@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.37.2", "In-Reply-To": "<cover.1776339451.git.matheus.bernardino@oss.qualcomm.com>", "References": "<cover.1776339451.git.matheus.bernardino@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-ORIG-GUID": "iUxAs-26Vxmz30I6rDlQ9G6bAjVN4sd2", "X-Proofpoint-GUID": "iUxAs-26Vxmz30I6rDlQ9G6bAjVN4sd2", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDE2MDExMCBTYWx0ZWRfX1jDNb12wB7eX\n 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definitions=2026-04-16_03,2026-04-13_04,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 bulkscore=0 adultscore=0 spamscore=0 phishscore=0\n impostorscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0\n clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000\n definitions=main-2604160110", "Received-SPF": "pass client-ip=205.220.168.131;\n envelope-from=matheus.bernardino@oss.qualcomm.com;\n helo=mx0a-0031df01.pphosted.com", "X-Spam_score_int": "-27", "X-Spam_score": "-2.8", "X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The following encodings have become stricter since v68:\n\n - V6_vunpackob, V6_vunpackoh: ---00 -> --000\n - V6_vaddbq/hq/wq, V6_vaddbnq/hnq/wnq: ---01 -> --001\n - V6_vsubbq/hq, V6_vsubwq/bnq/hnq/wnq: ---01/---10 -> --001/--010\n - V6_vhist, V6_vwhist128/256, V6_vwhist128/256_sat: ---00 -> --000\n - V6_vhistq, V6_vwhist128/256q, V6_vwhist128/256q_sat: ---10 -> --010\n\nPre v68 compilers, by default, already use \"0\" for the non-specified bit\nthat changed in v68, so unless someone is manually writing the binary\nencoding, this should not cause any backwards incompatibility with\npre-v68 binaries.\n\nReviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>\nSigned-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>\n---\n target/hexagon/imported/mmvec/encode_ext.def | 48 ++++++++++----------\n 1 file changed, 24 insertions(+), 24 deletions(-)", "diff": "diff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/imported/mmvec/encode_ext.def\nindex 402438f566..6d70086b5f 100644\n--- a/target/hexagon/imported/mmvec/encode_ext.def\n+++ b/target/hexagon/imported/mmvec/encode_ext.def\n@@ -647,36 +647,36 @@ DEF_ENC(V6_vsubububb_sat, ICLASS_CJ\" 1 110 101 vvvvv PP 0 uuuuu 101 ddddd\")\n DEF_ENC(V6_vmpyewuh_64, ICLASS_CJ\" 1 110 101 vvvvv PP 0 uuuuu 110 ddddd\")\n \n DEF_FIELDROW_DESC32( ICLASS_CJ\" 1 110 --0 ----- PP 1 ----- ----- ---\",\"Vx32=Vu32\")\n-DEF_ENC(V6_vunpackob, ICLASS_CJ\" 1 110 --0 ---00 PP 1 uuuuu 000 xxxxx\") //\n-DEF_ENC(V6_vunpackoh, ICLASS_CJ\" 1 110 --0 ---00 PP 1 uuuuu 001 xxxxx\") //\n+DEF_ENC(V6_vunpackob, ICLASS_CJ\" 1 110 --0 --000 PP 1 uuuuu 000 xxxxx\") //\n+DEF_ENC(V6_vunpackoh, ICLASS_CJ\" 1 110 --0 --000 PP 1 uuuuu 001 xxxxx\") //\n //DEF_ENC(V6_vunpackow, ICLASS_CJ\" 1 110 --0 ---00 PP 1 uuuuu 010 xxxxx\") //\n \n-DEF_ENC(V6_vhist, ICLASS_CJ\" 1 110 --0 ---00 PP 1 -000- 100 -----\")\n-DEF_ENC(V6_vwhist256, ICLASS_CJ\" 1 110 --0 ---00 PP 1 -0010 100 -----\")\n-DEF_ENC(V6_vwhist256_sat, ICLASS_CJ\" 1 110 --0 ---00 PP 1 -0011 100 -----\")\n-DEF_ENC(V6_vwhist128, ICLASS_CJ\" 1 110 --0 ---00 PP 1 -010- 100 -----\")\n-DEF_ENC(V6_vwhist128m, ICLASS_CJ\" 1 110 --0 ---00 PP 1 -011i 100 -----\")\n+DEF_ENC(V6_vhist, ICLASS_CJ\" 1 110 --0 --000 PP 1 -000- 100 -----\")\n+DEF_ENC(V6_vwhist256, ICLASS_CJ\" 1 110 --0 --000 PP 1 -0010 100 -----\")\n+DEF_ENC(V6_vwhist256_sat, ICLASS_CJ\" 1 110 --0 --000 PP 1 -0011 100 -----\")\n+DEF_ENC(V6_vwhist128, ICLASS_CJ\" 1 110 --0 --000 PP 1 -010- 100 -----\")\n+DEF_ENC(V6_vwhist128m, ICLASS_CJ\" 1 110 --0 --000 PP 1 -011i 100 -----\")\n \n DEF_FIELDROW_DESC32( ICLASS_CJ\" 1 110 --0 ----- PP 1 ----- ----- ---\",\"if (Qv4) Vx32=Vu32\")\n-DEF_ENC(V6_vaddbq, ICLASS_CJ\" 1 110 vv0 ---01 PP 1 uuuuu 000 xxxxx\") //\n-DEF_ENC(V6_vaddhq, ICLASS_CJ\" 1 110 vv0 ---01 PP 1 uuuuu 001 xxxxx\") //\n-DEF_ENC(V6_vaddwq, ICLASS_CJ\" 1 110 vv0 ---01 PP 1 uuuuu 010 xxxxx\") //\n-DEF_ENC(V6_vaddbnq, ICLASS_CJ\" 1 110 vv0 ---01 PP 1 uuuuu 011 xxxxx\") //\n-DEF_ENC(V6_vaddhnq, ICLASS_CJ\" 1 110 vv0 ---01 PP 1 uuuuu 100 xxxxx\") //\n-DEF_ENC(V6_vaddwnq, ICLASS_CJ\" 1 110 vv0 ---01 PP 1 uuuuu 101 xxxxx\") //\n-DEF_ENC(V6_vsubbq, ICLASS_CJ\" 1 110 vv0 ---01 PP 1 uuuuu 110 xxxxx\") //\n-DEF_ENC(V6_vsubhq, ICLASS_CJ\" 1 110 vv0 ---01 PP 1 uuuuu 111 xxxxx\") //\n+DEF_ENC(V6_vaddbq, ICLASS_CJ\" 1 110 vv0 --001 PP 1 uuuuu 000 xxxxx\") //\n+DEF_ENC(V6_vaddhq, ICLASS_CJ\" 1 110 vv0 --001 PP 1 uuuuu 001 xxxxx\") //\n+DEF_ENC(V6_vaddwq, ICLASS_CJ\" 1 110 vv0 --001 PP 1 uuuuu 010 xxxxx\") //\n+DEF_ENC(V6_vaddbnq, ICLASS_CJ\" 1 110 vv0 --001 PP 1 uuuuu 011 xxxxx\") //\n+DEF_ENC(V6_vaddhnq, ICLASS_CJ\" 1 110 vv0 --001 PP 1 uuuuu 100 xxxxx\") //\n+DEF_ENC(V6_vaddwnq, ICLASS_CJ\" 1 110 vv0 --001 PP 1 uuuuu 101 xxxxx\") //\n+DEF_ENC(V6_vsubbq, ICLASS_CJ\" 1 110 vv0 --001 PP 1 uuuuu 110 xxxxx\") //\n+DEF_ENC(V6_vsubhq, ICLASS_CJ\" 1 110 vv0 --001 PP 1 uuuuu 111 xxxxx\") //\n \n-DEF_ENC(V6_vsubwq, ICLASS_CJ\" 1 110 vv0 ---10 PP 1 uuuuu 000 xxxxx\") //\n-DEF_ENC(V6_vsubbnq, ICLASS_CJ\" 1 110 vv0 ---10 PP 1 uuuuu 001 xxxxx\") //\n-DEF_ENC(V6_vsubhnq, ICLASS_CJ\" 1 110 vv0 ---10 PP 1 uuuuu 010 xxxxx\") //\n-DEF_ENC(V6_vsubwnq, ICLASS_CJ\" 1 110 vv0 ---10 PP 1 uuuuu 011 xxxxx\") //\n+DEF_ENC(V6_vsubwq, ICLASS_CJ\" 1 110 vv0 --010 PP 1 uuuuu 000 xxxxx\") //\n+DEF_ENC(V6_vsubbnq, ICLASS_CJ\" 1 110 vv0 --010 PP 1 uuuuu 001 xxxxx\") //\n+DEF_ENC(V6_vsubhnq, ICLASS_CJ\" 1 110 vv0 --010 PP 1 uuuuu 010 xxxxx\") //\n+DEF_ENC(V6_vsubwnq, ICLASS_CJ\" 1 110 vv0 --010 PP 1 uuuuu 011 xxxxx\") //\n \n-DEF_ENC(V6_vhistq, ICLASS_CJ\" 1 110 vv0 ---10 PP 1 --00- 100 -----\")\n-DEF_ENC(V6_vwhist256q, ICLASS_CJ\" 1 110 vv0 ---10 PP 1 --010 100 -----\")\n-DEF_ENC(V6_vwhist256q_sat, ICLASS_CJ\" 1 110 vv0 ---10 PP 1 --011 100 -----\")\n-DEF_ENC(V6_vwhist128q, ICLASS_CJ\" 1 110 vv0 ---10 PP 1 --10- 100 -----\")\n-DEF_ENC(V6_vwhist128qm, ICLASS_CJ\" 1 110 vv0 ---10 PP 1 --11i 100 -----\")\n+DEF_ENC(V6_vhistq, ICLASS_CJ\" 1 110 vv0 --010 PP 1 --00- 100 -----\")\n+DEF_ENC(V6_vwhist256q, ICLASS_CJ\" 1 110 vv0 --010 PP 1 --010 100 -----\")\n+DEF_ENC(V6_vwhist256q_sat, ICLASS_CJ\" 1 110 vv0 --010 PP 1 --011 100 -----\")\n+DEF_ENC(V6_vwhist128q, ICLASS_CJ\" 1 110 vv0 --010 PP 1 --10- 100 -----\")\n+DEF_ENC(V6_vwhist128qm, ICLASS_CJ\" 1 110 vv0 --010 PP 1 --11i 100 -----\")\n \n \n DEF_ENC(V6_vandvqv, ICLASS_CJ\" 1 110 vv0 ---11 PP 1 uuuuu 000 ddddd\")\n", "prefixes": [ "v5", "02/16" ] }