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{
    "id": 2223577,
    "url": "http://patchwork.ozlabs.org/api/patches/2223577/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260415-topic-am33-evm-oftree-v2026-01-v6-14-94cde349bb01@baylibre.com/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260415-topic-am33-evm-oftree-v2026-01-v6-14-94cde349bb01@baylibre.com>",
    "list_archive_url": null,
    "date": "2026-04-15T16:02:35",
    "name": "[v6,14/14] arm: dts: am335x: Remove unused uboot devicetrees",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "d5e49c6623c9042133ca88a23beb60735f863de1",
    "submitter": {
        "id": 82333,
        "url": "http://patchwork.ozlabs.org/api/people/82333/?format=api",
        "name": "Markus Schneider-Pargmann",
        "email": "msp@baylibre.com"
    },
    "delegate": {
        "id": 3651,
        "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api",
        "username": "trini",
        "first_name": "Tom",
        "last_name": "Rini",
        "email": "trini@ti.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260415-topic-am33-evm-oftree-v2026-01-v6-14-94cde349bb01@baylibre.com/mbox/",
    "series": [
        {
            "id": 500011,
            "url": "http://patchwork.ozlabs.org/api/series/500011/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=500011",
            "date": "2026-04-15T16:02:21",
            "name": "arm: am335x: Switch to upstream devicetree",
            "version": 6,
            "mbox": "http://patchwork.ozlabs.org/series/500011/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2223577/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2223577/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "\"Markus Schneider-Pargmann (TI)\" <msp@baylibre.com>",
        "Date": "Wed, 15 Apr 2026 18:02:35 +0200",
        "Subject": "[PATCH v6 14/14] arm: dts: am335x: Remove unused uboot devicetrees",
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        "Message-Id": "\n <20260415-topic-am33-evm-oftree-v2026-01-v6-14-94cde349bb01@baylibre.com>",
        "References": "\n <20260415-topic-am33-evm-oftree-v2026-01-v6-0-94cde349bb01@baylibre.com>",
        "In-Reply-To": "\n <20260415-topic-am33-evm-oftree-v2026-01-v6-0-94cde349bb01@baylibre.com>",
        "To": "u-boot@lists.denx.de, Marc Murphy <marc.murphy@sancloud.com>",
        "Cc": "Tom Rini <trini@konsulko.com>, Rasmus Villemoes <ravi@prevas.dk>,\n  Kory Maincent <kory.maincent@bootlin.com>,\n  Marek Vasut <marek.vasut+renesas@mailbox.org>,\n  Romain Gantois <romain.gantois@bootlin.com>,\n  Parvathi Pudi <parvathi@couthit.com>,\n  Basharath Hussain Khaja <basharath@couthit.com>,\n  Paul Barker <paul.barker@sancloud.com>, \"Andrew F. Davis\" <afd@ti.com>,\n  Simon Glass <sjg@chromium.org>, Anshul Dalal <anshuld@ti.com>,\n  Michael Trimarchi <michael@amarulasolutions.com>,\n  Patrick Delaunay <patrick.delaunay@foss.st.com>,\n  Patrice Chotard <patrice.chotard@foss.st.com>,\n  Svyatoslav Ryhel <clamor95@gmail.com>,\n  Tien Fong Chee <tien.fong.chee@altera.com>,\n  Frieder Schrempf <frieder.schrempf@kontron.de>,\n  Johan Jonker <jbx6244@gmail.com>, Brian Sune <briansune@gmail.com>,\n  Hai Pham <hai.pham.ud@renesas.com>,\n  Bernhard Messerklinger <bernhard.messerklinger@at.abb.com>,\n  Emanuele Ghidoli <emanuele.ghidoli@toradex.com>,\n  Parth Pancholi <parth.pancholi@toradex.com>,\n =?utf-8?q?Jonas_Schw=C3=B6bel?= <jonasschwoebel@yahoo.de>,\n  Paul Kocialkowski <contact@paulk.fr>,\n  \"Markus Schneider-Pargmann (TI)\" <msp@baylibre.com>",
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    },
    "content": "These devicetrees are not used anymore because the boards are using\nupstream devicetrees now.\n\nSigned-off-by: Markus Schneider-Pargmann (TI) <msp@baylibre.com>\n---\n arch/arm/dts/Makefile                              |  11 -\n arch/arm/dts/am335x-bone.dts                       |  23 -\n arch/arm/dts/am335x-boneblack.dts                  | 174 -----\n arch/arm/dts/am335x-bonegreen-eco.dts              |  53 --\n arch/arm/dts/am335x-bonegreen.dts                  |  14 -\n arch/arm/dts/am335x-evm.dts                        | 767 ---------------------\n arch/arm/dts/am335x-evmsk.dts                      | 730 --------------------\n arch/arm/dts/am335x-icev2.dts                      | 486 -------------\n arch/arm/dts/am335x-pocketbeagle.dts               | 237 -------\n arch/arm/dts/am335x-sancloud-bbe-common.dtsi       |  67 --\n arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts | 113 ---\n arch/arm/dts/am335x-sancloud-bbe-lite.dts          |  50 --\n arch/arm/dts/am335x-sancloud-bbe.dts               |  53 --\n 13 files changed, 2778 deletions(-)",
    "diff": "diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex d90e02ca4e5c73534ce4c5f41173c897780bc6fe..35145d7e01176e320ebbf5e4004a46540f8933f1 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -403,26 +403,15 @@ dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \\\n \tzynqmp-r5.dtb\n dtb-$(CONFIG_AM33XX) += \\\n \tam335x-baltos.dtb \\\n-\tam335x-bone.dtb \\\n-\tam335x-boneblack.dtb \\\n \tam335x-boneblack-wireless.dtb \\\n \tam335x-boneblue.dtb \\\n \tam335x-brppt1-mmc.dtb \\\n \tam335x-brxre1.dtb \\\n \tam335x-brsmarc1.dtb \\\n \tam335x-draco.dtb \\\n-\tam335x-evm.dtb \\\n-\tam335x-evmsk.dtb \\\n-\tam335x-bonegreen.dtb \\\n-\tam335x-bonegreen-eco.dtb \\\n \tam335x-bonegreen-wireless.dtb \\\n-\tam335x-icev2.dtb \\\n-\tam335x-pocketbeagle.dtb \\\n \tam335x-pxm50.dtb \\\n \tam335x-rut.dtb \\\n-\tam335x-sancloud-bbe.dtb \\\n-\tam335x-sancloud-bbe-lite.dtb \\\n-\tam335x-sancloud-bbe-extended-wifi.dtb \\\n \tam335x-shc.dtb \\\n \tam335x-pdu001.dtb \\\n \tam335x-chiliboard.dtb \\\ndiff --git a/arch/arm/dts/am335x-bone.dts b/arch/arm/dts/am335x-bone.dts\ndeleted file mode 100644\nindex b5d85ef51a021038a099ba4c2bdc0a80f44c25e3..0000000000000000000000000000000000000000\n--- a/arch/arm/dts/am335x-bone.dts\n+++ /dev/null\n@@ -1,23 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/\n- */\n-/dts-v1/;\n-\n-#include \"am33xx.dtsi\"\n-#include \"am335x-bone-common.dtsi\"\n-\n-/ {\n-\tmodel = \"TI AM335x BeagleBone\";\n-\tcompatible = \"ti,am335x-bone\", \"ti,am33xx\";\n-};\n-\n-&ldo3_reg {\n-\tregulator-min-microvolt = <1800000>;\n-\tregulator-max-microvolt = <3300000>;\n-\tregulator-always-on;\n-};\n-\n-&mmc1 {\n-\tvmmc-supply = <&ldo3_reg>;\n-};\ndiff --git a/arch/arm/dts/am335x-boneblack.dts b/arch/arm/dts/am335x-boneblack.dts\ndeleted file mode 100644\nindex b956e2f60fe0701bf35ccac55d0388017dc41a10..0000000000000000000000000000000000000000\n--- a/arch/arm/dts/am335x-boneblack.dts\n+++ /dev/null\n@@ -1,174 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/\n- */\n-/dts-v1/;\n-\n-#include \"am33xx.dtsi\"\n-#include \"am335x-bone-common.dtsi\"\n-#include \"am335x-boneblack-common.dtsi\"\n-#include \"am335x-boneblack-hdmi.dtsi\"\n-\n-/ {\n-\tmodel = \"TI AM335x BeagleBone Black\";\n-\tcompatible = \"ti,am335x-bone-black\", \"ti,am335x-bone\", \"ti,am33xx\";\n-};\n-\n-&cpu0_opp_table {\n-\t/*\n-\t * All PG 2.0 silicon may not support 1GHz but some of the early\n-\t * BeagleBone Blacks have PG 2.0 silicon which is guaranteed\n-\t * to support 1GHz OPP so enable it for PG 2.0 on this board.\n-\t */\n-\toppnitro-1000000000 {\n-\t\topp-supported-hw = <0x06 0x0100>;\n-\t};\n-};\n-\n-&gpio0 {\n-\tgpio-line-names =\n-\t\t\"[mdio_data]\",\n-\t\t\"[mdio_clk]\",\n-\t\t\"P9_22 [spi0_sclk]\",\n-\t\t\"P9_21 [spi0_d0]\",\n-\t\t\"P9_18 [spi0_d1]\",\n-\t\t\"P9_17 [spi0_cs0]\",\n-\t\t\"[mmc0_cd]\",\n-\t\t\"P8_42A [ecappwm0]\",\n-\t\t\"P8_35 [lcd d12]\",\n-\t\t\"P8_33 [lcd d13]\",\n-\t\t\"P8_31 [lcd d14]\",\n-\t\t\"P8_32 [lcd d15]\",\n-\t\t\"P9_20 [i2c2_sda]\",\n-\t\t\"P9_19 [i2c2_scl]\",\n-\t\t\"P9_26 [uart1_rxd]\",\n-\t\t\"P9_24 [uart1_txd]\",\n-\t\t\"[rmii1_txd3]\",\n-\t\t\"[rmii1_txd2]\",\n-\t\t\"[usb0_drvvbus]\",\n-\t\t\"[hdmi cec]\",\n-\t\t\"P9_41B\",\n-\t\t\"[rmii1_txd1]\",\n-\t\t\"P8_19 [ehrpwm2a]\",\n-\t\t\"P8_13 [ehrpwm2b]\",\n-\t\t\"NC\",\n-\t\t\"NC\",\n-\t\t\"P8_14\",\n-\t\t\"P8_17\",\n-\t\t\"[rmii1_txd0]\",\n-\t\t\"[rmii1_refclk]\",\n-\t\t\"P9_11 [uart4_rxd]\",\n-\t\t\"P9_13 [uart4_txd]\";\n-};\n-\n-&gpio1 {\n-\tgpio-line-names =\n-\t\t\"P8_25 [mmc1_dat0]\",\n-\t\t\"[mmc1_dat1]\",\n-\t\t\"P8_5 [mmc1_dat2]\",\n-\t\t\"P8_6 [mmc1_dat3]\",\n-\t\t\"P8_23 [mmc1_dat4]\",\n-\t\t\"P8_22 [mmc1_dat5]\",\n-\t\t\"P8_3 [mmc1_dat6]\",\n-\t\t\"P8_4 [mmc1_dat7]\",\n-\t\t\"NC\",\n-\t\t\"NC\",\n-\t\t\"NC\",\n-\t\t\"NC\",\n-\t\t\"P8_12\",\n-\t\t\"P8_11\",\n-\t\t\"P8_16\",\n-\t\t\"P8_15\",\n-\t\t\"P9_15A\",\n-\t\t\"P9_23\",\n-\t\t\"P9_14 [ehrpwm1a]\",\n-\t\t\"P9_16 [ehrpwm1b]\",\n-\t\t\"[emmc rst]\",\n-\t\t\"[usr0 led]\",\n-\t\t\"[usr1 led]\",\n-\t\t\"[usr2 led]\",\n-\t\t\"[usr3 led]\",\n-\t\t\"[hdmi irq]\",\n-\t\t\"[usb vbus oc]\",\n-\t\t\"[hdmi audio]\",\n-\t\t\"P9_12\",\n-\t\t\"P8_26\",\n-\t\t\"P8_21 [emmc]\",\n-\t\t\"P8_20 [emmc]\";\n-};\n-\n-&gpio2 {\n-\tgpio-line-names =\n-\t\t\"P9_15B\",\n-\t\t\"P8_18\",\n-\t\t\"P8_7\",\n-\t\t\"P8_8\",\n-\t\t\"P8_10\",\n-\t\t\"P8_9\",\n-\t\t\"P8_45 [hdmi]\",\n-\t\t\"P8_46 [hdmi]\",\n-\t\t\"P8_43 [hdmi]\",\n-\t\t\"P8_44 [hdmi]\",\n-\t\t\"P8_41 [hdmi]\",\n-\t\t\"P8_42 [hdmi]\",\n-\t\t\"P8_39 [hdmi]\",\n-\t\t\"P8_40 [hdmi]\",\n-\t\t\"P8_37 [hdmi]\",\n-\t\t\"P8_38 [hdmi]\",\n-\t\t\"P8_36 [hdmi]\",\n-\t\t\"P8_34 [hdmi]\",\n-\t\t\"[rmii1_rxd3]\",\n-\t\t\"[rmii1_rxd2]\",\n-\t\t\"[rmii1_rxd1]\",\n-\t\t\"[rmii1_rxd0]\",\n-\t\t\"P8_27 [hdmi]\",\n-\t\t\"P8_29 [hdmi]\",\n-\t\t\"P8_28 [hdmi]\",\n-\t\t\"P8_30 [hdmi]\",\n-\t\t\"[mmc0_dat3]\",\n-\t\t\"[mmc0_dat2]\",\n-\t\t\"[mmc0_dat1]\",\n-\t\t\"[mmc0_dat0]\",\n-\t\t\"[mmc0_clk]\",\n-\t\t\"[mmc0_cmd]\";\n-};\n-\n-&gpio3 {\n-\tgpio-line-names =\n-\t\t\"[mii col]\",\n-\t\t\"[mii crs]\",\n-\t\t\"[mii rx err]\",\n-\t\t\"[mii tx en]\",\n-\t\t\"[mii rx dv]\",\n-\t\t\"[i2c0 sda]\",\n-\t\t\"[i2c0 scl]\",\n-\t\t\"[jtag emu0]\",\n-\t\t\"[jtag emu1]\",\n-\t\t\"[mii tx clk]\",\n-\t\t\"[mii rx clk]\",\n-\t\t\"NC\",\n-\t\t\"NC\",\n-\t\t\"[usb vbus en]\",\n-\t\t\"P9_31 [spi1_sclk]\",\n-\t\t\"P9_29 [spi1_d0]\",\n-\t\t\"P9_30 [spi1_d1]\",\n-\t\t\"P9_28 [spi1_cs0]\",\n-\t\t\"P9_42B [ecappwm0]\",\n-\t\t\"P9_27\",\n-\t\t\"P9_41A\",\n-\t\t\"P9_25\",\n-\t\t\"NC\",\n-\t\t\"NC\",\n-\t\t\"NC\",\n-\t\t\"NC\",\n-\t\t\"NC\",\n-\t\t\"NC\",\n-\t\t\"NC\",\n-\t\t\"NC\",\n-\t\t\"NC\",\n-\t\t\"NC\";\n-};\n-\n-&baseboard_eeprom {\n-\tvcc-supply = <&ldo4_reg>;\n-};\ndiff --git a/arch/arm/dts/am335x-bonegreen-eco.dts b/arch/arm/dts/am335x-bonegreen-eco.dts\ndeleted file mode 100644\nindex 1e9d7fed3fd46f35cd4f92783ffeb81bd878d055..0000000000000000000000000000000000000000\n--- a/arch/arm/dts/am335x-bonegreen-eco.dts\n+++ /dev/null\n@@ -1,53 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * Copyright (C) 2025 Bootlin\n- */\n-/dts-v1/;\n-\n-#include \"am33xx.dtsi\"\n-#include \"am335x-bone-common.dtsi\"\n-#include \"am335x-bonegreen-common.dtsi\"\n-#include <dt-bindings/net/ti-dp83867.h>\n-\n-/ {\n-\tmodel = \"TI AM335x BeagleBone Green Eco\";\n-\tcompatible = \"ti,am335x-bone-green-eco\", \"ti,am335x-bone-green\",\n-\t\t     \"ti,am335x-bone-black\", \"ti,am335x-bone\", \"ti,am33xx\";\n-\n-\tcpus {\n-\t\tcpu@0 {\n-\t\t\t/delete-property/ cpu0-supply;\n-\t\t};\n-\t};\n-};\n-\n-&usb0 {\n-\tinterrupts-extended = <&intc 18>;\n-\tinterrupt-names = \"mc\";\n-};\n-\n-&cpsw_emac0 {\n-\tphy-mode = \"rgmii-id\";\n-\tphy-handle = <&dp83867_0>;\n-};\n-\n-&davinci_mdio {\n-\t/delete-node/ ethernet-phy@0;\n-\n-\tdp83867_0: ethernet-phy@0 {\n-\t\treg = <0>;\n-\t\tti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;\n-\t\tti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;\n-\t\tti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;\n-\t\tti,min-output-impedance;\n-\t\tti,dp83867-rxctrl-strap-quirk;\n-\t};\n-};\n-\n-&baseboard_eeprom {\n-\t/delete-property/ vcc-supply;\n-};\n-\n-&i2c0 {\n-\t/delete-node/ tps@24;\n-};\ndiff --git a/arch/arm/dts/am335x-bonegreen.dts b/arch/arm/dts/am335x-bonegreen.dts\ndeleted file mode 100644\nindex 18cc0f49e999c3b905257188b34ae2732b32d35c..0000000000000000000000000000000000000000\n--- a/arch/arm/dts/am335x-bonegreen.dts\n+++ /dev/null\n@@ -1,14 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/\n- */\n-/dts-v1/;\n-\n-#include \"am33xx.dtsi\"\n-#include \"am335x-bone-common.dtsi\"\n-#include \"am335x-bonegreen-common.dtsi\"\n-\n-/ {\n-\tmodel = \"TI AM335x BeagleBone Green\";\n-\tcompatible = \"ti,am335x-bone-green\", \"ti,am335x-bone-black\", \"ti,am335x-bone\", \"ti,am33xx\";\n-};\ndiff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts\ndeleted file mode 100644\nindex 52ca4ff6809ad24fafbdd515fbcde840715cf20f..0000000000000000000000000000000000000000\n--- a/arch/arm/dts/am335x-evm.dts\n+++ /dev/null\n@@ -1,767 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/\n- */\n-/dts-v1/;\n-\n-#include \"am33xx.dtsi\"\n-#include <dt-bindings/interrupt-controller/irq.h>\n-\n-/ {\n-\tmodel = \"TI AM335x EVM\";\n-\tcompatible = \"ti,am335x-evm\", \"ti,am33xx\";\n-\n-\tchosen {\n-\t\tstdout-path = &uart0;\n-\t\ttick-timer = &timer2;\n-\t};\n-\n-\tcpus {\n-\t\tcpu@0 {\n-\t\t\tcpu0-supply = <&vdd1_reg>;\n-\t\t};\n-\t};\n-\n-\tmemory@80000000 {\n-\t\tdevice_type = \"memory\";\n-\t\treg = <0x80000000 0x10000000>; /* 256 MB */\n-\t};\n-\n-\tvbat: fixedregulator0 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"vbat\";\n-\t\tregulator-min-microvolt = <5000000>;\n-\t\tregulator-max-microvolt = <5000000>;\n-\t\tregulator-boot-on;\n-\t};\n-\n-\tlis3_reg: fixedregulator1 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"lis3_reg\";\n-\t\tregulator-boot-on;\n-\t};\n-\n-\twlan_en_reg: fixedregulator2 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"wlan-en-regulator\";\n-\t\tregulator-min-microvolt = <1800000>;\n-\t\tregulator-max-microvolt = <1800000>;\n-\n-\t\t/* WLAN_EN GPIO for this board - Bank1, pin16 */\n-\t\tgpio = <&gpio1 16 0>;\n-\n-\t\t/* WLAN card specific delay */\n-\t\tstartup-delay-us = <70000>;\n-\t\tenable-active-high;\n-\t};\n-\n-\tmatrix_keypad: matrix_keypad@0 {\n-\t\tcompatible = \"gpio-matrix-keypad\";\n-\t\tdebounce-delay-ms = <5>;\n-\t\tcol-scan-delay-us = <2>;\n-\n-\t\trow-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH\t\t/* Bank1, pin25 */\n-\t\t\t     &gpio1 26 GPIO_ACTIVE_HIGH\t\t/* Bank1, pin26 */\n-\t\t\t     &gpio1 27 GPIO_ACTIVE_HIGH>;\t/* Bank1, pin27 */\n-\n-\t\tcol-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH\t\t/* Bank1, pin21 */\n-\t\t\t     &gpio1 22 GPIO_ACTIVE_HIGH>;\t/* Bank1, pin22 */\n-\n-\t\tlinux,keymap = <0x0000008b\t/* MENU */\n-\t\t\t\t0x0100009e\t/* BACK */\n-\t\t\t\t0x02000069\t/* LEFT */\n-\t\t\t\t0x0001006a\t/* RIGHT */\n-\t\t\t\t0x0101001c\t/* ENTER */\n-\t\t\t\t0x0201006c>;\t/* DOWN */\n-\t};\n-\n-\tgpio_keys: volume-keys {\n-\t\tcompatible = \"gpio-keys\";\n-\t\tautorepeat;\n-\n-\t\tswitch-9 {\n-\t\t\tlabel = \"volume-up\";\n-\t\t\tlinux,code = <115>;\n-\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n-\t\t\tgpio-key,wakeup;\n-\t\t};\n-\n-\t\tswitch-10 {\n-\t\t\tlabel = \"volume-down\";\n-\t\t\tlinux,code = <114>;\n-\t\t\tgpios = <&gpio0 3 GPIO_ACTIVE_LOW>;\n-\t\t\tgpio-key,wakeup;\n-\t\t};\n-\t};\n-\n-\tpwm_backlight: backlight {\n-\t\tcompatible = \"pwm-backlight\";\n-\t\tpwms = <&ecap0 0 50000 0>;\n-\t\tbrightness-levels = <0 51 53 56 62 75 101 152 255>;\n-\t\tdefault-brightness-level = <8>;\n-\t};\n-\n-\tpanel {\n-\t\tcompatible = \"ti,tilcdc,panel\";\n-\t\tstatus = \"okay\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&lcd_pins_s0>;\n-\t\tbacklight = <&pwm_backlight>;\n-\t\tpanel-info {\n-\t\t\tac-bias           = <255>;\n-\t\t\tac-bias-intrpt    = <0>;\n-\t\t\tdma-burst-sz      = <16>;\n-\t\t\tbpp               = <32>;\n-\t\t\tfdd               = <0x80>;\n-\t\t\tsync-edge         = <0>;\n-\t\t\tsync-ctrl         = <1>;\n-\t\t\traster-order      = <0>;\n-\t\t\tfifo-th           = <0>;\n-\t\t};\n-\n-\t\tdisplay-timings {\n-\t\t\t800x480p62 {\n-\t\t\t\tclock-frequency = <30000000>;\n-\t\t\t\thactive = <800>;\n-\t\t\t\tvactive = <480>;\n-\t\t\t\thfront-porch = <39>;\n-\t\t\t\thback-porch = <39>;\n-\t\t\t\thsync-len = <47>;\n-\t\t\t\tvback-porch = <29>;\n-\t\t\t\tvfront-porch = <13>;\n-\t\t\t\tvsync-len = <2>;\n-\t\t\t\thsync-active = <1>;\n-\t\t\t\tvsync-active = <1>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tsound {\n-\t\tcompatible = \"ti,da830-evm-audio\";\n-\t\tti,model = \"AM335x-EVM\";\n-\t\tti,audio-codec = <&tlv320aic3106>;\n-\t\tti,mcasp-controller = <&mcasp1>;\n-\t\tti,codec-clock-rate = <12000000>;\n-\t\tti,audio-routing =\n-\t\t\t\"Headphone Jack\",       \"HPLOUT\",\n-\t\t\t\"Headphone Jack\",       \"HPROUT\",\n-\t\t\t\"LINE1L\",               \"Line In\",\n-\t\t\t\"LINE1R\",               \"Line In\";\n-\t};\n-};\n-\n-&am33xx_pinmux {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;\n-\n-\tmatrix_keypad_s0: matrix_keypad_s0 {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_a5.gpio1_21 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_a6.gpio1_22 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_a9.gpio1_25 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_a10.gpio1_26 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_a11.gpio1_27 */\n-\t\t>;\n-\t};\n-\n-\tvolume_keys_s0: volume_keys_s0 {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* spi0_sclk.gpio0_2 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* spi0_d0.gpio0_3 */\n-\t\t>;\n-\t};\n-\n-\ti2c0_pins: pinmux_i2c0_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)\t/* i2c0_sda.i2c0_sda */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)\t/* i2c0_scl.i2c0_scl */\n-\t\t>;\n-\t};\n-\n-\ti2c1_pins: pinmux_i2c1_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2)\t/* spi0_d1.i2c1_sda */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2)\t/* spi0_cs0.i2c1_scl */\n-\t\t>;\n-\t};\n-\n-\tuart0_pins: pinmux_uart0_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n-\t\t>;\n-\t};\n-\n-\tuart1_pins: pinmux_uart1_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n-\t\t>;\n-\t};\n-\n-\tclkout2_pin: pinmux_clkout2_pin {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)\t/* xdma_event_intr1.clkout2 */\n-\t\t>;\n-\t};\n-\n-\tnandflash_pins_s0: nandflash_pins_s0 {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7)\t/* gpmc_wpn.gpio0_31 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)\n-\t\t>;\n-\t};\n-\n-\tecap0_pins: backlight_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0)\n-\t\t>;\n-\t};\n-\n-\tcpsw_default: cpsw_default {\n-\t\tpinctrl-single,pins = <\n-\t\t\t/* Slave 1 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txen.rgmii1_tctl */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxdv.rgmii1_rctl */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd3.rgmii1_td3 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd2.rgmii1_td2 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd1.rgmii1_td1 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd0.rgmii1_td0 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txclk.rgmii1_tclk */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxclk.rgmii1_rclk */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd3.rgmii1_rd3 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd2.rgmii1_rd2 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd1.rgmii1_rd1 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd0.rgmii1_rd0 */\n-\t\t>;\n-\t};\n-\n-\tcpsw_sleep: cpsw_sleep {\n-\t\tpinctrl-single,pins = <\n-\t\t\t/* Slave 1 reset value */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t>;\n-\t};\n-\n-\tdavinci_mdio_default: davinci_mdio_default {\n-\t\tpinctrl-single,pins = <\n-\t\t\t/* MDIO */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)\n-\t\t>;\n-\t};\n-\n-\tdavinci_mdio_sleep: davinci_mdio_sleep {\n-\t\tpinctrl-single,pins = <\n-\t\t\t/* MDIO reset value */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t>;\n-\t};\n-\n-\tmmc1_pins: pinmux_mmc1_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)\t\t/* spi0_cs1.gpio0_6 */\n-\t\t>;\n-\t};\n-\n-\tmmc3_pins: pinmux_mmc3_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */\n-\t\t>;\n-\t};\n-\n-\twlan_pins: pinmux_wlan_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_a0.gpio1_16 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7)\t\t/* mcasp0_ahclkr.gpio3_17 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* mcasp0_ahclkx.gpio3_21 */\n-\t\t>;\n-\t};\n-\n-\tlcd_pins_s0: lcd_pins_s0 {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_ad8.lcd_data23 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_ad9.lcd_data22 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_ad10.lcd_data21 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_ad11.lcd_data20 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_ad12.lcd_data19 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_ad13.lcd_data18 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_ad14.lcd_data17 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_ad15.lcd_data16 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)\n-\t\t>;\n-\t};\n-\n-\tmcasp1_pins: mcasp1_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */\n-\t\t>;\n-\t};\n-\n-\tdcan1_pins_default: dcan1_pins_default {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */\n-\t\t>;\n-\t};\n-};\n-\n-&uart0 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&uart0_pins>;\n-\n-\tstatus = \"okay\";\n-};\n-\n-&uart1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&uart1_pins>;\n-\n-\tstatus = \"okay\";\n-};\n-\n-&i2c0 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&i2c0_pins>;\n-\n-\tstatus = \"okay\";\n-\tclock-frequency = <400000>;\n-\n-\ttps: tps@2d {\n-\t\treg = <0x2d>;\n-\t};\n-};\n-\n-&usb {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_ctrl_mod {\n-\tstatus = \"okay\";\n-};\n-\n-&usb0_phy {\n-\tstatus = \"okay\";\n-};\n-\n-&usb1_phy {\n-\tstatus = \"okay\";\n-};\n-\n-&usb0 {\n-\tstatus = \"okay\";\n-};\n-\n-&usb1 {\n-\tstatus = \"okay\";\n-\tdr_mode = \"host\";\n-};\n-\n-&cppi41dma  {\n-\tstatus = \"okay\";\n-};\n-\n-&i2c1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&i2c1_pins>;\n-\n-\tstatus = \"okay\";\n-\tclock-frequency = <100000>;\n-\n-\tlis331dlh: lis331dlh@18 {\n-\t\tcompatible = \"st,lis331dlh\", \"st,lis3lv02d\";\n-\t\treg = <0x18>;\n-\t\tVdd-supply = <&lis3_reg>;\n-\t\tVdd_IO-supply = <&lis3_reg>;\n-\n-\t\tst,click-single-x;\n-\t\tst,click-single-y;\n-\t\tst,click-single-z;\n-\t\tst,click-thresh-x = <10>;\n-\t\tst,click-thresh-y = <10>;\n-\t\tst,click-thresh-z = <10>;\n-\t\tst,irq1-click;\n-\t\tst,irq2-click;\n-\t\tst,wakeup-x-lo;\n-\t\tst,wakeup-x-hi;\n-\t\tst,wakeup-y-lo;\n-\t\tst,wakeup-y-hi;\n-\t\tst,wakeup-z-lo;\n-\t\tst,wakeup-z-hi;\n-\t\tst,min-limit-x = <120>;\n-\t\tst,min-limit-y = <120>;\n-\t\tst,min-limit-z = <140>;\n-\t\tst,max-limit-x = <550>;\n-\t\tst,max-limit-y = <550>;\n-\t\tst,max-limit-z = <750>;\n-\t};\n-\n-\ttsl2550: tsl2550@39 {\n-\t\tcompatible = \"taos,tsl2550\";\n-\t\treg = <0x39>;\n-\t};\n-\n-\ttmp275: tmp275@48 {\n-\t\tcompatible = \"ti,tmp275\";\n-\t\treg = <0x48>;\n-\t};\n-\n-\ttlv320aic3106: tlv320aic3106@1b {\n-\t\tcompatible = \"ti,tlv320aic3106\";\n-\t\treg = <0x1b>;\n-\t\tstatus = \"okay\";\n-\n-\t\t/* Regulators */\n-\t\tAVDD-supply = <&vaux2_reg>;\n-\t\tIOVDD-supply = <&vaux2_reg>;\n-\t\tDRVDD-supply = <&vaux2_reg>;\n-\t\tDVDD-supply = <&vbat>;\n-\t};\n-};\n-\n-&lcdc {\n-\tstatus = \"okay\";\n-};\n-\n-&elm {\n-\tstatus = \"okay\";\n-};\n-\n-&epwmss0 {\n-\tstatus = \"okay\";\n-\n-\tecap0: pwm@100 {\n-\t\tstatus = \"okay\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&ecap0_pins>;\n-\t};\n-};\n-\n-&gpmc {\n-\tstatus = \"okay\";\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&nandflash_pins_s0>;\n-\tranges = <0 0 0x08000000 0x1000000>;\t/* CS0: 16MB for NAND */\n-\tnand@0,0 {\n-\t\treg = <0 0 4>; /* CS0, offset 0, IO size 4 */\n-\t\tti,nand-ecc-opt = \"bch8\";\n-\t\tti,elm-id = <&elm>;\n-\t\tnand-bus-width = <8>;\n-\t\tgpmc,device-width = <1>;\n-\t\tgpmc,sync-clk-ps = <0>;\n-\t\tgpmc,cs-on-ns = <0>;\n-\t\tgpmc,cs-rd-off-ns = <44>;\n-\t\tgpmc,cs-wr-off-ns = <44>;\n-\t\tgpmc,adv-on-ns = <6>;\n-\t\tgpmc,adv-rd-off-ns = <34>;\n-\t\tgpmc,adv-wr-off-ns = <44>;\n-\t\tgpmc,we-on-ns = <0>;\n-\t\tgpmc,we-off-ns = <40>;\n-\t\tgpmc,oe-on-ns = <0>;\n-\t\tgpmc,oe-off-ns = <54>;\n-\t\tgpmc,access-ns = <64>;\n-\t\tgpmc,rd-cycle-ns = <82>;\n-\t\tgpmc,wr-cycle-ns = <82>;\n-\t\tgpmc,wait-on-read = \"true\";\n-\t\tgpmc,wait-on-write = \"true\";\n-\t\tgpmc,bus-turnaround-ns = <0>;\n-\t\tgpmc,cycle2cycle-delay-ns = <0>;\n-\t\tgpmc,clk-activation-ns = <0>;\n-\t\tgpmc,wait-monitoring-ns = <0>;\n-\t\tgpmc,wr-access-ns = <40>;\n-\t\tgpmc,wr-data-mux-bus-ns = <0>;\n-\t\t/* MTD partition table */\n-\t\t/* All SPL-* partitions are sized to minimal length\n-\t\t * which can be independently programmable. For\n-\t\t * NAND flash this is equal to size of erase-block */\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\t\tpartition@0 {\n-\t\t\tlabel = \"NAND.SPL\";\n-\t\t\treg = <0x00000000 0x00020000>;\n-\t\t};\n-\t\tpartition@1 {\n-\t\t\tlabel = \"NAND.SPL.backup1\";\n-\t\t\treg = <0x00020000 0x00020000>;\n-\t\t};\n-\t\tpartition@2 {\n-\t\t\tlabel = \"NAND.SPL.backup2\";\n-\t\t\treg = <0x00040000 0x00020000>;\n-\t\t};\n-\t\tpartition@3 {\n-\t\t\tlabel = \"NAND.SPL.backup3\";\n-\t\t\treg = <0x00060000 0x00020000>;\n-\t\t};\n-\t\tpartition@4 {\n-\t\t\tlabel = \"NAND.u-boot-spl-os\";\n-\t\t\treg = <0x00080000 0x00040000>;\n-\t\t};\n-\t\tpartition@5 {\n-\t\t\tlabel = \"NAND.u-boot\";\n-\t\t\treg = <0x000C0000 0x00100000>;\n-\t\t};\n-\t\tpartition@6 {\n-\t\t\tlabel = \"NAND.u-boot-env\";\n-\t\t\treg = <0x001C0000 0x00020000>;\n-\t\t};\n-\t\tpartition@7 {\n-\t\t\tlabel = \"NAND.u-boot-env.backup1\";\n-\t\t\treg = <0x001E0000 0x00020000>;\n-\t\t};\n-\t\tpartition@8 {\n-\t\t\tlabel = \"NAND.kernel\";\n-\t\t\treg = <0x00200000 0x00800000>;\n-\t\t};\n-\t\tpartition@9 {\n-\t\t\tlabel = \"NAND.file-system\";\n-\t\t\treg = <0x00A00000 0x0F600000>;\n-\t\t};\n-\t};\n-};\n-\n-#include \"tps65910.dtsi\"\n-\n-&mcasp1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&mcasp1_pins>;\n-\n-\tstatus = \"okay\";\n-\n-\top-mode = <0>;          /* MCASP_IIS_MODE */\n-\ttdm-slots = <2>;\n-\t/* 4 serializers */\n-\tserial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */\n-\t\t0 0 1 2\n-\t>;\n-\ttx-num-evt = <32>;\n-\trx-num-evt = <32>;\n-};\n-\n-&tps {\n-\tvcc1-supply = <&vbat>;\n-\tvcc2-supply = <&vbat>;\n-\tvcc3-supply = <&vbat>;\n-\tvcc4-supply = <&vbat>;\n-\tvcc5-supply = <&vbat>;\n-\tvcc6-supply = <&vbat>;\n-\tvcc7-supply = <&vbat>;\n-\tvccio-supply = <&vbat>;\n-\n-\tregulators {\n-\t\tvrtc_reg: regulator@0 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvio_reg: regulator@1 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvdd1_reg: regulator@2 {\n-\t\t\t/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */\n-\t\t\tregulator-name = \"vdd_mpu\";\n-\t\t\tregulator-min-microvolt = <912500>;\n-\t\t\tregulator-max-microvolt = <1312500>;\n-\t\t\tregulator-boot-on;\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvdd2_reg: regulator@3 {\n-\t\t\t/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */\n-\t\t\tregulator-name = \"vdd_core\";\n-\t\t\tregulator-min-microvolt = <912500>;\n-\t\t\tregulator-max-microvolt = <1150000>;\n-\t\t\tregulator-boot-on;\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvdd3_reg: regulator@4 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvdig1_reg: regulator@5 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvdig2_reg: regulator@6 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvpll_reg: regulator@7 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvdac_reg: regulator@8 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvaux1_reg: regulator@9 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvaux2_reg: regulator@10 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvaux33_reg: regulator@11 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvmmc_reg: regulator@12 {\n-\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\tregulator-always-on;\n-\t\t};\n-\t};\n-};\n-\n-&mac {\n-\tpinctrl-names = \"default\", \"sleep\";\n-\tpinctrl-0 = <&cpsw_default>;\n-\tpinctrl-1 = <&cpsw_sleep>;\n-\tstatus = \"okay\";\n-\tslaves = <1>;\n-};\n-\n-&davinci_mdio {\n-\tpinctrl-names = \"default\", \"sleep\";\n-\tpinctrl-0 = <&davinci_mdio_default>;\n-\tpinctrl-1 = <&davinci_mdio_sleep>;\n-\tstatus = \"okay\";\n-\n-\tethphy0: ethernet-phy@0 {\n-\t\treg = <0>;\n-\t};\n-};\n-\n-&cpsw_emac0 {\n-\tphy-handle = <&ethphy0>;\n-\tphy-mode = \"rgmii-id\";\n-};\n-\n-&tscadc {\n-\tstatus = \"okay\";\n-\ttsc {\n-\t\tti,wires = <4>;\n-\t\tti,x-plate-resistance = <200>;\n-\t\tti,coordinate-readouts = <5>;\n-\t\tti,wire-config = <0x00 0x11 0x22 0x33>;\n-\t\tti,charge-delay = <0x400>;\n-\t};\n-\n-\tadc {\n-\t\tti,adc-channels = <4 5 6 7>;\n-\t};\n-};\n-\n-&mmc1 {\n-\tstatus = \"okay\";\n-\tvmmc-supply = <&vmmc_reg>;\n-\tbus-width = <4>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&mmc1_pins>;\n-\tcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;\n-};\n-\n-&mmc3 {\n-\t/* these are on the crossbar and are outlined in the\n-\t   xbar-event-map element */\n-\tdmas = <&edma 12 0\n-\t\t&edma 13 0>;\n-\tdma-names = \"tx\", \"rx\";\n-\tstatus = \"okay\";\n-\tvmmc-supply = <&wlan_en_reg>;\n-\tbus-width = <4>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&mmc3_pins &wlan_pins>;\n-\tti,non-removable;\n-\tti,needs-special-hs-handling;\n-\tcap-power-off-card;\n-\tkeep-power-in-suspend;\n-\n-\t#address-cells = <1>;\n-\t#size-cells = <0>;\n-\twlcore: wlcore@0 {\n-\t\tcompatible = \"ti,wl1835\";\n-\t\treg = <2>;\n-\t\tinterrupt-parent = <&gpio3>;\n-\t\tinterrupts = <17 IRQ_TYPE_LEVEL_HIGH>;\n-\t};\n-};\n-\n-&edma {\n-\tti,edma-xbar-event-map = /bits/ 16 <1 12\n-\t\t\t\t\t    2 13>;\n-};\n-\n-&sham {\n-\tstatus = \"okay\";\n-};\n-\n-&aes {\n-\tstatus = \"okay\";\n-};\n-\n-&dcan1 {\n-\tstatus = \"disabled\";\t/* Enable only if Profile 1 is selected */\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&dcan1_pins_default>;\n-};\n-\n-&rtc {\n-\tclocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;\n-\tclock-names = \"ext-clk\", \"int-clk\";\n-};\ndiff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts\ndeleted file mode 100644\nindex e0267657f9009135201db1b1f1b39c1e640b8d57..0000000000000000000000000000000000000000\n--- a/arch/arm/dts/am335x-evmsk.dts\n+++ /dev/null\n@@ -1,730 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/\n- */\n-\n-/*\n- * AM335x Starter Kit\n- * https://www.ti.com/tool/tmdssk3358\n- */\n-\n-/dts-v1/;\n-\n-#include \"am33xx.dtsi\"\n-#include <dt-bindings/pwm/pwm.h>\n-#include <dt-bindings/interrupt-controller/irq.h>\n-\n-/ {\n-\tmodel = \"TI AM335x EVM-SK\";\n-\tcompatible = \"ti,am335x-evmsk\", \"ti,am33xx\";\n-\n-\tchosen {\n-\t\tstdout-path = &uart0;\n-\t\ttick-timer = &timer2;\n-\t};\n-\n-\tcpus {\n-\t\tcpu@0 {\n-\t\t\tcpu0-supply = <&vdd1_reg>;\n-\t\t};\n-\t};\n-\n-\tmemory@80000000 {\n-\t\tdevice_type = \"memory\";\n-\t\treg = <0x80000000 0x10000000>; /* 256 MB */\n-\t};\n-\n-\tvbat: fixedregulator0 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"vbat\";\n-\t\tregulator-min-microvolt = <5000000>;\n-\t\tregulator-max-microvolt = <5000000>;\n-\t\tregulator-boot-on;\n-\t};\n-\n-\tlis3_reg: fixedregulator1 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"lis3_reg\";\n-\t\tregulator-boot-on;\n-\t};\n-\n-\twl12xx_vmmc: fixedregulator2 {\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&wl12xx_gpio>;\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"vwl1271\";\n-\t\tregulator-min-microvolt = <1800000>;\n-\t\tregulator-max-microvolt = <1800000>;\n-\t\tgpio = <&gpio1 29 0>;\n-\t\tstartup-delay-us = <70000>;\n-\t\tenable-active-high;\n-\t};\n-\n-\tvtt_fixed: fixedregulator3 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"vtt\";\n-\t\tregulator-min-microvolt = <1500000>;\n-\t\tregulator-max-microvolt = <1500000>;\n-\t\tgpio = <&gpio0 7 GPIO_ACTIVE_HIGH>;\n-\t\tregulator-always-on;\n-\t\tregulator-boot-on;\n-\t\tenable-active-high;\n-\t};\n-\n-\tleds {\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&user_leds_s0>;\n-\n-\t\tcompatible = \"gpio-leds\";\n-\n-\t\tled1 {\n-\t\t\tlabel = \"evmsk:green:usr0\";\n-\t\t\tgpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\n-\t\tled2 {\n-\t\t\tlabel = \"evmsk:green:usr1\";\n-\t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\n-\t\tled3 {\n-\t\t\tlabel = \"evmsk:green:mmc0\";\n-\t\t\tgpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;\n-\t\t\tlinux,default-trigger = \"mmc0\";\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\n-\t\tled4 {\n-\t\t\tlabel = \"evmsk:green:heartbeat\";\n-\t\t\tgpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;\n-\t\t\tlinux,default-trigger = \"heartbeat\";\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\t};\n-\n-\tgpio_buttons: gpio_buttons0 {\n-\t\tcompatible = \"gpio-keys\";\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\tswitch1 {\n-\t\t\tlabel = \"button0\";\n-\t\t\tlinux,code = <0x100>;\n-\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;\n-\t\t};\n-\n-\t\tswitch2 {\n-\t\t\tlabel = \"button1\";\n-\t\t\tlinux,code = <0x101>;\n-\t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;\n-\t\t};\n-\n-\t\tswitch3 {\n-\t\t\tlabel = \"button2\";\n-\t\t\tlinux,code = <0x102>;\n-\t\t\tgpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;\n-\t\t\twakeup-source;\n-\t\t};\n-\n-\t\tswitch4 {\n-\t\t\tlabel = \"button3\";\n-\t\t\tlinux,code = <0x103>;\n-\t\t\tgpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;\n-\t\t};\n-\t};\n-\n-\tlcd_bl: backlight {\n-\t\tcompatible = \"pwm-backlight\";\n-\t\tpwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>;\n-\t\tbrightness-levels = <0 58 61 66 75 90 125 170 255>;\n-\t\tdefault-brightness-level = <8>;\n-\t};\n-\n-\tsound {\n-\t\tcompatible = \"simple-audio-card\";\n-\t\tsimple-audio-card,name = \"AM335x-EVMSK\";\n-\t\tsimple-audio-card,widgets =\n-\t\t\t\"Headphone\", \"Headphone Jack\";\n-\t\tsimple-audio-card,routing =\n-\t\t\t\"Headphone Jack\",\t\"HPLOUT\",\n-\t\t\t\"Headphone Jack\",\t\"HPROUT\";\n-\t\tsimple-audio-card,format = \"dsp_b\";\n-\t\tsimple-audio-card,bitclock-master = <&sound_master>;\n-\t\tsimple-audio-card,frame-master = <&sound_master>;\n-\t\tsimple-audio-card,bitclock-inversion;\n-\n-\t\tsimple-audio-card,cpu {\n-\t\t\tsound-dai = <&mcasp1>;\n-\t\t};\n-\n-\t\tsound_master: simple-audio-card,codec {\n-\t\t\tsound-dai = <&tlv320aic3106>;\n-\t\t\tsystem-clock-frequency = <24000000>;\n-\t\t};\n-\t};\n-\n-\tpanel {\n-\t\tcompatible = \"ti,tilcdc,panel\";\n-\t\tpinctrl-names = \"default\", \"sleep\";\n-\t\tpinctrl-0 = <&lcd_pins_default>;\n-\t\tpinctrl-1 = <&lcd_pins_sleep>;\n-\t\tstatus = \"okay\";\n-\t\tpanel-info {\n-\t\t\tac-bias           = <255>;\n-\t\t\tac-bias-intrpt    = <0>;\n-\t\t\tdma-burst-sz      = <16>;\n-\t\t\tbpp               = <32>;\n-\t\t\tfdd               = <0x80>;\n-\t\t\tsync-edge         = <0>;\n-\t\t\tsync-ctrl         = <1>;\n-\t\t\traster-order      = <0>;\n-\t\t\tfifo-th           = <0>;\n-\t\t};\n-\t\tdisplay-timings {\n-\t\t\t480x272 {\n-\t\t\t\thactive         = <480>;\n-\t\t\t\tvactive         = <272>;\n-\t\t\t\thback-porch     = <43>;\n-\t\t\t\thfront-porch    = <8>;\n-\t\t\t\thsync-len       = <4>;\n-\t\t\t\tvback-porch     = <12>;\n-\t\t\t\tvfront-porch    = <4>;\n-\t\t\t\tvsync-len       = <10>;\n-\t\t\t\tclock-frequency = <9000000>;\n-\t\t\t\thsync-active    = <0>;\n-\t\t\t\tvsync-active    = <0>;\n-\t\t\t};\n-\t\t};\n-\t};\n-};\n-\n-&am33xx_pinmux {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;\n-\n-\tlcd_pins_default: lcd_pins_default {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1)\t/* gpmc_ad8.lcd_data23 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1)\t/* gpmc_ad9.lcd_data22 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1)\t/* gpmc_ad10.lcd_data21 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1)\t/* gpmc_ad11.lcd_data20 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1)\t/* gpmc_ad12.lcd_data19 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1)\t/* gpmc_ad13.lcd_data18 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1)\t/* gpmc_ad14.lcd_data17 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1)\t/* gpmc_ad15.lcd_data16 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)\n-\t\t>;\n-\t};\n-\n-\tlcd_pins_sleep: lcd_pins_sleep {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad8.lcd_data23 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad9.lcd_data22 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad10.lcd_data21 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad11.lcd_data20 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad12.lcd_data19 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad13.lcd_data18 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad14.lcd_data17 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad15.lcd_data16 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t>;\n-\t};\n-\n-\n-\tuser_leds_s0: user_leds_s0 {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad4.gpio1_4 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad5.gpio1_5 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad6.gpio1_6 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad7.gpio1_7 */\n-\t\t>;\n-\t};\n-\n-\tgpio_keys_s0: gpio_keys_s0 {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_oen_ren.gpio2_3 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_advn_ale.gpio2_2 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_wait0.gpio0_30 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ben0_cle.gpio2_5 */\n-\t\t>;\n-\t};\n-\n-\ti2c0_pins: pinmux_i2c0_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t>;\n-\t};\n-\n-\tuart0_pins: pinmux_uart0_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n-\t\t>;\n-\t};\n-\n-\tclkout2_pin: pinmux_clkout2_pin {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)\t/* xdma_event_intr1.clkout2 */\n-\t\t>;\n-\t};\n-\n-\tecap2_pins: backlight_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, 0x0, MUX_MODE4)\t/* mcasp0_ahclkr.ecap2_in_pwm2_out */\n-\t\t>;\n-\t};\n-\n-\tcpsw_default: cpsw_default {\n-\t\tpinctrl-single,pins = <\n-\t\t\t/* Slave 1 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txen.rgmii1_tctl */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxdv.rgmii1_rctl */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd3.rgmii1_td3 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd2.rgmii1_td2 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd1.rgmii1_td1 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd0.rgmii1_td0 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txclk.rgmii1_tclk */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxclk.rgmii1_rclk */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd3.rgmii1_rd3 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd2.rgmii1_rd2 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd1.rgmii1_rd1 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd0.rgmii1_rd0 */\n-\n-\t\t\t/* Slave 2 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a0.rgmii2_tctl */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a1.rgmii2_rctl */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a2.rgmii2_td3 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a3.rgmii2_td2 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a4.rgmii2_td1 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a5.rgmii2_td0 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a6.rgmii2_tclk */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a7.rgmii2_rclk */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a8.rgmii2_rd3 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a9.rgmii2_rd2 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a10.rgmii2_rd1 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a11.rgmii2_rd0 */\n-\t\t>;\n-\t};\n-\n-\tcpsw_sleep: cpsw_sleep {\n-\t\tpinctrl-single,pins = <\n-\t\t\t/* Slave 1 reset value */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\n-\t\t\t/* Slave 2 reset value*/\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t>;\n-\t};\n-\n-\tdavinci_mdio_default: davinci_mdio_default {\n-\t\tpinctrl-single,pins = <\n-\t\t\t/* MDIO */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)\n-\t\t>;\n-\t};\n-\n-\tdavinci_mdio_sleep: davinci_mdio_sleep {\n-\t\tpinctrl-single,pins = <\n-\t\t\t/* MDIO reset value */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t>;\n-\t};\n-\n-\tmmc1_pins: pinmux_mmc1_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) \t\t/* spi0_cs1.gpio0_6 */\n-\t\t>;\n-\t};\n-\n-\tmcasp1_pins: mcasp1_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */\n-\t\t>;\n-\t};\n-\n-\tmcasp1_pins_sleep: mcasp1_pins_sleep {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t>;\n-\t};\n-\n-\tmmc2_pins: pinmux_mmc2_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */\n-\t\t>;\n-\t};\n-\n-\twl12xx_gpio: pinmux_wl12xx_gpio {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */\n-\t\t>;\n-\t};\n-};\n-\n-&uart0 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&uart0_pins>;\n-\n-\tstatus = \"okay\";\n-};\n-\n-&i2c0 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&i2c0_pins>;\n-\n-\tstatus = \"okay\";\n-\tclock-frequency = <400000>;\n-\n-\ttps: tps@2d {\n-\t\treg = <0x2d>;\n-\t};\n-\n-\tlis331dlh: lis331dlh@18 {\n-\t\tcompatible = \"st,lis331dlh\", \"st,lis3lv02d\";\n-\t\treg = <0x18>;\n-\t\tVdd-supply = <&lis3_reg>;\n-\t\tVdd_IO-supply = <&lis3_reg>;\n-\n-\t\tst,click-single-x;\n-\t\tst,click-single-y;\n-\t\tst,click-single-z;\n-\t\tst,click-thresh-x = <10>;\n-\t\tst,click-thresh-y = <10>;\n-\t\tst,click-thresh-z = <10>;\n-\t\tst,irq1-click;\n-\t\tst,irq2-click;\n-\t\tst,wakeup-x-lo;\n-\t\tst,wakeup-x-hi;\n-\t\tst,wakeup-y-lo;\n-\t\tst,wakeup-y-hi;\n-\t\tst,wakeup-z-lo;\n-\t\tst,wakeup-z-hi;\n-\t\tst,min-limit-x = <120>;\n-\t\tst,min-limit-y = <120>;\n-\t\tst,min-limit-z = <140>;\n-\t\tst,max-limit-x = <550>;\n-\t\tst,max-limit-y = <550>;\n-\t\tst,max-limit-z = <750>;\n-\t};\n-\n-\ttlv320aic3106: tlv320aic3106@1b {\n-\t\t#sound-dai-cells = <0>;\n-\t\tcompatible = \"ti,tlv320aic3106\";\n-\t\treg = <0x1b>;\n-\t\tstatus = \"okay\";\n-\n-\t\t/* Regulators */\n-\t\tAVDD-supply = <&vaux2_reg>;\n-\t\tIOVDD-supply = <&vaux2_reg>;\n-\t\tDRVDD-supply = <&vaux2_reg>;\n-\t\tDVDD-supply = <&vbat>;\n-\t};\n-};\n-\n-&usb {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_ctrl_mod {\n-\tstatus = \"okay\";\n-};\n-\n-&usb0_phy {\n-\tstatus = \"okay\";\n-};\n-\n-&usb1_phy {\n-\tstatus = \"okay\";\n-};\n-\n-&usb0 {\n-\tstatus = \"okay\";\n-};\n-\n-&usb1 {\n-\tstatus = \"okay\";\n-\tdr_mode = \"host\";\n-};\n-\n-&cppi41dma  {\n-\tstatus = \"okay\";\n-};\n-\n-&epwmss2 {\n-\tstatus = \"okay\";\n-\n-\tecap2: pwm@100 {\n-\t\tstatus = \"okay\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&ecap2_pins>;\n-\t};\n-};\n-\n-#include \"tps65910.dtsi\"\n-\n-&tps {\n-\tvcc1-supply = <&vbat>;\n-\tvcc2-supply = <&vbat>;\n-\tvcc3-supply = <&vbat>;\n-\tvcc4-supply = <&vbat>;\n-\tvcc5-supply = <&vbat>;\n-\tvcc6-supply = <&vbat>;\n-\tvcc7-supply = <&vbat>;\n-\tvccio-supply = <&vbat>;\n-\n-\tregulators {\n-\t\tvrtc_reg: regulator@0 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvio_reg: regulator@1 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvdd1_reg: regulator@2 {\n-\t\t\t/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */\n-\t\t\tregulator-name = \"vdd_mpu\";\n-\t\t\tregulator-min-microvolt = <912500>;\n-\t\t\tregulator-max-microvolt = <1312500>;\n-\t\t\tregulator-boot-on;\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvdd2_reg: regulator@3 {\n-\t\t\t/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */\n-\t\t\tregulator-name = \"vdd_core\";\n-\t\t\tregulator-min-microvolt = <912500>;\n-\t\t\tregulator-max-microvolt = <1150000>;\n-\t\t\tregulator-boot-on;\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvdd3_reg: regulator@4 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvdig1_reg: regulator@5 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvdig2_reg: regulator@6 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvpll_reg: regulator@7 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvdac_reg: regulator@8 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvaux1_reg: regulator@9 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvaux2_reg: regulator@10 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvaux33_reg: regulator@11 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvmmc_reg: regulator@12 {\n-\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\tregulator-always-on;\n-\t\t};\n-\t};\n-};\n-\n-&mac {\n-\tpinctrl-names = \"default\", \"sleep\";\n-\tpinctrl-0 = <&cpsw_default>;\n-\tpinctrl-1 = <&cpsw_sleep>;\n-\tdual_emac = <1>;\n-\tstatus = \"okay\";\n-};\n-\n-&davinci_mdio {\n-\tpinctrl-names = \"default\", \"sleep\";\n-\tpinctrl-0 = <&davinci_mdio_default>;\n-\tpinctrl-1 = <&davinci_mdio_sleep>;\n-\tstatus = \"okay\";\n-\n-\tethphy0: ethernet-phy@0 {\n-\t\treg = <0>;\n-\t};\n-\n-\tethphy1: ethernet-phy@1 {\n-\t\treg = <1>;\n-\t};\n-};\n-\n-&cpsw_emac0 {\n-\tphy-handle = <&ethphy0>;\n-\tphy-mode = \"rgmii-id\";\n-\tdual_emac_res_vlan = <1>;\n-};\n-\n-&cpsw_emac1 {\n-\tphy-handle = <&ethphy1>;\n-\tphy-mode = \"rgmii-id\";\n-\tdual_emac_res_vlan = <2>;\n-};\n-\n-&mmc1 {\n-\tstatus = \"okay\";\n-\tvmmc-supply = <&vmmc_reg>;\n-\tbus-width = <4>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&mmc1_pins>;\n-\tcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;\n-};\n-\n-&sham {\n-\tstatus = \"okay\";\n-};\n-\n-&aes {\n-\tstatus = \"okay\";\n-};\n-\n-&gpio0 {\n-\tti,no-reset-on-init;\n-};\n-\n-&mmc2 {\n-\tstatus = \"okay\";\n-\tvmmc-supply = <&wl12xx_vmmc>;\n-\tti,non-removable;\n-\tbus-width = <4>;\n-\tcap-power-off-card;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&mmc2_pins>;\n-\n-\t#address-cells = <1>;\n-\t#size-cells = <0>;\n-\twlcore: wlcore@2 {\n-\t\tcompatible = \"ti,wl1271\";\n-\t\treg = <2>;\n-\t\tinterrupt-parent = <&gpio0>;\n-\t\tinterrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */\n-\t\tref-clock-frequency = <38400000>;\n-\t};\n-};\n-\n-&mcasp1 {\n-\t#sound-dai-cells = <0>;\n-\tpinctrl-names = \"default\", \"sleep\";\n-\tpinctrl-0 = <&mcasp1_pins>;\n-\tpinctrl-1 = <&mcasp1_pins_sleep>;\n-\n-\tstatus = \"okay\";\n-\n-\top-mode = <0>;          /* MCASP_IIS_MODE */\n-\ttdm-slots = <2>;\n-\t/* 4 serializers */\n-\tserial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */\n-\t\t0 0 1 2\n-\t>;\n-\ttx-num-evt = <32>;\n-\trx-num-evt = <32>;\n-};\n-\n-&tscadc {\n-\tstatus = \"okay\";\n-\ttsc {\n-\t\tti,wires = <4>;\n-\t\tti,x-plate-resistance = <200>;\n-\t\tti,coordinate-readouts = <5>;\n-\t\tti,wire-config = <0x00 0x11 0x22 0x33>;\n-\t};\n-};\n-\n-&lcdc {\n-\tstatus = \"okay\";\n-};\n-\n-&rtc {\n-\tclocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;\n-\tclock-names = \"ext-clk\", \"int-clk\";\n-};\ndiff --git a/arch/arm/dts/am335x-icev2.dts b/arch/arm/dts/am335x-icev2.dts\ndeleted file mode 100644\nindex bcfdbb772c11d0a0d7fd24e61c4ae6e529619a87..0000000000000000000000000000000000000000\n--- a/arch/arm/dts/am335x-icev2.dts\n+++ /dev/null\n@@ -1,486 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/\n- */\n-\n-/*\n- * AM335x ICE V2 board\n- * https://www.ti.com/tool/tmdsice3359\n- */\n-\n-/dts-v1/;\n-\n-#include \"am33xx.dtsi\"\n-\n-/ {\n-\tmodel = \"TI AM3359 ICE-V2\";\n-\tcompatible = \"ti,am3359-icev2\", \"ti,am33xx\";\n-\n-\tchosen {\n-\t\tstdout-path = &uart3;\n-\t\ttick-timer = &timer2;\n-\t};\n-\n-\tmemory@80000000 {\n-\t\tdevice_type = \"memory\";\n-\t\treg = <0x80000000 0x10000000>; /* 256 MB */\n-\t};\n-\n-\tvbat: fixedregulator0 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"vbat\";\n-\t\tregulator-min-microvolt = <5000000>;\n-\t\tregulator-max-microvolt = <5000000>;\n-\t\tregulator-boot-on;\n-\t};\n-\n-\tvtt_fixed: fixedregulator1 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"vtt\";\n-\t\tregulator-min-microvolt = <1500000>;\n-\t\tregulator-max-microvolt = <1500000>;\n-\t\tgpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;\n-\t\tregulator-always-on;\n-\t\tregulator-boot-on;\n-\t\tenable-active-high;\n-\t};\n-\n-\tleds-iio {\n-\t\tcompatible = \"gpio-leds\";\n-\t\tled-out0 {\n-\t\t\tlabel = \"out0\";\n-\t\t\tgpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\n-\t\tled-out1 {\n-\t\t\tlabel = \"out1\";\n-\t\t\tgpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\n-\t\tled-out2 {\n-\t\t\tlabel = \"out2\";\n-\t\t\tgpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\n-\t\tled-out3 {\n-\t\t\tlabel = \"out3\";\n-\t\t\tgpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\n-\t\tled-out4 {\n-\t\t\tlabel = \"out4\";\n-\t\t\tgpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\n-\t\tled-out5 {\n-\t\t\tlabel = \"out5\";\n-\t\t\tgpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\n-\t\tled-out6 {\n-\t\t\tlabel = \"out6\";\n-\t\t\tgpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\n-\t\tled-out7 {\n-\t\t\tlabel = \"out7\";\n-\t\t\tgpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\t};\n-\n-\t/* Tricolor status LEDs */\n-\tleds1 {\n-\t\tcompatible = \"gpio-leds\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&user_leds>;\n-\n-\t\tled0 {\n-\t\t\tlabel = \"status0:red:cpu0\";\n-\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"off\";\n-\t\t\tlinux,default-trigger = \"cpu0\";\n-\t\t};\n-\n-\t\tled1 {\n-\t\t\tlabel = \"status0:green:usr\";\n-\t\t\tgpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\n-\t\tled2 {\n-\t\t\tlabel = \"status0:yellow:usr\";\n-\t\t\tgpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\n-\t\tled3 {\n-\t\t\tlabel = \"status1:red:mmc0\";\n-\t\t\tgpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"off\";\n-\t\t\tlinux,default-trigger = \"mmc0\";\n-\t\t};\n-\n-\t\tled4 {\n-\t\t\tlabel = \"status1:green:usr\";\n-\t\t\tgpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\n-\t\tled5 {\n-\t\t\tlabel = \"status1:yellow:usr\";\n-\t\t\tgpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\t};\n-};\n-\n-&am33xx_pinmux {\n-\tuser_leds: user_leds {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */\n-\t\t>;\n-\t};\n-\n-\tmmc0_pins_default: mmc0_pins_default {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */\n-\t\t>;\n-\t};\n-\n-\ti2c0_pins_default: i2c0_pins_default {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)\n-\t\t>;\n-\t};\n-\n-\tspi0_pins_default: spi0_pins_default {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */\n-\t\t\tAM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */\n-\t\t\tAM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */\n-\t\t\tAM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */\n-\t\t>;\n-\t};\n-\n-\tuart3_pins_default: uart3_pins_default {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */\n-\t\t>;\n-\t};\n-\n-\tcpsw_default: cpsw_default {\n-\t\tpinctrl-single,pins = <\n-\t\t\t/* Slave 1, RMII mode */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1)\t/* mii1_crs.rmii1_crs_dv */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)\t/* mii1_rxerr.rmii1_rxerr */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)\t/* mii1_txd0.rmii1_txd0 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)\t/* mii1_txd1.rmii1_txd1 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)\t/* mii1_txen.rmii1_txen */\n-\t\t\t/* Slave 2, RMII mode */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_wait0.rmii2_crs_dv */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE1)\t/* mii1_col.rmii2_refclk */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_a11.rmii2_rxd0 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_a10.rmii2_rxd1 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_wpn.rmii2_rxerr */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3)\t/* gpmc_a5.rmii2_txd0 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3)\t/* gpmc_a4.rmii2_txd1 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)\t/* gpmc_a0.rmii2_txen */\n-\t\t>;\n-\t};\n-\n-\tcpsw_sleep: cpsw_sleep {\n-\t\tpinctrl-single,pins = <\n-\t\t\t/* Slave 1 reset value */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\n-\t\t\t/* Slave 2 reset value */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t>;\n-\t};\n-\n-\tdavinci_mdio_default: davinci_mdio_default {\n-\t\tpinctrl-single,pins = <\n-\t\t\t/* MDIO */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)\n-\t\t>;\n-\t};\n-\n-\tdavinci_mdio_sleep: davinci_mdio_sleep {\n-\t\tpinctrl-single,pins = <\n-\t\t\t/* MDIO reset value */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t>;\n-\t};\n-};\n-\n-&i2c0 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&i2c0_pins_default>;\n-\n-\tstatus = \"okay\";\n-\tclock-frequency = <400000>;\n-\n-\ttps: power-controller@2d {\n-\t\treg = <0x2d>;\n-\t};\n-\n-\ttpic2810: gpio@60 {\n-\t\tcompatible = \"ti,tpic2810\";\n-\t\treg = <0x60>;\n-\t\tgpio-controller;\n-\t\t#gpio-cells = <2>;\n-\t};\n-};\n-\n-&spi0 {\n-\tstatus = \"okay\";\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&spi0_pins_default>;\n-\n-\tsn65hvs882@1 {\n-\t\tcompatible = \"pisosr-gpio\";\n-\t\tgpio-controller;\n-\t\t#gpio-cells = <2>;\n-\n-\t\tload-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;\n-\n-\t\treg = <1>;\n-\t\tspi-max-frequency = <1000000>;\n-\t\tspi-cpol;\n-\t};\n-\n-\tspi_nor: flash@0 {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\t\tcompatible = \"winbond,w25q64\", \"jedec,spi-nor\";\n-\t\tspi-max-frequency = <80000000>;\n-\t\tm25p,fast-read;\n-\t\treg = <0>;\n-\n-\t\tpartition@0 {\n-\t\t\tlabel = \"u-boot-spl\";\n-\t\t\treg = <0x0 0x80000>;\n-\t\t\tread-only;\n-\t\t};\n-\n-\t\tpartition@1 {\n-\t\t\tlabel = \"u-boot\";\n-\t\t\treg = <0x80000 0x100000>;\n-\t\t\tread-only;\n-\t\t};\n-\n-\t\tpartition@2 {\n-\t\t\tlabel = \"u-boot-env\";\n-\t\t\treg = <0x180000 0x20000>;\n-\t\t\tread-only;\n-\t\t};\n-\n-\t\tpartition@3 {\n-\t\t\tlabel = \"misc\";\n-\t\t\treg = <0x1A0000 0x660000>;\n-\t\t};\n-\t};\n-};\n-\n-#include \"tps65910.dtsi\"\n-\n-&tps {\n-\tvcc1-supply = <&vbat>;\n-\tvcc2-supply = <&vbat>;\n-\tvcc3-supply = <&vbat>;\n-\tvcc4-supply = <&vbat>;\n-\tvcc5-supply = <&vbat>;\n-\tvcc6-supply = <&vbat>;\n-\tvcc7-supply = <&vbat>;\n-\tvccio-supply = <&vbat>;\n-\n-\tregulators {\n-\t\tvrtc_reg: regulator@0 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvio_reg: regulator@1 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvdd1_reg: regulator@2 {\n-\t\t\tregulator-name = \"vdd_mpu\";\n-\t\t\tregulator-min-microvolt = <912500>;\n-\t\t\tregulator-max-microvolt = <1326000>;\n-\t\t\tregulator-boot-on;\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvdd2_reg: regulator@3 {\n-\t\t\tregulator-name = \"vdd_core\";\n-\t\t\tregulator-min-microvolt = <912500>;\n-\t\t\tregulator-max-microvolt = <1144000>;\n-\t\t\tregulator-boot-on;\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvdd3_reg: regulator@4 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvdig1_reg: regulator@5 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvdig2_reg: regulator@6 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvpll_reg: regulator@7 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvdac_reg: regulator@8 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvaux1_reg: regulator@9 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvaux2_reg: regulator@10 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvaux33_reg: regulator@11 {\n-\t\t\tregulator-always-on;\n-\t\t};\n-\n-\t\tvmmc_reg: regulator@12 {\n-\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\tregulator-always-on;\n-\t\t};\n-\t};\n-};\n-\n-&mmc1 {\n-\tstatus = \"okay\";\n-\tvmmc-supply = <&vmmc_reg>;\n-\tbus-width = <4>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&mmc0_pins_default>;\n-};\n-\n-&gpio0 {\n-\t/* Do not idle the GPIO used for holding the VTT regulator */\n-\tti,no-reset-on-init;\n-\tti,no-idle-on-init;\n-\n-\tp7 {\n-\t\tgpio-hog;\n-\t\tgpios = <7 GPIO_ACTIVE_HIGH>;\n-\t\toutput-high;\n-\t\tline-name = \"FET_SWITCH_CTRL\";\n-\t};\n-};\n-\n-&uart3 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&uart3_pins_default>;\n-\tstatus = \"okay\";\n-};\n-\n-&gpio3 {\n-\tpr1-mii-ctl-hog {\n-\t\tgpio-hog;\n-\t\tgpios = <4 GPIO_ACTIVE_HIGH>;\n-\t\toutput-high;\n-\t\tline-name = \"PR1_MII_CTRL\";\n-\t};\n-\n-\tmux-mii-hog {\n-\t\tgpio-hog;\n-\t\tgpios = <10 GPIO_ACTIVE_HIGH>;\n-\t\t/* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */\n-\t\toutput-high;\n-\t\tline-name = \"MUX_MII_CTRL\";\n-\t};\n-};\n-\n-&cpsw_emac0 {\n-\tphy-handle = <&ethphy0>;\n-\tphy-mode = \"rmii\";\n-\tdual_emac_res_vlan = <1>;\n-};\n-\n-&cpsw_emac1 {\n-\tphy-handle = <&ethphy1>;\n-\tphy-mode = \"rmii\";\n-\tdual_emac_res_vlan = <2>;\n-};\n-\n-&mac {\n-\tpinctrl-names = \"default\", \"sleep\";\n-\tpinctrl-0 = <&cpsw_default>;\n-\tpinctrl-1 = <&cpsw_sleep>;\n-\tstatus = \"okay\";\n-\tdual_emac;\n-};\n-\n-&phy_sel {\n-\trmii-clock-ext;\n-};\n-\n-&davinci_mdio {\n-\tpinctrl-names = \"default\", \"sleep\";\n-\tpinctrl-0 = <&davinci_mdio_default>;\n-\tpinctrl-1 = <&davinci_mdio_sleep>;\n-\tstatus = \"okay\";\n-\treset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;\n-\treset-delay-us = <2>;   /* PHY datasheet states 1uS min */\n-\n-\tethphy0: ethernet-phy@1 {\n-\t\treg = <1>;\n-\t};\n-\n-\tethphy1: ethernet-phy@3 {\n-\t\treg = <3>;\n-\t};\n-};\n-\ndiff --git a/arch/arm/dts/am335x-pocketbeagle.dts b/arch/arm/dts/am335x-pocketbeagle.dts\ndeleted file mode 100644\nindex b379e3a5570d4e8fd70ab69e996d909068d8538d..0000000000000000000000000000000000000000\n--- a/arch/arm/dts/am335x-pocketbeagle.dts\n+++ /dev/null\n@@ -1,237 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0\n-/*\n- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/\n- *\n- * Author: Robert Nelson <robertcnelson@gmail.com>\n- */\n-/dts-v1/;\n-\n-#include \"am33xx.dtsi\"\n-#include \"am335x-osd335x-common.dtsi\"\n-\n-/ {\n-\tmodel = \"TI AM335x PocketBeagle\";\n-\tcompatible = \"ti,am335x-pocketbeagle\", \"ti,am335x-bone\", \"ti,am33xx\";\n-\n-\tchosen {\n-\t\tstdout-path = &uart0;\n-\t};\n-\n-\tleds {\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&usr_leds_pins>;\n-\n-\t\tcompatible = \"gpio-leds\";\n-\n-\t\tled-usr0 {\n-\t\t\tlabel = \"beaglebone:green:usr0\";\n-\t\t\tgpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;\n-\t\t\tlinux,default-trigger = \"heartbeat\";\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\n-\t\tled-usr1 {\n-\t\t\tlabel = \"beaglebone:green:usr1\";\n-\t\t\tgpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;\n-\t\t\tlinux,default-trigger = \"mmc0\";\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\n-\t\tled-usr2 {\n-\t\t\tlabel = \"beaglebone:green:usr2\";\n-\t\t\tgpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;\n-\t\t\tlinux,default-trigger = \"cpu0\";\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\n-\t\tled-usr3 {\n-\t\t\tlabel = \"beaglebone:green:usr3\";\n-\t\t\tgpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\t};\n-\n-\tvmmcsd_fixed: fixedregulator0 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"vmmcsd_fixed\";\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-max-microvolt = <3300000>;\n-\t};\n-};\n-\n-&am33xx_pinmux {\n-\ti2c2_pins: pinmux-i2c2-pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)\t/* (D17) uart1_rtsn.I2C2_SCL */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)\t/* (D18) uart1_ctsn.I2C2_SDA */\n-\t\t>;\n-\t};\n-\n-\tehrpwm0_pins: pinmux-ehrpwm0-pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE1)\t/* (A13) mcasp0_aclkx.ehrpwm0A */\n-\t\t>;\n-\t};\n-\n-\tehrpwm1_pins: pinmux-ehrpwm1-pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE6)\t/* (U14) gpmc_a2.ehrpwm1A */\n-\t\t>;\n-\t};\n-\n-\tmmc0_pins: pinmux-mmc0-pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)\t\t/* (C15) spi0_cs1.gpio0[6] */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4)\t\t/* (B12) mcasp0_aclkr.mmc0_sdwp */\n-\t\t>;\n-\t};\n-\n-\tspi0_pins: pinmux-spi0-pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t>;\n-\t};\n-\n-\tspi1_pins: pinmux-spi1-pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4)\t/* (C18) eCAP0_in_PWM0_out.spi1_sclk */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4)\t/* (E18) uart0_ctsn.spi1_d0 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4)\t/* (E17) uart0_rtsn.spi1_d1 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE4)\t/* (A15) xdma_event_intr0.spi1_cs1 */\n-\t\t>;\n-\t};\n-\n-\tusr_leds_pins: pinmux-usr-leds-pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)\t\t/* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)\t\t/* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7)\t\t/* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7)\t\t/* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */\n-\t\t>;\n-\t};\n-\n-\tuart0_pins: pinmux-uart0-pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n-\t\t>;\n-\t};\n-\n-\tuart4_pins: pinmux-uart4-pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)\t/* (T17) gpmc_wait0.uart4_rxd */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6)\t/* (U17) gpmc_wpn.uart4_txd */\n-\t\t>;\n-\t};\n-};\n-\n-&epwmss0 {\n-\tstatus = \"okay\";\n-};\n-\n-&ehrpwm0 {\n-\tstatus = \"okay\";\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&ehrpwm0_pins>;\n-};\n-\n-&epwmss1 {\n-\tstatus = \"okay\";\n-};\n-\n-&ehrpwm1 {\n-\tstatus = \"okay\";\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&ehrpwm1_pins>;\n-};\n-\n-&i2c0 {\n-\teeprom: eeprom@50 {\n-\t\tcompatible = \"atmel,24c256\";\n-\t\treg = <0x50>;\n-\t};\n-};\n-\n-&i2c2 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&i2c2_pins>;\n-\n-\tstatus = \"okay\";\n-\tclock-frequency = <400000>;\n-};\n-\n-&mmc1 {\n-\tstatus = \"okay\";\n-\tvmmc-supply = <&vmmcsd_fixed>;\n-\tbus-width = <4>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&mmc0_pins>;\n-\tcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;\n-};\n-\n-&rtc {\n-\tsystem-power-controller;\n-};\n-\n-&tscadc {\n-\tstatus = \"okay\";\n-\tadc {\n-\t\tti,adc-channels = <0 1 2 3 4 5 6 7>;\n-\t\tti,chan-step-avg = <16 16 16 16 16 16 16 16>;\n-\t\tti,chan-step-opendelay = <0x98 0x98 0x98 0x98 0x98 0x98 0x98 0x98>;\n-\t\tti,chan-step-sampledelay = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;\n-\t};\n-};\n-\n-&uart0 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&uart0_pins>;\n-\n-\tstatus = \"okay\";\n-};\n-\n-&uart4 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&uart4_pins>;\n-\n-\tstatus = \"okay\";\n-};\n-\n-&usb {\n-\tstatus = \"okay\";\n-};\n-\n-&usb_ctrl_mod {\n-\tstatus = \"okay\";\n-};\n-\n-&usb0_phy {\n-\tstatus = \"okay\";\n-};\n-\n-&usb0 {\n-\tstatus = \"okay\";\n-\tdr_mode = \"otg\";\n-};\n-\n-&usb1_phy {\n-\tstatus = \"okay\";\n-};\n-\n-&usb1 {\n-\tstatus = \"okay\";\n-\tdr_mode = \"host\";\n-};\n-\n-&cppi41dma  {\n-\tstatus = \"okay\";\n-};\ndiff --git a/arch/arm/dts/am335x-sancloud-bbe-common.dtsi b/arch/arm/dts/am335x-sancloud-bbe-common.dtsi\ndeleted file mode 100644\nindex 21b601fa4c127e64aba0b094bce43fe50e67f69c..0000000000000000000000000000000000000000\n--- a/arch/arm/dts/am335x-sancloud-bbe-common.dtsi\n+++ /dev/null\n@@ -1,67 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/\n- */\n-\n-&am33xx_pinmux {\n-\tcpsw_default: cpsw_default {\n-\t\tpinctrl-single,pins = <\n-\t\t\t/* Slave 1 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txen.rgmii1_tctl */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxdv.rgmii1_rctl */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd3.rgmii1_td3 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd2.rgmii1_td2 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd1.rgmii1_td1 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd0.rgmii1_td0 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txclk.rgmii1_tclk */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxclk.rgmii1_rclk */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd3.rgmii1_rd3 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd2.rgmii1_rd2 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd1.rgmii1_rd1 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd0.rgmii1_rd0 */\n-\t\t>;\n-\t};\n-\n-\tcpsw_sleep: cpsw_sleep {\n-\t\tpinctrl-single,pins = <\n-\t\t\t/* Slave 1 reset value */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n-\t\t>;\n-\t};\n-\n-\tusb_hub_ctrl: usb_hub_ctrl {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7)     /* rmii1_refclk.gpio0_29 */\n-\t\t>;\n-\t};\n-};\n-\n-&mac {\n-\tpinctrl-0 = <&cpsw_default>;\n-\tpinctrl-1 = <&cpsw_sleep>;\n-};\n-\n-&cpsw_emac0 {\n-\tphy-mode = \"rgmii-id\";\n-};\n-\n-&i2c0 {\n-\tusb2512b: usb-hub@2c {\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&usb_hub_ctrl>;\n-\t\tcompatible = \"microchip,usb2512b\";\n-\t\treg = <0x2c>;\n-\t\treset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;\n-\t};\n-};\ndiff --git a/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts\ndeleted file mode 100644\nindex 271d1ab356c8c59297279798c7d10b72ac7d687e..0000000000000000000000000000000000000000\n--- a/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts\n+++ /dev/null\n@@ -1,113 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * Copyright (C) 2021 Sancloud Ltd\n- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/\n- */\n-/dts-v1/;\n-\n-#include \"am33xx.dtsi\"\n-#include \"am335x-bone-common.dtsi\"\n-#include \"am335x-boneblack-common.dtsi\"\n-#include \"am335x-sancloud-bbe-common.dtsi\"\n-#include <dt-bindings/interrupt-controller/irq.h>\n-\n-/ {\n-\tmodel = \"SanCloud BeagleBone Enhanced Extended WiFi\";\n-\tcompatible = \"sancloud,am335x-boneenhanced\",\n-\t\t     \"ti,am335x-bone-black\",\n-\t\t     \"ti,am335x-bone\",\n-\t\t     \"ti,am33xx\";\n-\n-\twlan_en_reg: fixedregulator@2 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"wlan-en-regulator\";\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tstartup-delay-us = <100000>;\n-\t};\n-};\n-\n-&am33xx_pinmux {\n-\tmmc3_pins: pinmux_mmc3_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\t/* gpmc_a9.gpio1_25: RADIO_EN */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_OUTPUT_PULLUP, MUX_MODE7)\n-\n-\t\t\t/* gpmc_ad12.mmc2_dat0 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3)\n-\n-\t\t\t/* gpmc_ad13.mmc2_dat1 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3)\n-\n-\t\t\t/* gpmc_ad14.mmc2_dat2 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3)\n-\n-\t\t\t/* gpmc_ad15.mmc2_dat3 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3)\n-\n-\t\t\t/* gpmc_csn3.mmc2_cmd */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3)\n-\n-\t\t\t/* gpmc_clk.mmc2_clk */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3)\n-\t\t>;\n-\t};\n-\n-\tbluetooth_pins: pinmux_bluetooth_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\t/* event_intr0.gpio0_19 */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE7)\n-\t\t>;\n-\t};\n-\n-\tuart1_pins: pinmux_uart1_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\t/* uart1_rxd */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)\n-\n-\t\t\t/* uart1_txd */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0)\n-\n-\t\t\t/* uart1_ctsn */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)\n-\n-\t\t\t/* uart1_rtsn */\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n-\t\t>;\n-\t};\n-};\n-\n-&i2c2 {\n-\tstatus = \"disabled\";\n-};\n-\n-&mmc3 {\n-\tstatus = \"okay\";\n-\tvmmc-supply = <&wlan_en_reg>;\n-\tbus-width = <4>;\n-\tnon-removable;\n-\tcap-power-off-card;\n-\tti,needs-special-hs-handling;\n-\tkeep-power-in-suspend;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&mmc3_pins>;\n-\tdmas = <&edma_xbar 12 0 1\n-\t\t&edma_xbar 13 0 2>;\n-\tdma-names = \"tx\", \"rx\";\n-\tclock-frequency = <50000000>;\n-\tmax-frequency = <50000000>;\n-};\n-\n-&uart1 {\n-\tstatus = \"okay\";\n-\n-\tbluetooth {\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&uart1_pins &bluetooth_pins>;\n-\t\tcompatible = \"qcom,qca6174-bt\";\n-\t\tenable-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;\n-\t\tclocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>;\n-\t\tinterrupt-parent = <&gpio0>;\n-\t\tinterrupts = <19 IRQ_TYPE_EDGE_RISING>;\n-\t};\n-};\ndiff --git a/arch/arm/dts/am335x-sancloud-bbe-lite.dts b/arch/arm/dts/am335x-sancloud-bbe-lite.dts\ndeleted file mode 100644\nindex daa90f64a8a5ba4b623974b700f93eecdec6fffd..0000000000000000000000000000000000000000\n--- a/arch/arm/dts/am335x-sancloud-bbe-lite.dts\n+++ /dev/null\n@@ -1,50 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/\n- * Copyright (C) 2021 SanCloud Ltd\n- */\n-/dts-v1/;\n-\n-#include \"am33xx.dtsi\"\n-#include \"am335x-bone-common.dtsi\"\n-#include \"am335x-boneblack-common.dtsi\"\n-#include \"am335x-sancloud-bbe-common.dtsi\"\n-\n-/ {\n-\tmodel = \"SanCloud BeagleBone Enhanced Lite\";\n-\tcompatible = \"sancloud,am335x-boneenhanced\",\n-\t\t     \"ti,am335x-bone-black\",\n-\t\t     \"ti,am335x-bone\",\n-\t\t     \"ti,am33xx\";\n-};\n-\n-&am33xx_pinmux {\n-\tbb_spi0_pins: pinmux_bb_spi0_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0)\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE0)\n-\t\t>;\n-\t};\n-};\n-\n-&spi0 {\n-\t#address-cells = <1>;\n-\t#size-cells = <0>;\n-\n-\tstatus = \"okay\";\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&bb_spi0_pins>;\n-\n-\tchannel@0 {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\tcompatible = \"micron,spi-authenta\", \"jedec,spi-nor\";\n-\n-\t\treg = <0>;\n-\t\tspi-max-frequency = <16000000>;\n-\t\tspi-cpha;\n-\t};\n-};\ndiff --git a/arch/arm/dts/am335x-sancloud-bbe.dts b/arch/arm/dts/am335x-sancloud-bbe.dts\ndeleted file mode 100644\nindex efbe93135dbe45e716fb7abf46a8fe9583d89e14..0000000000000000000000000000000000000000\n--- a/arch/arm/dts/am335x-sancloud-bbe.dts\n+++ /dev/null\n@@ -1,53 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/\n- */\n-/dts-v1/;\n-\n-#include \"am33xx.dtsi\"\n-#include \"am335x-bone-common.dtsi\"\n-#include \"am335x-boneblack-common.dtsi\"\n-#include \"am335x-boneblack-hdmi.dtsi\"\n-#include \"am335x-sancloud-bbe-common.dtsi\"\n-#include <dt-bindings/interrupt-controller/irq.h>\n-\n-/ {\n-\tmodel = \"SanCloud BeagleBone Enhanced\";\n-\tcompatible = \"sancloud,am335x-boneenhanced\", \"ti,am335x-bone-black\", \"ti,am335x-bone\", \"ti,am33xx\";\n-};\n-\n-&am33xx_pinmux {\n-\tmpu6050_pins: pinmux_mpu6050_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE7)    /* uart0_ctsn.gpio1_8 */\n-\t\t>;\n-\t};\n-\n-\tlps3331ap_pins: pinmux_lps3331ap_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7)     /* gpmc_a10.gpio1_26 */\n-\t\t>;\n-\t};\n-};\n-\n-&i2c0 {\n-\tlps331ap: barometer@5c {\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&lps3331ap_pins>;\n-\t\tcompatible = \"st,lps331ap-press\";\n-\t\tst,drdy-int-pin = <1>;\n-\t\treg = <0x5c>;\n-\t\tinterrupt-parent = <&gpio1>;\n-\t\tinterrupts = <26 IRQ_TYPE_EDGE_RISING>;\n-\t};\n-\n-\tmpu6050: accelerometer@68 {\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&mpu6050_pins>;\n-\t\tcompatible = \"invensense,mpu6050\";\n-\t\treg = <0x68>;\n-\t\tinterrupt-parent = <&gpio0>;\n-\t\tinterrupts = <2 IRQ_TYPE_EDGE_RISING>;\n-\t\torientation = <0xff 0 0 0 1 0 0 0 0xff>;\n-\t};\n-};\n",
    "prefixes": [
        "v6",
        "14/14"
    ]
}