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GET /api/patches/2223407/?format=api
{ "id": 2223407, "url": "http://patchwork.ozlabs.org/api/patches/2223407/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260415090959.53672-2-fengchengwen@huawei.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415090959.53672-2-fengchengwen@huawei.com>", "list_archive_url": null, "date": "2026-04-15T09:09:56", "name": "[1/4] vfio/pci: Add PCIe TPH interface with capability query", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f201fa8fc45d4b5b42b4eaff4e10fa0bab1c2d0c", "submitter": { "id": 92756, "url": "http://patchwork.ozlabs.org/api/people/92756/?format=api", "name": "fengchengwen", "email": "fengchengwen@huawei.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260415090959.53672-2-fengchengwen@huawei.com/mbox/", "series": [ { "id": 499948, "url": "http://patchwork.ozlabs.org/api/series/499948/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=499948", "date": "2026-04-15T09:09:55", "name": "vfio/pci: Add PCIe TPH support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499948/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223407/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223407/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-52546-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=huawei.com header.i=@huawei.com header.a=rsa-sha256\n header.s=dkim header.b=kSC7UOJC;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; helo=sto.lore.kernel.org;\n envelope-from=linux-pci+bounces-52546-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=\"kSC7UOJC\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=113.46.200.220", "smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=huawei.com" ], "Received": [ "from sto.lore.kernel.org (sto.lore.kernel.org\n [IPv6:2600:3c09:e001:a7::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 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c=relaxed/simple;\n\tbh=eWgqyhRae6Tlm1UzbVQQnoFE594vqqD0bb/C5dP3sVg=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=YHOy3MYW+TdOSiLbHGIXL+rSYJ2GRr9t9XPKePz3krRpFJNYdHtEcsUPWfbPsp6tdnZcngk7ABC9CvrgWjTaGyi0fIpvVHnXLpRwA2zX6UmjRnoyXuQBwTtHyfWlTXaSIIxSG7j48SqiRRyihNyXWCa/P245MFJXfzPpl6BiqdE=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com;\n spf=pass smtp.mailfrom=huawei.com;\n dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=kSC7UOJC; arc=none smtp.client-ip=113.46.200.220", "dkim-signature": "v=1; a=rsa-sha256; d=huawei.com; s=dkim;\n\tc=relaxed/relaxed; q=dns/txt;\n\th=From;\n\tbh=ozwKrSsjZnb0J3eiqXz1w2jjI92OrNbLu9VFMMnKB0o=;\n\tb=kSC7UOJCEQYiN1rORu401mr371loZ7NGrhIEb9UC1RvScBNOYlKM2rutvKixFKvJk71VyVISE\n\tAnjDoD+m0Qmu5UTfmWjYT3b5FqjzA6ljR8uUlaMS8TLy66to4gJIzCXzG69ltEQRGFQ21C0Iuz3\n\tzw7qJ+yxNMWtvjuc3hM3rDU=", "From": "Chengwen Feng <fengchengwen@huawei.com>", "To": "<alex@shazbot.org>, <jgg@ziepe.ca>", "CC": "<wathsala.vithanage@arm.com>, <kvm@vger.kernel.org>,\n\t<linux-pci@vger.kernel.org>, Chengwen Feng <fengchengwen@huawei.com>", "Subject": "[PATCH 1/4] vfio/pci: Add PCIe TPH interface with capability query", "Date": "Wed, 15 Apr 2026 17:09:56 +0800", "Message-ID": "<20260415090959.53672-2-fengchengwen@huawei.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20260415090959.53672-1-fengchengwen@huawei.com>", "References": "<20260415090959.53672-1-fengchengwen@huawei.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-ClientProxiedBy": "kwepems200001.china.huawei.com (7.221.188.67) To\n kwepemk500009.china.huawei.com (7.202.194.94)" }, "content": "Add the VFIO_DEVICE_PCI_TPH IOCTL and implement the basic\ncapability query operation to let userspace discover device\nTPH support, supported modes and ST table information.\n\nSigned-off-by: Chengwen Feng <fengchengwen@huawei.com>\n---\n drivers/vfio/pci/vfio_pci_core.c | 56 ++++++++++++++++++++++++++++++++\n include/uapi/linux/vfio.h | 54 ++++++++++++++++++++++++++++++\n 2 files changed, 110 insertions(+)", "diff": "diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c\nindex d43745fe4c84..35df624439a3 100644\n--- a/drivers/vfio/pci/vfio_pci_core.c\n+++ b/drivers/vfio/pci/vfio_pci_core.c\n@@ -29,6 +29,7 @@\n #include <linux/sched/mm.h>\n #include <linux/iommufd.h>\n #include <linux/pci-p2pdma.h>\n+#include <linux/pci-tph.h>\n #if IS_ENABLED(CONFIG_EEH)\n #include <asm/eeh.h>\n #endif\n@@ -1461,6 +1462,59 @@ static int vfio_pci_ioctl_ioeventfd(struct vfio_pci_core_device *vdev,\n \t\t\t\t ioeventfd.fd);\n }\n \n+static int vfio_pci_tph_get_cap(struct vfio_pci_core_device *vdev,\n+\t\t\t\tstruct vfio_device_pci_tph_op *op,\n+\t\t\t\tvoid __user *uarg)\n+{\n+#ifdef CONFIG_PCIE_TPH\n+\tstruct pci_dev *pdev = vdev->pdev;\n+\tstruct vfio_pci_tph_cap cap = {0};\n+\tu32 reg;\n+\n+\tif (!pdev->tph_cap)\n+\t\treturn -EOPNOTSUPP;\n+\n+\tpci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CAP, ®);\n+\tif (reg & PCI_TPH_CAP_ST_NS)\n+\t\tcap.supported_modes |= VFIO_PCI_TPH_MODE_NS;\n+\tif (reg & PCI_TPH_CAP_ST_IV)\n+\t\tcap.supported_modes |= VFIO_PCI_TPH_MODE_IV;\n+\tif (reg & PCI_TPH_CAP_ST_DS)\n+\t\tcap.supported_modes |= VFIO_PCI_TPH_MODE_DS;\n+\tcap.st_table_present = !!(pcie_tph_get_st_table_loc(pdev) != PCI_TPH_LOC_NONE);\n+\tcap.st_table_sz = pcie_tph_get_st_table_size(pdev);\n+\n+\tif (copy_to_user(uarg, &cap, sizeof(cap)))\n+\t\treturn -EFAULT;\n+\n+\treturn 0;\n+#else\n+\treturn -EOPNOTSUPP;\n+#endif\n+}\n+\n+static int vfio_pci_ioctl_tph(struct vfio_pci_core_device *vdev,\n+\t\t\t void __user *uarg)\n+{\n+\tstruct vfio_device_pci_tph_op op;\n+\tsize_t minsz;\n+\n+\tif (copy_from_user(&op, uarg, sizeof(op.argsz) + sizeof(op.op)))\n+\t\treturn -EFAULT;\n+\n+\tminsz = offsetof(struct vfio_device_pci_tph_op, cap);\n+\tif (op.argsz < minsz)\n+\t\treturn -EINVAL;\n+\n+\tswitch (op.op) {\n+\tcase VFIO_PCI_TPH_GET_CAP:\n+\t\treturn vfio_pci_tph_get_cap(vdev, &op, uarg + minsz);\n+\tdefault:\n+\t\t/* Other ops are not implemented yet */\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n long vfio_pci_core_ioctl(struct vfio_device *core_vdev, unsigned int cmd,\n \t\t\t unsigned long arg)\n {\n@@ -1483,6 +1537,8 @@ long vfio_pci_core_ioctl(struct vfio_device *core_vdev, unsigned int cmd,\n \t\treturn vfio_pci_ioctl_reset(vdev, uarg);\n \tcase VFIO_DEVICE_SET_IRQS:\n \t\treturn vfio_pci_ioctl_set_irqs(vdev, uarg);\n+\tcase VFIO_DEVICE_PCI_TPH:\n+\t\treturn vfio_pci_ioctl_tph(vdev, uarg);\n \tdefault:\n \t\treturn -ENOTTY;\n \t}\ndiff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h\nindex bb7b89330d35..f3f79f43cee9 100644\n--- a/include/uapi/linux/vfio.h\n+++ b/include/uapi/linux/vfio.h\n@@ -1307,6 +1307,60 @@ struct vfio_precopy_info {\n \n #define VFIO_MIG_GET_PRECOPY_INFO _IO(VFIO_TYPE, VFIO_BASE + 21)\n \n+/* PCIe TPH capability query */\n+struct vfio_pci_tph_cap {\n+\t__u8 supported_modes;\n+#define VFIO_PCI_TPH_MODE_NS\t(1u << 0) /* No steering */\n+#define VFIO_PCI_TPH_MODE_IV\t(1u << 1) /* Interrupt vector */\n+#define VFIO_PCI_TPH_MODE_DS\t(1u << 2) /* Device specific */\n+\t__u8 st_table_present;\t/* Indicates whether ST table present */\n+\t__u16 st_table_sz;\t/* ST table size */\n+\t__u32 reserved;\n+};\n+\n+/* PCIe TPH enable control */\n+struct vfio_pci_tph_ctrl {\n+\t__u8 mode;\t/* VFIO_PCI_TPH_MODE_* */\n+\t__u8 reserved[7];\n+};\n+\n+/* PCIe TPH steer-tag single entry */\n+struct vfio_pci_tph_entry {\n+\t__u32 cpu;\t/* [IN] CPU identifier, used with get/set ops */\n+\t__u8 mem_type;\t/* [IN] Memory type, used with get/set ops */\n+#define VFIO_PCI_TPH_MEM_TYPE_VM\t0\n+#define VFIO_PCI_TPH_MEM_TYPE_PM\t1\n+\t__u8 reserved0;\n+\t__u16 index;\t/* [IN] ST table index, used with set ops */\n+\t__u16 st;\t/* [OUT] steer-tag, used with get ops */\n+\t__u16 reserved1;\n+};\n+\n+/* PCIe TPH batch steer-tags request */\n+struct vfio_pci_tph_st {\n+\t__u32 count;\n+\t__u32 reserved;\n+\tstruct vfio_pci_tph_entry ents[];\n+};\n+\n+/* IOCTL argument for VFIO_DEVICE_PCI_TPH */\n+struct vfio_device_pci_tph_op {\n+\t__u32 argsz;\n+\t__u32 op;\n+#define VFIO_PCI_TPH_GET_CAP\t0\n+#define VFIO_PCI_TPH_ENABLE\t1\n+#define VFIO_PCI_TPH_DISABLE\t2\n+#define VFIO_PCI_TPH_GET_ST\t3\n+#define VFIO_PCI_TPH_SET_ST\t4\n+\tunion {\n+\t\tstruct vfio_pci_tph_cap cap;\t/* GET_CAP: out */\n+\t\tstruct vfio_pci_tph_ctrl ctrl;\t/* ENABLE: in */\n+\t\tstruct vfio_pci_tph_st st;\t/* GET_ST/SET_ST */\n+\t};\n+};\n+\n+#define VFIO_DEVICE_PCI_TPH\t_IO(VFIO_TYPE, VFIO_BASE + 22)\n+\n /*\n * Upon VFIO_DEVICE_FEATURE_SET, allow the device to be moved into a low power\n * state with the platform-based power management. Device use of lower power\n", "prefixes": [ "1/4" ] }