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GET /api/patches/2223374/?format=api
{ "id": 2223374, "url": "http://patchwork.ozlabs.org/api/patches/2223374/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260415-ultrarisc-pcie-v3-2-73f06e972616@ultrarisc.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415-ultrarisc-pcie-v3-2-73f06e972616@ultrarisc.com>", "list_archive_url": null, "date": "2026-04-15T07:21:18", "name": "[v3,2/3] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "648e1e8123c7584e535a065a7ceab5ac0bc64a57", "submitter": { "id": 92886, "url": "http://patchwork.ozlabs.org/api/people/92886/?format=api", "name": "Jia Wang", "email": "wangjia@ultrarisc.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260415-ultrarisc-pcie-v3-2-73f06e972616@ultrarisc.com/mbox/", "series": [ { "id": 499935, "url": "http://patchwork.ozlabs.org/api/series/499935/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=499935", "date": "2026-04-15T07:21:17", "name": "riscv: Add PCIe support for UltraRISC DP1000 SoC", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/499935/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223374/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223374/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-52530-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", 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"DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=ultrarisc.com; s=dkim; h=Received:From:Date:Subject:\n\tMIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:\n\tReferences:In-Reply-To:To:Cc; bh=9RcR/I77BpXlSQN2RD71AluqcNUviDV\n\tEiKCP77YvyBA=; b=rT3j+86SlLCbHDYxYmNTCCY8AYhx5Fvq8j40Z3kDy8UepPA\n\tam2WapESx9c+8llf4tVlO5sKFpVd3Cq11Rll+Fhw1CZ9fKh4F7SkRQHc2o9x2GYe\n\tPaLHCJ83rZVOrdMiR+PxtpKjnsMYmku5jtDMRn9m590HksGS0mfCXPsSJT2I=", "From": "Jia Wang <wangjia@ultrarisc.com>", "Date": "Wed, 15 Apr 2026 15:21:18 +0800", "Subject": "[PATCH v3 2/3] dt-bindings: PCI: Add UltraRISC DP1000 PCIe\n controller", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260415-ultrarisc-pcie-v3-2-73f06e972616@ultrarisc.com>", "References": "<20260415-ultrarisc-pcie-v3-0-73f06e972616@ultrarisc.com>", "In-Reply-To": "<20260415-ultrarisc-pcie-v3-0-73f06e972616@ultrarisc.com>", "To": "Paul Walmsley <pjw@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>,\n Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alex@ghiti.fr>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>, Jingoo Han <jingoohan1@gmail.com>,\n Xincheng Zhang <zhangxincheng@ultrarisc.com>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>", "Cc": "linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,\n linux-pci@vger.kernel.org, devicetree@vger.kernel.org,\n Jia Wang <wangjia@ultrarisc.com>", "X-Mailer": "b4 0.15-dev", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1776237679; l=3909;\n i=wangjia@ultrarisc.com; s=20260309; h=from:subject:message-id;\n bh=kXanUtk0Z+qovTWMtEnCE6bIyzU1LFldyzcpZgOfTnA=;\n b=Jw/Hfu2HfAvuUQp0ma9RQfEiFSut1ef2zRJpxuX8p7ygTC8+JNjRiLYbzRhiUL1C21nSmo630\n hD9Gr0z0dJxC9P5arBz9pF1ElwdC1x6MHTqZ08d0qX2MARsI4smhJFb", "X-Developer-Key": "i=wangjia@ultrarisc.com; a=ed25519;\n pk=XvYkrelqJIIzobY7j+nIg8rsfv5kzaOzuc1UPhd087U=", "X-CM-TRANSID": "AQAAfwAnYUKdPN9poSgCAA--.1324S4", "X-Coremail-Antispam": "1UD129KBjvJXoWxZw4kZr4Utr1rAFW7XFWUurg_yoW5Kr43pF\n\tWUCFykCF4xtr13uw4fK3W0k3W5XF4vkF9YkwnFgw1UtFZ5Kw1jqrsIkw13G3W5Gr4UXry2\n\t9Fn0kw17Kw4UAw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n\t9KBjDU0xBIdaVrnRJUUUmG14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0\n\trVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2\n\tx26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0\n\tY4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2\n\t8EF7xvwVC2z280aVAFwI0_Gr0_Cr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4j6r4UJwAS\n\t0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2\n\tIY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0\n\tY48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2\n\txKxwCY1x0262kKe7AKxVW8ZVWrXwCY02Avz4vE-syl42xK82IYc2Ij64vIr41l4I8I3I0E\n\t4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGV\n\tWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_\n\tJr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwCI42IY6xAIw20EY4v20xvaj4\n\t0_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8\n\tJrUvcSsGvfC2KfnxnUUI43ZEXa7sRiy89tUUUUU==", "X-CM-SenderInfo": "pzdqwylld63zxwud2x1vfou0bp/1tbiAQASEWnfCz0AFgAAsU" }, "content": "Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.\n\nSigned-off-by: Jia Wang <wangjia@ultrarisc.com>\n---\n .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 93 ++++++++++++++++++++++\n MAINTAINERS | 7 ++\n 2 files changed, 100 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml\nnew file mode 100644\nindex 000000000000..512b935bf5d1\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml\n@@ -0,0 +1,93 @@\n+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: UltraRISC DP1000 PCIe Host Controller\n+\n+description:\n+ UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.\n+\n+maintainers:\n+ - Xincheng Zhang <zhangxincheng@ultrarisc.com>\n+ - Jia Wang <wangjia@ultrarisc.com>\n+\n+allOf:\n+ - $ref: /schemas/pci/snps,dw-pcie.yaml#\n+\n+properties:\n+ compatible:\n+ const: ultrarisc,dp1000-pcie\n+\n+ reg:\n+ items:\n+ - description: Data Bus Interface (DBI) registers.\n+ - description: PCIe configuration space region.\n+\n+ reg-names:\n+ items:\n+ - const: dbi\n+ - const: config\n+\n+ num-lanes:\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ enum: [4, 16]\n+ description: Number of lanes to use.\n+\n+ interrupts:\n+ items:\n+ - description: MSI interrupt\n+ - description: Legacy INTA interrupt\n+ - description: Legacy INTB interrupt\n+ - description: Legacy INTC interrupt\n+ - description: Legacy INTD interrupt\n+\n+ interrupt-names:\n+ items:\n+ - const: msi\n+ - const: inta\n+ - const: intb\n+ - const: intc\n+ - const: intd\n+\n+required:\n+ - compatible\n+ - reg\n+ - reg-names\n+ - interrupts\n+ - interrupt-names\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ soc {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ pcie@21000000 {\n+ compatible = \"ultrarisc,dp1000-pcie\";\n+ reg = <0x0 0x21000000 0x0 0x01000000>,\n+ <0x0 0x4fff0000 0x0 0x00010000>;\n+ reg-names = \"dbi\", \"config\";\n+ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>,\n+ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>,\n+ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>;\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+ #interrupt-cells = <1>;\n+ device_type = \"pci\";\n+ dma-coherent;\n+ bus-range = <0x0 0xff>;\n+ num-lanes = <16>;\n+ interrupt-parent = <&plic>;\n+ interrupts = <43>, <44>, <45>, <46>, <47>;\n+ interrupt-names = \"msi\", \"inta\", \"intb\", \"intc\", \"intd\";\n+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;\n+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>,\n+ <0x0 0x0 0x0 0x2 &plic 45>,\n+ <0x0 0x0 0x0 0x3 &plic 46>,\n+ <0x0 0x0 0x0 0x4 &plic 47>;\n+ };\n+ };\ndiff --git a/MAINTAINERS b/MAINTAINERS\nindex c3fe46d7c4bc..2ec02d8443dd 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -20582,6 +20582,13 @@ S:\tMaintained\n F:\tDocumentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml\n F:\tdrivers/pci/controller/plda/pcie-starfive.c\n \n+PCIE DRIVER FOR ULTRARISC DP1000\n+M:\tXincheng Zhang <zhangxincheng@ultrarisc.com>\n+M:\tJia Wang <wangjia@ultrarisc.com>\n+L:\tlinux-pci@vger.kernel.org\n+S:\tMaintained\n+F:\tDocumentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml\n+\n PCIE ENDPOINT DRIVER FOR QUALCOMM\n M:\tManivannan Sadhasivam <mani@kernel.org>\n L:\tlinux-pci@vger.kernel.org\n", "prefixes": [ "v3", "2/3" ] }