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GET /api/patches/2223367/?format=api
{ "id": 2223367, "url": "http://patchwork.ozlabs.org/api/patches/2223367/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415064838.652297-2-joel@jms.id.au/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415064838.652297-2-joel@jms.id.au>", "list_archive_url": null, "date": "2026-04-15T06:48:33", "name": "[v2,1/4] hw/riscv/boot: Describe discontiguous memory in boot_info", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2702c3381f3c9646bfe44a1315e15e50c9bc3c1a", "submitter": { "id": 48628, "url": "http://patchwork.ozlabs.org/api/people/48628/?format=api", "name": "Joel Stanley", "email": "joel@jms.id.au" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415064838.652297-2-joel@jms.id.au/mbox/", "series": [ { "id": 499931, "url": "http://patchwork.ozlabs.org/api/series/499931/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499931", "date": "2026-04-15T06:48:32", "name": "hw/riscv: Boot setup improvements", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/499931/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223367/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223367/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=nAqUKf4Q;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fwWwW6Bsrz211q\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 15 Apr 2026 16:49:46 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wCu3b-0001LK-U2; Wed, 15 Apr 2026 02:49:05 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <joel.stan@gmail.com>)\n id 1wCu3U-0001Je-93\n for qemu-devel@nongnu.org; Wed, 15 Apr 2026 02:48:56 -0400", "from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <joel.stan@gmail.com>)\n id 1wCu3S-0001gX-QF\n for qemu-devel@nongnu.org; Wed, 15 Apr 2026 02:48:56 -0400", "by mail-pl1-x630.google.com with SMTP id\n d9443c01a7336-2b4583f0a1aso20065275ad.3\n for <qemu-devel@nongnu.org>; Tue, 14 Apr 2026 23:48:54 -0700 (PDT)", "from donnager-debian.. ([45.124.203.19])\n by smtp.gmail.com with ESMTPSA id\n d9443c01a7336-2b478142565sm10353195ad.37.2026.04.14.23.48.48\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 14 Apr 2026 23:48:52 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1776235733; x=1776840533; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:sender:from:to:cc:subject:date\n :message-id:reply-to;\n bh=nxPGaHE4PCoGhoZp84fsTDqeNnYG1t2SMlGq1B2LOqo=;\n b=nAqUKf4Q1jI7cpgH0LDvFtGcTjYxYlslJm8Qi+GDRhBYsRGoQYDqOOMHIhw1aV7akL\n PPC7VLenP3q3v7F8LxRhWiohoW4ulnZ1dcc3Y1n8X8+9Xqcz57ayrdalOUQ6o32xmfNM\n 6WmcS2+q/d3E8IMU2bthQ7FHgtSn9EK2w47YvpEbKlqP+xV69HR4r+E5jmbVAE3DBhBo\n PvNfOewECB2OVeryyP3Wlx2vi8U0H+3IXzoG0rcotytiSi+7mr/cynEv0tJYP5Td6dzu\n fOdric7F9vmA3YEYeOYeu8trBooR/el/MfwQpNJejwvTfbkSUDNhfoWT/d9pTIUL0Rns\n +SWQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1776235733; x=1776840533;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:sender:x-gm-gg\n :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to;\n bh=nxPGaHE4PCoGhoZp84fsTDqeNnYG1t2SMlGq1B2LOqo=;\n b=EAyV9PsZLHGlUpkyMnhutgJePbQ2GYtde02amueuAFjjodUptZvf2eJ4watElqN6XF\n cLAzz+ld8/BudViaqq2pFhpfPUf+vq1W8BPKS5T5ghaf2qI8b1sFXQa5r4UpPGR8Aixt\n HLPSP0ZQqr59MMlt9/TgfA+31T+ue3GDDccspDMp9KEoPTQQk7nRPBzBYPBi5Rd+y9QA\n 3DWXPa7EOZpkxiM6pbGdZUwGCGeTnSRYVsMOVbN0VlwZM9Mnfgi/alu8owcyrZgGmQXD\n WmmtzqYXFAUTtfnghi9P7iOig/RZoRD0m8J6Y48qs2PpR1Uo2EeUHB3kcO75VS3asB/l\n GV8g==", "X-Forwarded-Encrypted": "i=1;\n AFNElJ+UF0lJ8pTaH6lCWegdYAgUJaT6M1aErwWGhdQMuJJNPP4TTBGPQLMtp3JbuqXtImzvKjVrcZmnPKXU@nongnu.org", "X-Gm-Message-State": "AOJu0Yy0KBvUAgMXy9m66eDHutaaRJCmkNrDSHep6I6Kp7JC+Mvb9FEK\n OKhxFnaAx3ovHs9gOTj2U1RIbyvL6dnROje4kholKyOCBsgFrGaLbnKf", "X-Gm-Gg": "AeBDieuzptvbBLsoAu6+Qt7VbnYcZnrwJrotGoA/OdpyZ+u0tFWeJZ2GuJLRzQgE+tX\n +0kP1RpoycasZNDZGrnr4MFV9tfTfb4+abLOebSuc7h3VF85yshIa9Sk7xKm7gPRFRFSrolYFdv\n W7rurjwMkiDxKkT0hqMox3nHcRbdtIBqLVpOx8wAyNJ/TH9Eq+zBX5Te3y+r40UKHmMiLPDx3L1\n WHuVEixC6ILLJhXQX0LwmugAOeqF/fLisXalKdnlN45Hh4rvinPpImdtW7HtvXZEMqFfy8XdXgE\n jsLMhJwF/+J0Hr762oNx5Jk96rKTvG8r3oS78r7SQAXSdd/zQxBYoZtBj49YgQOqES5NMOSDiIc\n Nx5i/1/R66wDp4bJbGApmtWIUh7L98vOniFkPHZpXgxQqNYbAKo31B5rvTBe3zjSiCkm9QcDrvs\n NITQzocaCN32DpRcN5YDwJeVV6VbkKV9o1R4eoLjI1KUgPHJF4bDEx0RUZ9c0BiyGhPdFvxvM81\n FtjVem5jrcNwIE4G9KuOg==", "X-Received": "by 2002:a17:902:d583:b0:2b4:689a:e420 with SMTP id\n d9443c01a7336-2b4689ae791mr74305565ad.8.1776235733289;\n Tue, 14 Apr 2026 23:48:53 -0700 (PDT)", "From": "Joel Stanley <joel@jms.id.au>", "To": "Alistair Francis <alistair.francis@wdc.com>,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n qemu-devel@nongnu.org", "Cc": "Nicholas Piggin <npiggin@gmail.com>, Weiwei Li <liwei1518@gmail.com>,\n Michael Ellerman <mpe@oss.tenstorrent.com>,\n Joel Stanley <jms@oss.tenstorrent.com>,\n Nick Piggin <npiggin@oss.tenstorrent.com>,\n Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>, qemu-riscv@nongnu.org", "Subject": "[PATCH v2 1/4] hw/riscv/boot: Describe discontiguous memory in\n boot_info", "Date": "Wed, 15 Apr 2026 16:48:33 +1000", "Message-ID": "<20260415064838.652297-2-joel@jms.id.au>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260415064838.652297-1-joel@jms.id.au>", "References": "<20260415064838.652297-1-joel@jms.id.au>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::630;\n envelope-from=joel.stan@gmail.com; helo=mail-pl1-x630.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001,\n FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Nicholas Piggin <npiggin@gmail.com>\n\nMachines that have discontiguous memory may need to adjust where\nfirmware and images are loaded at boot. Provide an interfaces for\nmachines to describe a discontiguous low/high RAM scheme for this\npurpose.\n\nSigned-off-by: Nicholas Piggin <npiggin@gmail.com>\nReviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>\nSigned-off-by: Joel Stanley <joel@jms.id.au>\n---\n include/hw/riscv/boot.h | 7 +++++++\n hw/riscv/boot.c | 11 +++++++++++\n 2 files changed, 18 insertions(+)", "diff": "diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h\nindex f00b3ca12245..115e3222174f 100644\n--- a/include/hw/riscv/boot.h\n+++ b/include/hw/riscv/boot.h\n@@ -28,6 +28,10 @@\n #define RISCV64_BIOS_BIN \"opensbi-riscv64-generic-fw_dynamic.bin\"\n \n typedef struct RISCVBootInfo {\n+ /* First contiguous RAM region. If size is zero then assume entire RAM */\n+ hwaddr ram_low_start;\n+ hwaddr ram_low_size;\n+\n ssize_t kernel_size;\n hwaddr image_low_addr;\n hwaddr image_high_addr;\n@@ -43,6 +47,9 @@ bool riscv_is_32bit(RISCVHartArrayState *harts);\n char *riscv_plic_hart_config_string(int hart_count);\n \n void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts);\n+void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info,\n+ RISCVHartArrayState *harts,\n+ hwaddr start, hwaddr size);\n vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,\n hwaddr firmware_end_addr);\n hwaddr riscv_find_and_load_firmware(MachineState *machine,\ndiff --git a/hw/riscv/boot.c b/hw/riscv/boot.c\nindex e5490beda007..9babb85b0458 100644\n--- a/hw/riscv/boot.c\n+++ b/hw/riscv/boot.c\n@@ -69,11 +69,22 @@ char *riscv_plic_hart_config_string(int hart_count)\n \n void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts)\n {\n+ info->ram_low_start = 0;\n+ info->ram_low_size = 0;\n info->kernel_size = 0;\n info->initrd_size = 0;\n info->is_32bit = riscv_is_32bit(harts);\n }\n \n+void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info,\n+ RISCVHartArrayState *harts,\n+ hwaddr start, hwaddr size)\n+{\n+ riscv_boot_info_init(info, harts);\n+ info->ram_low_start = start;\n+ info->ram_low_size = size;\n+}\n+\n vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,\n hwaddr firmware_end_addr) {\n if (info->is_32bit) {\n", "prefixes": [ "v2", "1/4" ] }