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GET /api/patches/2223209/?format=api
{ "id": 2223209, "url": "http://patchwork.ozlabs.org/api/patches/2223209/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/177618728515.4917.14466194789826252277-7@git.sr.ht/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<177618728515.4917.14466194789826252277-7@git.sr.ht>", "list_archive_url": null, "date": "2026-04-14T12:45:41", "name": "[qemu,v3,07/10] ot_uart: handle break condition", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "94f4a2cb253af5da069f5d1ce272b6efcd15b10e", "submitter": { "id": 92675, "url": "http://patchwork.ozlabs.org/api/people/92675/?format=api", "name": "~lexbaileylowrisc", "email": "lexbaileylowrisc@git.sr.ht" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/177618728515.4917.14466194789826252277-7@git.sr.ht/mbox/", "series": [ { "id": 499878, "url": "http://patchwork.ozlabs.org/api/series/499878/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499878", "date": "2026-04-14T17:21:25", "name": "Update opentitan uart (part of supporting opentitan version 1)", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/499878/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223209/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223209/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"key not found in DNS\" header.d=git.sr.ht\n header.i=@git.sr.ht header.a=rsa-sha256 header.s=20240113 header.b=Dy7/DM9q;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fwB2V2jfnz1y2d\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 15 Apr 2026 03:23:46 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wChSL-0005xE-SG; Tue, 14 Apr 2026 13:21:45 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <outgoing@sr.ht>)\n id 1wChSE-0005sW-92; Tue, 14 Apr 2026 13:21:40 -0400", "from mail-a.sr.ht ([46.23.81.152])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <outgoing@sr.ht>)\n id 1wChSB-0007Kn-Hd; Tue, 14 Apr 2026 13:21:37 -0400", "from git.sr.ht (unknown [46.23.81.155])\n by mail-a.sr.ht (Postfix) with ESMTPSA id 6F99420A3B;\n Tue, 14 Apr 2026 17:21:26 +0000 (UTC)" ], "DKIM-Signature": "a=rsa-sha256; bh=xYiqsFO1CpF379rzC+qC6atuSvv1f1B7+qpGDOgv7VA=;\n c=simple/simple; d=git.sr.ht;\n h=From:Date:Subject:Reply-to:In-Reply-To:To:Cc; q=dns/txt; s=20240113;\n t=1776187286; v=1;\n b=Dy7/DM9qouTfnwasfx6eBwfuAUQ3FuVmcT5+X2jUAPbJlTSI3fxcOw1PkhLMHpZagCgr2gX9\n jxYeHBip3456eXTdEcgyWb7xRHfGLk/w5pvQy/k3PQvLUxIEDz+6w1EsfpETwPdwDzVvIrc/oAx\n rrpuIIDZDA/CtZAasiGjsR5iYdR5ovWqlddPY7grlNGW6aZVNFmQL1FZN1/cDuhKCIH1sQF1X7i\n 9dJB7zZ9wSsymM1mhXgY+QGv5Al8BCs9R8FpDL0hAbzDTpokLUJWK0ZOi5L26HWyRBIbrYf1RGE\n V1qlgFGHP+Nr+fybeRFacXf6Lpog+rU7O7HIbg+GANA+Q==", "From": "~lexbaileylowrisc <lexbaileylowrisc@git.sr.ht>", "Date": "Tue, 14 Apr 2026 13:45:41 +0100", "Subject": "[PATCH qemu v3 07/10] ot_uart: handle break condition", "Message-ID": "<177618728515.4917.14466194789826252277-7@git.sr.ht>", "X-Mailer": "git.sr.ht", "In-Reply-To": "<177618728515.4917.14466194789826252277-0@git.sr.ht>", "To": "qemu-riscv@nongnu.org, Alistair Francis <Alistair.Francis@wdc.com>", "Cc": "Paolo Bonzini <pbonzini@redhat.com>,\n =?utf-8?q?Marc-Andr=C3=A9?= Lureau <marcandre.lureau@redhat.com>,\n Palmer Dabbelt <palmer@dabbelt.com>, Weiwei Li <liwei1518@gmail.com>,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,\n Chao Liu <chao.liu.zevorn@gmail.com>, qemu-devel@nongnu.org,\n qemu-riscv@nongnu.org, Amit Kumar-Hermosillo <amitkh@google.com>,\n nabihestefan <nabihestefan@google.com>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "Received-SPF": "pass client-ip=46.23.81.152; envelope-from=outgoing@sr.ht;\n helo=mail-a.sr.ht", "X-Spam_score_int": "0", "X-Spam_score": "-0.1", "X-Spam_bar": "/", "X-Spam_report": "(-0.1 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_03_06=1.592,\n DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Reply-To": "~lexbaileylowrisc <lex.bailey@lowrisc.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Lex Bailey <lex.bailey@lowrisc.org>\n\nThis adds a handler for the UART break event, and logic to emulate a break\nwhen oversampling is enabled and there is a break event.\n\nSigned-off-by: Lex Bailey <lex.bailey@lowrisc.org>\n---\n hw/char/ot_uart.c | 92 +++++++++++++++++++++++++++++++++++++--\n include/hw/char/ot_uart.h | 4 ++\n 2 files changed, 93 insertions(+), 3 deletions(-)", "diff": "diff --git a/hw/char/ot_uart.c b/hw/char/ot_uart.c\nindex 3511a42fbe..cdf02da62b 100644\n--- a/hw/char/ot_uart.c\n+++ b/hw/char/ot_uart.c\n@@ -179,6 +179,11 @@ static void ot_uart_receive(void *opaque, const uint8_t *buf, int size)\n uint32_t rx_watermark_level;\n size_t count = MIN(fifo8_num_free(&s->rx_fifo), (size_t)size);\n \n+ if (size && !s->toggle_break) {\n+ /* no longer breaking, so emulate idle in oversampled VAL register */\n+ s->in_break = false;\n+ }\n+\n for (int index = 0; index < size; index++) {\n fifo8_push(&s->rx_fifo, buf[index]);\n }\n@@ -331,9 +336,40 @@ static void ot_uart_reset_enter(Object *obj, ResetType type)\n \n s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;\n \n+ /*\n+ * do not reset `s->in_break`, as that tracks whether we are currently\n+ * receiving a break condition over UART RX from some device talking\n+ * to OpenTitan, which should survive resets. The QEMU CharDev only\n+ * supports transient break events and not the notion of holding the\n+ * UART in break, so remembering breaks like this is required to\n+ * support mocking of break conditions in the oversampled `VAL` reg.\n+ */\n+ if (s->in_break) {\n+ /* ignore CTRL.RXBLVL as we have no notion of break \"time\" */\n+ s->regs[R_INTR_STATE] |= INTR_RX_BREAK_ERR_MASK;\n+ }\n+\n ot_uart_update_irqs(s);\n }\n \n+static void ot_uart_event_handler(void *opaque, QEMUChrEvent event)\n+{\n+ OtUARTState *s = opaque;\n+\n+ if (event == CHR_EVENT_BREAK) {\n+ if (!s->in_break || !s->oversample_break) {\n+ /* ignore CTRL.RXBLVL as we have no notion of break \"time\" */\n+ s->regs[R_INTR_STATE] |= INTR_RX_BREAK_ERR_MASK;\n+ ot_uart_update_irqs(s);\n+ /* emulate break in the oversampled VAL register */\n+ s->in_break = true;\n+ } else if (s->toggle_break) {\n+ /* emulate toggling break off in the oversampled VAL register */\n+ s->in_break = false;\n+ }\n+ }\n+}\n+\n static uint8_t ot_uart_read_rx_fifo(OtUARTState *s)\n {\n uint8_t val;\n@@ -355,6 +391,17 @@ static uint8_t ot_uart_read_rx_fifo(OtUARTState *s)\n return val;\n }\n \n+static gboolean ot_uart_watch_cb(void *do_not_use, GIOCondition cond,\n+ void *opaque)\n+{\n+ OtUARTState *s = opaque;\n+\n+ s->watch_tag = 0;\n+ ot_uart_xmit(s);\n+\n+ return FALSE;\n+}\n+\n static uint64_t ot_uart_get_baud(OtUARTState *s)\n {\n uint64_t baud;\n@@ -424,6 +471,26 @@ static uint64_t ot_uart_read(void *opaque, hwaddr addr, unsigned int size)\n break;\n \n case R_VAL:\n+ /*\n+ * This is not trivially implemented due to the QEMU UART\n+ * interface. There is no way to reliably sample or oversample\n+ * given our emulated interface, but some software might poll the\n+ * value of this register to determine break conditions.\n+ *\n+ * As such, default to reporting 16 of the last sample received\n+ * instead. This defaults to 16 idle high samples (as a stop bit is\n+ * always the last received), except for when the `oversample-break`\n+ * property is set and a break condition is received over UART RX,\n+ * where we then show 16 low samples until the next valid UART\n+ * transmission is received (or break is toggled off with the\n+ * `toggle-break` property enabled). This will not be accurate, but\n+ * should be sufficient to support basic software flows that\n+ * essentially use UART break as a strapping mechanism.\n+ */\n+ retvalue = (s->in_break && s->oversample_break) ? 0u : UINT16_MAX;\n+ qemu_log_mask(LOG_UNIMP, \"%s: VAL only shows idle%s\\n\", __func__,\n+ (s->oversample_break ? \"/break\" : \"\"));\n+ break;\n case R_OVRD:\n case R_TIMEOUT_CTRL:\n retvalue = s->regs[reg];\n@@ -607,8 +674,27 @@ static const VMStateDescription vmstate_ot_uart = {\n \n static const Property ot_uart_properties[] = {\n DEFINE_PROP_CHR(\"chardev\", OtUARTState, chr),\n+ DEFINE_PROP_BOOL(\"oversample-break\", OtUARTState, oversample_break, false),\n+ DEFINE_PROP_BOOL(\"toggle-break\", OtUARTState, toggle_break, false),\n };\n \n+static int ot_uart_fe_change(void *opaque)\n+{\n+ OtUARTState *s = opaque;\n+\n+ qemu_chr_fe_set_handlers(&s->chr, ot_uart_can_receive, ot_uart_receive,\n+ ot_uart_event_handler, ot_uart_fe_change, s, NULL,\n+ true);\n+\n+ if (s->watch_tag > 0) {\n+ g_source_remove(s->watch_tag);\n+ s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,\n+ ot_uart_watch_cb, s);\n+ }\n+\n+ return 0;\n+}\n+\n static void ot_uart_init(Object *obj)\n {\n OtUARTState *s = OT_UART(obj);\n@@ -644,9 +730,9 @@ static void ot_uart_realize(DeviceState *dev, Error **errp)\n fifo8_create(&s->tx_fifo, OT_UART_TX_FIFO_SIZE);\n fifo8_create(&s->rx_fifo, OT_UART_RX_FIFO_SIZE);\n \n- qemu_chr_fe_set_handlers(&s->chr, ot_uart_can_receive,\n- ot_uart_receive, NULL, NULL,\n- s, NULL, true);\n+ qemu_chr_fe_set_handlers(&s->chr, ot_uart_can_receive, ot_uart_receive,\n+ ot_uart_event_handler, ot_uart_fe_change, s, NULL,\n+ true);\n }\n \n static void ot_uart_class_init(ObjectClass *klass, const void *data)\ndiff --git a/include/hw/char/ot_uart.h b/include/hw/char/ot_uart.h\nindex a2c5ff8b33..997bf2f367 100644\n--- a/include/hw/char/ot_uart.h\n+++ b/include/hw/char/ot_uart.h\n@@ -56,10 +56,14 @@ struct OtUARTState {\n Fifo8 tx_fifo;\n Fifo8 rx_fifo;\n uint32_t tx_watermark_level;\n+ bool in_break;\n+ guint watch_tag;\n \n Clock *f_clk;\n \n CharFrontend chr;\n+ bool oversample_break; /* Should mock break in the oversampled VAL reg? */\n+ bool toggle_break; /* Are incoming breaks temporary or toggled? */\n };\n \n struct OtUARTClass {\n", "prefixes": [ "qemu", "v3", "07/10" ] }