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GET /api/patches/2222972/?format=api
{ "id": 2222972, "url": "http://patchwork.ozlabs.org/api/patches/2222972/?format=api", "web_url": "http://patchwork.ozlabs.org/project/rtc-linux/patch/20260414-s2mu005-pmic-v4-6-7fe7480577e6@disroot.org/", "project": { "id": 9, "url": "http://patchwork.ozlabs.org/api/projects/9/?format=api", "name": "Linux RTC development", "link_name": "rtc-linux", "list_id": "linux-rtc.vger.kernel.org", "list_email": "linux-rtc@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260414-s2mu005-pmic-v4-6-7fe7480577e6@disroot.org>", "list_archive_url": null, "date": "2026-04-14T06:32:58", "name": "[v4,06/13] mfd: sec: add support for S2MU005 PMIC", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b0e1771b009ba086b334a839b6a9b5e8f48dc265", "submitter": { "id": 88698, "url": "http://patchwork.ozlabs.org/api/people/88698/?format=api", "name": "Kaustabh Chakraborty", "email": "kauschluss@disroot.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/rtc-linux/patch/20260414-s2mu005-pmic-v4-6-7fe7480577e6@disroot.org/mbox/", "series": [ { "id": 499781, "url": "http://patchwork.ozlabs.org/api/series/499781/?format=api", "web_url": "http://patchwork.ozlabs.org/project/rtc-linux/list/?series=499781", "date": "2026-04-14T06:32:53", "name": "Support for Samsung S2MU005 PMIC and its sub-devices", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499781/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222972/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222972/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-rtc+bounces-6322-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-rtc@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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+0200 (CEST)", "from layka.disroot.org ([127.0.0.1])\n by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP\n id ZCVmNClBUqVR; Tue, 14 Apr 2026 08:33:51 +0200 (CEST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776148436; cv=none;\n b=GNSMy0oIlsj4eoHBBLuEcFHM4I7XtZaz2gz8Ju6eKqYEi1OEcLqloeU/VGzEuXepBf3Woy2jgvT5a69DUnRI34Gh4no2Ii5SmgVZ31g38u9iupT5o2A62CuT0P/aUkEUUSsa+GkGbUOaqDnjnal8T0cAVkXtvdyx3q+Yy9Gti2Y=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776148436; c=relaxed/simple;\n\tbh=R/cwOV2hOHY83KCLt9TND1Q4L6bTF8iVTFG1Vxpsh0E=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=lJfSzU8oMXit8ZQ5gesbptbDtn57AySI/LeO0CBd82yksAb0nbVwe8hi0Ts563hMQoG5ewE9Q6pzMigI9u/8YtchrviE4v4+paAv5ho4lNeOanqAr6vBzuspWHX70We45ZZc0DexxrVjEu5X+2Vyuxlj3AGLwrg1rUbp8T16/N0=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=disroot.org;\n spf=pass smtp.mailfrom=disroot.org;\n dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org\n header.b=adQtsQRA; arc=none smtp.client-ip=178.21.23.139", "X-Virus-Scanned": "SPAM Filter at disroot.org", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail;\n\tt=1776148431; bh=R/cwOV2hOHY83KCLt9TND1Q4L6bTF8iVTFG1Vxpsh0E=;\n\th=From:Date:Subject:References:In-Reply-To:To:Cc;\n\tb=adQtsQRA0gIr9uHKzoKOxzAm5YHCz1KapiziUq0pr6W7x4dz8sdtboGol1XeVsvuV\n\t K4M7Ae1zcX3wY/JB15HOWw3mwPmHU+68Daq1RucG75Pj8ifNpYQ2xxP7kHbAp0tl51\n\t 1bj4ldAX8RoI95TNU3nkGzSdUFtm4MRu4cjRi9URMwgnVz6BqsjFND4cesMqFVSwx6\n\t AVCS1QbUUxgNRteX8m/9+zer2ScfqScYgVsHES+ZUq9BB60koOvlDE8J+pvjd8MDLV\n\t 1DHH9QbNR8dgyjJFzrMxysUT0OOAbS4FYU8LKQvd/Vqaoxjkd5A5ugnj8eKUXuHzY6\n\t Gqxr6LEUr0Ung==", "From": "Kaustabh Chakraborty <kauschluss@disroot.org>", "Date": "Tue, 14 Apr 2026 12:02:58 +0530", "Subject": "[PATCH v4 06/13] mfd: sec: add support for S2MU005 PMIC", "Precedence": "bulk", "X-Mailing-List": "linux-rtc@vger.kernel.org", "List-Id": "<linux-rtc.vger.kernel.org>", "List-Subscribe": "<mailto:linux-rtc+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-rtc+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260414-s2mu005-pmic-v4-6-7fe7480577e6@disroot.org>", "References": "<20260414-s2mu005-pmic-v4-0-7fe7480577e6@disroot.org>", "In-Reply-To": "<20260414-s2mu005-pmic-v4-0-7fe7480577e6@disroot.org>", "To": "Lee Jones <lee@kernel.org>, Pavel Machek <pavel@kernel.org>,\n Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>, MyungJoo Ham <myungjoo.ham@samsung.com>,\n Chanwoo Choi <cw00.choi@samsung.com>, Sebastian Reichel <sre@kernel.org>,\n Krzysztof Kozlowski <krzk@kernel.org>,\n =?utf-8?q?Andr=C3=A9_Draszik?= <andre.draszik@linaro.org>,\n Alexandre Belloni <alexandre.belloni@bootlin.com>,\n Jonathan Corbet <corbet@lwn.net>, Shuah Khan <skhan@linuxfoundation.org>,\n Nam Tran <trannamatk@gmail.com>,\n =?utf-8?b?xYF1a2FzeiBMZWJpZWR6acWEc2tp?= <kernel@lvkasz.us>", "Cc": "linux-leds@vger.kernel.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,\n linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org,\n linux-doc@vger.kernel.org, Kaustabh Chakraborty <kauschluss@disroot.org>" }, "content": "Samsung's S2MU005 PMIC includes subdevices for a charger, an MUIC (Micro\nUSB Interface Controller), and flash and RGB LED controllers.\n\nS2MU005's interrupt registers can be properly divided into three regmap\nIRQ chips, one each for the charger, flash LEDs, and the MUIC.\n\nAdd initial support for S2MU005 in the PMIC driver, along with it's three\ninterrupt chips.\n\nSigned-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>\n---\n drivers/mfd/sec-common.c | 16 ++\n drivers/mfd/sec-i2c.c | 29 ++++\n drivers/mfd/sec-irq.c | 74 ++++++++\n include/linux/mfd/samsung/core.h | 1 +\n include/linux/mfd/samsung/irq.h | 66 ++++++++\n include/linux/mfd/samsung/s2mu005.h | 327 ++++++++++++++++++++++++++++++++++++\n 6 files changed, 513 insertions(+)", "diff": "diff --git a/drivers/mfd/sec-common.c b/drivers/mfd/sec-common.c\nindex bd8b5f9686892..b3268516bf75e 100644\n--- a/drivers/mfd/sec-common.c\n+++ b/drivers/mfd/sec-common.c\n@@ -105,6 +105,18 @@ static const struct mfd_cell s2mpu05_devs[] = {\n \tMFD_CELL_RES(\"s2mps15-rtc\", s2mpu05_rtc_resources),\n };\n \n+static const struct resource s2mu005_muic_resources[] = {\n+\tDEFINE_RES_IRQ_NAMED(S2MU005_IRQ_MUIC_ATTACH, \"attach\"),\n+\tDEFINE_RES_IRQ_NAMED(S2MU005_IRQ_MUIC_DETACH, \"detach\"),\n+};\n+\n+static const struct mfd_cell s2mu005_devs[] = {\n+\tMFD_CELL_OF(\"s2mu005-charger\", NULL, NULL, 0, 0, \"samsung,s2mu005-charger\"),\n+\tMFD_CELL_OF(\"s2mu005-flash\", NULL, NULL, 0, 0, \"samsung,s2mu005-flash\"),\n+\tMFD_CELL_OF(\"s2mu005-muic\", s2mu005_muic_resources, NULL, 0, 0, \"samsung,s2mu005-muic\"),\n+\tMFD_CELL_OF(\"s2mu005-rgb\", NULL, NULL, 0, 0, \"samsung,s2mu005-rgb\"),\n+};\n+\n static void sec_pmic_dump_rev(struct sec_pmic_dev *sec_pmic)\n {\n \tunsigned int val;\n@@ -250,6 +262,10 @@ int sec_pmic_probe(struct device *dev, int device_type, unsigned int irq,\n \t\tsec_devs = s2mpu05_devs;\n \t\tnum_sec_devs = ARRAY_SIZE(s2mpu05_devs);\n \t\tbreak;\n+\tcase S2MU005:\n+\t\tsec_devs = s2mu005_devs;\n+\t\tnum_sec_devs = ARRAY_SIZE(s2mu005_devs);\n+\t\tbreak;\n \tdefault:\n \t\treturn dev_err_probe(sec_pmic->dev, -EINVAL,\n \t\t\t\t \"Unsupported device type %d\\n\",\ndiff --git a/drivers/mfd/sec-i2c.c b/drivers/mfd/sec-i2c.c\nindex 3132b849b4bc4..d8609886fcc80 100644\n--- a/drivers/mfd/sec-i2c.c\n+++ b/drivers/mfd/sec-i2c.c\n@@ -17,6 +17,7 @@\n #include <linux/mfd/samsung/s2mps14.h>\n #include <linux/mfd/samsung/s2mps15.h>\n #include <linux/mfd/samsung/s2mpu02.h>\n+#include <linux/mfd/samsung/s2mu005.h>\n #include <linux/mfd/samsung/s5m8767.h>\n #include <linux/mod_devicetable.h>\n #include <linux/module.h>\n@@ -66,6 +67,19 @@ static bool s2mpu02_volatile(struct device *dev, unsigned int reg)\n \t}\n }\n \n+static bool s2mu005_volatile(struct device *dev, unsigned int reg)\n+{\n+\tswitch (reg) {\n+\tcase S2MU005_REG_CHGR_INT1M:\n+\tcase S2MU005_REG_FLED_INT1M:\n+\tcase S2MU005_REG_MUIC_INT1M:\n+\tcase S2MU005_REG_MUIC_INT2M:\n+\t\treturn false;\n+\tdefault:\n+\t\treturn true;\n+\t}\n+}\n+\n static const struct regmap_config s2dos05_regmap_config = {\n \t.reg_bits = 8,\n \t.val_bits = 8,\n@@ -130,6 +144,15 @@ static const struct regmap_config s2mpu05_regmap_config = {\n \t.val_bits = 8,\n };\n \n+static const struct regmap_config s2mu005_regmap_config = {\n+\t.reg_bits = 8,\n+\t.val_bits = 8,\n+\n+\t.max_register = S2MU005_REG_MUIC_LDOADC_H,\n+\t.volatile_reg = s2mu005_volatile,\n+\t.cache_type = REGCACHE_FLAT_S,\n+};\n+\n static const struct regmap_config s5m8767_regmap_config = {\n \t.reg_bits = 8,\n \t.val_bits = 8,\n@@ -203,6 +226,11 @@ static const struct sec_pmic_i2c_platform_data s2mpu05_data = {\n \t.device_type = S2MPU05,\n };\n \n+static const struct sec_pmic_i2c_platform_data s2mu005_data = {\n+\t.regmap_cfg = &s2mu005_regmap_config,\n+\t.device_type = S2MU005,\n+};\n+\n static const struct sec_pmic_i2c_platform_data s5m8767_data = {\n \t.regmap_cfg = &s5m8767_regmap_config,\n \t.device_type = S5M8767X,\n@@ -217,6 +245,7 @@ static const struct of_device_id sec_pmic_i2c_of_match[] = {\n \t{ .compatible = \"samsung,s2mps15-pmic\", .data = &s2mps15_data, },\n \t{ .compatible = \"samsung,s2mpu02-pmic\", .data = &s2mpu02_data, },\n \t{ .compatible = \"samsung,s2mpu05-pmic\", .data = &s2mpu05_data, },\n+\t{ .compatible = \"samsung,s2mu005-pmic\", .data = &s2mu005_data, },\n \t{ .compatible = \"samsung,s5m8767-pmic\", .data = &s5m8767_data, },\n \t{ },\n };\ndiff --git a/drivers/mfd/sec-irq.c b/drivers/mfd/sec-irq.c\nindex 133188391f7c2..91a2922463fb6 100644\n--- a/drivers/mfd/sec-irq.c\n+++ b/drivers/mfd/sec-irq.c\n@@ -16,6 +16,7 @@\n #include <linux/mfd/samsung/s2mps14.h>\n #include <linux/mfd/samsung/s2mpu02.h>\n #include <linux/mfd/samsung/s2mpu05.h>\n+#include <linux/mfd/samsung/s2mu005.h>\n #include <linux/mfd/samsung/s5m8767.h>\n #include <linux/regmap.h>\n #include \"sec-core.h\"\n@@ -223,6 +224,65 @@ static const struct regmap_irq s2mpu05_irqs[] = {\n \tREGMAP_IRQ_REG(S2MPU05_IRQ_TSD, 2, S2MPU05_IRQ_TSD_MASK),\n };\n \n+static const struct regmap_irq s2mu005_irqs[] = {\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_CHGR_DETBAT, 0, S2MU005_IRQ_CHGR_DETBAT_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_CHGR_BAT, 0, S2MU005_IRQ_CHGR_BAT_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_CHGR_IVR, 0, S2MU005_IRQ_CHGR_IVR_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_CHGR_EVENT, 0, S2MU005_IRQ_CHGR_EVENT_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_CHGR_CHG, 0, S2MU005_IRQ_CHGR_CHG_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_CHGR_VMID, 0, S2MU005_IRQ_CHGR_VMID_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_CHGR_WCIN, 0, S2MU005_IRQ_CHGR_WCIN_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_CHGR_VBUS, 0, S2MU005_IRQ_CHGR_VBUS_MASK),\n+\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_FLED_LBPROT, 1, S2MU005_IRQ_FLED_LBPROT_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_FLED_OPENCH2, 1, S2MU005_IRQ_FLED_OPENCH2_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_FLED_OPENCH1, 1, S2MU005_IRQ_FLED_OPENCH1_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_FLED_SHORTCH2, 1, S2MU005_IRQ_FLED_SHORTCH2_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_FLED_SHORTCH1, 1, S2MU005_IRQ_FLED_SHORTCH1_MASK),\n+\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_MUIC_ATTACH, 2, S2MU005_IRQ_MUIC_ATTACH_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_MUIC_DETACH, 2, S2MU005_IRQ_MUIC_DETACH_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_MUIC_KP, 2, S2MU005_IRQ_MUIC_KP_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_MUIC_LKP, 2, S2MU005_IRQ_MUIC_LKP_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_MUIC_LKR, 2, S2MU005_IRQ_MUIC_LKR_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_MUIC_RIDCHG, 2, S2MU005_IRQ_MUIC_RIDCHG_MASK),\n+\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_MUIC_VBUSON, 3, S2MU005_IRQ_MUIC_VBUSON_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_MUIC_RSVD, 3, S2MU005_IRQ_MUIC_RSVD_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_MUIC_ADC, 3, S2MU005_IRQ_MUIC_ADC_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_MUIC_STUCK, 3, S2MU005_IRQ_MUIC_STUCK_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_MUIC_STUCKRCV, 3, S2MU005_IRQ_MUIC_STUCKRCV_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_MUIC_MHDL, 3, S2MU005_IRQ_MUIC_MHDL_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_MUIC_AVCHG, 3, S2MU005_IRQ_MUIC_AVCHG_MASK),\n+\tREGMAP_IRQ_REG(S2MU005_IRQ_MUIC_VBUSOFF, 3, S2MU005_IRQ_MUIC_VBUSOFF_MASK),\n+};\n+\n+static unsigned int s2mu005_irq_get_reg(struct regmap_irq_chip_data *data,\n+\t\t\t\t\tunsigned int base, int index)\n+{\n+\tconst unsigned int irqf_regs[] = {\n+\t\tS2MU005_REG_CHGR_INT1,\n+\t\tS2MU005_REG_FLED_INT1,\n+\t\tS2MU005_REG_MUIC_INT1,\n+\t\tS2MU005_REG_MUIC_INT2,\n+\t};\n+\tconst unsigned int mask_regs[] = {\n+\t\tS2MU005_REG_CHGR_INT1M,\n+\t\tS2MU005_REG_FLED_INT1M,\n+\t\tS2MU005_REG_MUIC_INT1M,\n+\t\tS2MU005_REG_MUIC_INT2M,\n+\t};\n+\n+\tswitch (base) {\n+\tcase S2MU005_REG_CHGR_INT1:\n+\t\treturn irqf_regs[index];\n+\tcase S2MU005_REG_CHGR_INT1M:\n+\t\treturn mask_regs[index];\n+\t}\n+\n+\treturn base;\n+}\n+\n static const struct regmap_irq s5m8767_irqs[] = {\n \tREGMAP_IRQ_REG(S5M8767_IRQ_PWRR, 0, S5M8767_IRQ_PWRR_MASK),\n \tREGMAP_IRQ_REG(S5M8767_IRQ_PWRF, 0, S5M8767_IRQ_PWRF_MASK),\n@@ -337,6 +397,17 @@ static const struct regmap_irq_chip s2mpu05_irq_chip = {\n \t.ack_base = S2MPU05_REG_INT1,\n };\n \n+static const struct regmap_irq_chip s2mu005_irq_chip = {\n+\t.name = \"s2mu005\",\n+\t.irqs = s2mu005_irqs,\n+\t.num_irqs = ARRAY_SIZE(s2mu005_irqs),\n+\t.num_regs = 4,\n+\t.status_base = S2MU005_REG_CHGR_INT1,\n+\t.mask_base = S2MU005_REG_CHGR_INT1M,\n+\t.ack_base = S2MU005_REG_CHGR_INT1,\n+\t.get_irq_reg = s2mu005_irq_get_reg,\n+};\n+\n static const struct regmap_irq_chip s5m8767_irq_chip = {\n \t.name = \"s5m8767\",\n \t.irqs = s5m8767_irqs,\n@@ -442,6 +513,9 @@ struct regmap_irq_chip_data *sec_irq_init(struct sec_pmic_dev *sec_pmic)\n \tcase S2MPU05:\n \t\tsec_irq_chip = &s2mpu05_irq_chip;\n \t\tbreak;\n+\tcase S2MU005:\n+\t\tsec_irq_chip = &s2mu005_irq_chip;\n+\t\tbreak;\n \tdefault:\n \t\treturn dev_err_ptr_probe(sec_pmic->dev, -EINVAL, \"Unsupported device type %d\\n\",\n \t\t\t\t\t sec_pmic->device_type);\ndiff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h\nindex 4480c631110a6..6191f409de945 100644\n--- a/include/linux/mfd/samsung/core.h\n+++ b/include/linux/mfd/samsung/core.h\n@@ -47,6 +47,7 @@ enum sec_device_type {\n \tS2MPS15X,\n \tS2MPU02,\n \tS2MPU05,\n+\tS2MU005,\n };\n \n /**\ndiff --git a/include/linux/mfd/samsung/irq.h b/include/linux/mfd/samsung/irq.h\nindex 6eab95de6fa83..19d0f0e12944f 100644\n--- a/include/linux/mfd/samsung/irq.h\n+++ b/include/linux/mfd/samsung/irq.h\n@@ -408,6 +408,72 @@ enum s2mpu05_irq {\n #define S2MPU05_IRQ_INT140C_MASK\tBIT(1)\n #define S2MPU05_IRQ_TSD_MASK\t\tBIT(2)\n \n+enum s2mu005_irq {\n+\tS2MU005_IRQ_CHGR_DETBAT,\n+\tS2MU005_IRQ_CHGR_BAT,\n+\tS2MU005_IRQ_CHGR_IVR,\n+\tS2MU005_IRQ_CHGR_EVENT,\n+\tS2MU005_IRQ_CHGR_CHG,\n+\tS2MU005_IRQ_CHGR_VMID,\n+\tS2MU005_IRQ_CHGR_WCIN,\n+\tS2MU005_IRQ_CHGR_VBUS,\n+\n+\tS2MU005_IRQ_FLED_LBPROT,\n+\tS2MU005_IRQ_FLED_OPENCH2,\n+\tS2MU005_IRQ_FLED_OPENCH1,\n+\tS2MU005_IRQ_FLED_SHORTCH2,\n+\tS2MU005_IRQ_FLED_SHORTCH1,\n+\n+\tS2MU005_IRQ_MUIC_ATTACH,\n+\tS2MU005_IRQ_MUIC_DETACH,\n+\tS2MU005_IRQ_MUIC_KP,\n+\tS2MU005_IRQ_MUIC_LKP,\n+\tS2MU005_IRQ_MUIC_LKR,\n+\tS2MU005_IRQ_MUIC_RIDCHG,\n+\n+\tS2MU005_IRQ_MUIC_VBUSON,\n+\tS2MU005_IRQ_MUIC_RSVD,\n+\tS2MU005_IRQ_MUIC_ADC,\n+\tS2MU005_IRQ_MUIC_STUCK,\n+\tS2MU005_IRQ_MUIC_STUCKRCV,\n+\tS2MU005_IRQ_MUIC_MHDL,\n+\tS2MU005_IRQ_MUIC_AVCHG,\n+\tS2MU005_IRQ_MUIC_VBUSOFF,\n+\n+\tS2MU005_IRQ_NR,\n+};\n+\n+#define S2MU005_IRQ_CHGR_DETBAT_MASK\tBIT(0)\n+#define S2MU005_IRQ_CHGR_BAT_MASK\tBIT(1)\n+#define S2MU005_IRQ_CHGR_IVR_MASK\tBIT(2)\n+#define S2MU005_IRQ_CHGR_EVENT_MASK\tBIT(3)\n+#define S2MU005_IRQ_CHGR_CHG_MASK\tBIT(4)\n+#define S2MU005_IRQ_CHGR_VMID_MASK\tBIT(5)\n+#define S2MU005_IRQ_CHGR_WCIN_MASK\tBIT(6)\n+#define S2MU005_IRQ_CHGR_VBUS_MASK\tBIT(7)\n+\n+#define S2MU005_IRQ_FLED_LBPROT_MASK\t\tBIT(2)\n+#define S2MU005_IRQ_FLED_OPENCH2_MASK\t\tBIT(4)\n+#define S2MU005_IRQ_FLED_OPENCH1_MASK\t\tBIT(5)\n+#define S2MU005_IRQ_FLED_SHORTCH2_MASK\t\tBIT(6)\n+#define S2MU005_IRQ_FLED_SHORTCH1_MASK\t\tBIT(7)\n+\n+#define S2MU005_IRQ_MUIC_ATTACH_MASK\t\tBIT(0)\n+#define S2MU005_IRQ_MUIC_DETACH_MASK\t\tBIT(1)\n+#define S2MU005_IRQ_MUIC_KP_MASK\t\tBIT(2)\n+#define S2MU005_IRQ_MUIC_LKP_MASK\t\tBIT(3)\n+#define S2MU005_IRQ_MUIC_LKR_MASK\t\tBIT(4)\n+#define S2MU005_IRQ_MUIC_RIDCHG_MASK\t\tBIT(5)\n+\n+#define S2MU005_IRQ_MUIC_VBUSON_MASK\t\tBIT(0)\n+#define S2MU005_IRQ_MUIC_RSVD_MASK\t\tBIT(1)\n+#define S2MU005_IRQ_MUIC_ADC_MASK\t\tBIT(2)\n+#define S2MU005_IRQ_MUIC_STUCK_MASK\t\tBIT(3)\n+#define S2MU005_IRQ_MUIC_STUCKRCV_MASK\t\tBIT(4)\n+#define S2MU005_IRQ_MUIC_MHDL_MASK\t\tBIT(5)\n+#define S2MU005_IRQ_MUIC_AVCHG_MASK\t\tBIT(6)\n+#define S2MU005_IRQ_MUIC_VBUSOFF_MASK\t\tBIT(7)\n+\n enum s5m8767_irq {\n \tS5M8767_IRQ_PWRR,\n \tS5M8767_IRQ_PWRF,\ndiff --git a/include/linux/mfd/samsung/s2mu005.h b/include/linux/mfd/samsung/s2mu005.h\nnew file mode 100644\nindex 0000000000000..07f4ae664950d\n--- /dev/null\n+++ b/include/linux/mfd/samsung/s2mu005.h\n@@ -0,0 +1,327 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright (c) 2015 Samsung Electronics Co., Ltd\n+ * Copyright (c) 2025 Kaustabh Chakraborty <kauschluss@disroot.org>\n+ */\n+\n+#ifndef __LINUX_MFD_S2MU005_H\n+#define __LINUX_MFD_S2MU005_H\n+\n+#include <linux/bitfield.h>\n+#include <linux/bits.h>\n+\n+/* S2MU005 registers */\n+enum s2mu005_reg {\n+\tS2MU005_REG_CHGR_INT1,\n+\tS2MU005_REG_CHGR_INT1M,\n+\n+\tS2MU005_REG_FLED_INT1,\n+\tS2MU005_REG_FLED_INT1M,\n+\n+\tS2MU005_REG_MUIC_INT1,\n+\tS2MU005_REG_MUIC_INT2,\n+\tS2MU005_REG_MUIC_INT1M,\n+\tS2MU005_REG_MUIC_INT2M,\n+\n+\tS2MU005_REG_CHGR_STATUS0,\n+\tS2MU005_REG_CHGR_STATUS1,\n+\tS2MU005_REG_CHGR_STATUS2,\n+\tS2MU005_REG_CHGR_STATUS3,\n+\tS2MU005_REG_CHGR_STATUS4,\n+\tS2MU005_REG_CHGR_STATUS5,\n+\tS2MU005_REG_CHGR_CTRL0,\n+\tS2MU005_REG_CHGR_CTRL1,\n+\tS2MU005_REG_CHGR_CTRL2,\n+\tS2MU005_REG_CHGR_CTRL3,\n+\tS2MU005_REG_CHGR_CTRL4,\n+\tS2MU005_REG_CHGR_CTRL5,\n+\tS2MU005_REG_CHGR_CTRL6,\n+\tS2MU005_REG_CHGR_CTRL7,\n+\tS2MU005_REG_CHGR_CTRL8,\n+\tS2MU005_REG_CHGR_CTRL9,\n+\tS2MU005_REG_CHGR_CTRL10,\n+\tS2MU005_REG_CHGR_CTRL11,\n+\tS2MU005_REG_CHGR_CTRL12,\n+\tS2MU005_REG_CHGR_CTRL13,\n+\tS2MU005_REG_CHGR_CTRL14,\n+\tS2MU005_REG_CHGR_CTRL15,\n+\tS2MU005_REG_CHGR_CTRL16,\n+\tS2MU005_REG_CHGR_CTRL17,\n+\tS2MU005_REG_CHGR_CTRL18,\n+\tS2MU005_REG_CHGR_CTRL19,\n+\tS2MU005_REG_CHGR_TEST0,\n+\tS2MU005_REG_CHGR_TEST1,\n+\tS2MU005_REG_CHGR_TEST2,\n+\tS2MU005_REG_CHGR_TEST3,\n+\tS2MU005_REG_CHGR_TEST4,\n+\tS2MU005_REG_CHGR_TEST5,\n+\tS2MU005_REG_CHGR_TEST6,\n+\tS2MU005_REG_CHGR_TEST7,\n+\tS2MU005_REG_CHGR_TEST8,\n+\tS2MU005_REG_CHGR_TEST9,\n+\tS2MU005_REG_CHGR_TEST10,\n+\n+\tS2MU005_REG_FLED_STATUS,\n+\tS2MU005_REG_FLED_CH0_CTRL0,\n+\tS2MU005_REG_FLED_CH0_CTRL1,\n+\tS2MU005_REG_FLED_CH0_CTRL2,\n+\tS2MU005_REG_FLED_CH0_CTRL3,\n+\tS2MU005_REG_FLED_CH1_CTRL0,\n+\tS2MU005_REG_FLED_CH1_CTRL1,\n+\tS2MU005_REG_FLED_CH1_CTRL2,\n+\tS2MU005_REG_FLED_CH1_CTRL3,\n+\tS2MU005_REG_FLED_CTRL0,\n+\tS2MU005_REG_FLED_CTRL1,\n+\tS2MU005_REG_FLED_CTRL2,\n+\tS2MU005_REG_FLED_CTRL3,\n+\tS2MU005_REG_FLED_CTRL4,\n+\tS2MU005_REG_FLED_CTRL5,\n+\tS2MU005_REG_FLED_CTRL6,\n+\n+\tS2MU005_REG_RGB_EN,\n+\tS2MU005_REG_RGB_CH0_CTRL,\n+\tS2MU005_REG_RGB_CH1_CTRL,\n+\tS2MU005_REG_RGB_CH2_CTRL,\n+\tS2MU005_REG_RGB_CH0_RAMP,\n+\tS2MU005_REG_RGB_CH0_STAY,\n+\tS2MU005_REG_RGB_CH1_RAMP,\n+\tS2MU005_REG_RGB_CH1_STAY,\n+\tS2MU005_REG_RGB_CH2_RAMP,\n+\tS2MU005_REG_RGB_CH2_STAY,\n+\tS2MU005_REG_RGB_TEST0,\n+\tS2MU005_REG_RGB_CTRL0,\n+\n+\tS2MU005_REG_MUIC_ADC,\n+\tS2MU005_REG_MUIC_DEV1,\n+\tS2MU005_REG_MUIC_DEV2,\n+\tS2MU005_REG_MUIC_DEV3,\n+\tS2MU005_REG_MUIC_BUTTON1,\n+\tS2MU005_REG_MUIC_BUTTON2,\n+\tS2MU005_REG_MUIC_RESET,\n+\tS2MU005_REG_MUIC_CHGTYPE,\n+\tS2MU005_REG_MUIC_DEVAPPLE,\n+\tS2MU005_REG_MUIC_BCDRESCAN,\n+\tS2MU005_REG_MUIC_TEST1,\n+\tS2MU005_REG_MUIC_TEST2,\n+\tS2MU005_REG_MUIC_TEST3,\n+\n+\tS2MU005_REG_ID = 0x73,\n+\n+\tS2MU005_REG_MUIC_CTRL1 = 0xb2,\n+\tS2MU005_REG_MUIC_TIMERSET1,\n+\tS2MU005_REG_MUIC_TIMERSET2,\n+\tS2MU005_REG_MUIC_SWCTRL,\n+\tS2MU005_REG_MUIC_TIMERSET3,\n+\tS2MU005_REG_MUIC_CTRL2,\n+\tS2MU005_REG_MUIC_CTRL3,\n+\n+\tS2MU005_REG_MUIC_LDOADC_L = 0xbf,\n+\tS2MU005_REG_MUIC_LDOADC_H,\n+};\n+\n+#define S2MU005_REG_FLED_CH_CTRL0(x)\t(S2MU005_REG_FLED_CH0_CTRL0 + 4 * (x))\n+#define S2MU005_REG_FLED_CH_CTRL1(x)\t(S2MU005_REG_FLED_CH0_CTRL1 + 4 * (x))\n+#define S2MU005_REG_FLED_CH_CTRL2(x)\t(S2MU005_REG_FLED_CH0_CTRL2 + 4 * (x))\n+#define S2MU005_REG_FLED_CH_CTRL3(x)\t(S2MU005_REG_FLED_CH0_CTRL3 + 4 * (x))\n+\n+#define S2MU005_REG_RGB_CH_CTRL(x)\t(S2MU005_REG_RGB_CH0_CTRL + 1 * (x))\n+#define S2MU005_REG_RGB_CH_RAMP(x)\t(S2MU005_REG_RGB_CH0_RAMP + 2 * (x))\n+#define S2MU005_REG_RGB_CH_STAY(x)\t(S2MU005_REG_RGB_CH0_STAY + 2 * (x))\n+\n+/* S2MU005_REG_CHGR_STATUS0 */\n+#define S2MU005_CHGR_VBUS\t\tBIT(7)\n+#define S2MU005_CHGR_WCIN\t\tBIT(6)\n+#define S2MU005_CHGR_VMID\t\tBIT(5)\n+#define S2MU005_CHGR_CHG\t\tBIT(4)\n+#define S2MU005_CHGR_STAT\t\tGENMASK(3, 0)\n+\n+#define S2MU005_CHGR_STAT_DONE\t\t8\n+#define S2MU005_CHGR_STAT_TOPOFF\t7\n+#define S2MU005_CHGR_STAT_DONE_FLAG\t6\n+#define S2MU005_CHGR_STAT_CV\t\t5\n+#define S2MU005_CHGR_STAT_CC\t\t4\n+#define S2MU005_CHGR_STAT_COOL_CHG\t3\n+#define S2MU005_CHGR_STAT_PRE_CHG\t2\n+\n+/* S2MU005_REG_CHGR_STATUS1 */\n+#define S2MU005_CHGR_DETBAT\t\tBIT(7)\n+#define S2MU005_CHGR_VBUS_OVP\t\tGENMASK(6, 4)\n+\n+#define S2MU005_CHGR_VBUS_OVP_OVERVOLT\t2\n+\n+/* S2MU005_REG_CHGR_STATUS2 */\n+#define S2MU005_CHGR_BAT\t\tGENMASK(6, 4)\n+\n+#define S2MU005_CHGR_BAT_VOLT_DET\t7\n+#define S2MU005_CHGR_BAT_FAST_CHG_DET\t6\n+#define S2MU005_CHGR_BAT_COOL_CHG_DET\t5\n+#define S2MU005_CHGR_BAT_LOW_CHG\t2\n+#define S2MU005_CHGR_BAT_SELF_DISCHG\t1\n+#define S2MU005_CHGR_BAT_OVP_DET\t0\n+\n+/* S2MU005_REG_CHGR_STATUS3 */\n+#define S2MU005_CHGR_EVT\t\tGENMASK(3, 0)\n+\n+#define S2MU005_CHGR_EVT_WDT_RST\t6\n+#define S2MU005_CHGR_EVT_WDT_SUSP\t5\n+#define S2MU005_CHGR_EVT_VSYS_VUVLO\t4\n+#define S2MU005_CHGR_EVT_VSYS_VOVP\t3\n+#define S2MU005_CHGR_EVT_THERM_FOLDBACK\t2\n+#define S2MU005_CHGR_EVT_THERM_SHUTDOWN\t1\n+\n+/* S2MU005_REG_CHGR_CTRL0 */\n+#define S2MU005_CHGR_CHG_EN\t\tBIT(4)\n+#define S2MU005_CHGR_OP_MODE\t\tGENMASK(2, 0)\n+\n+#define S2MU005_CHGR_OP_MODE_OTG\tBIT(2)\n+#define S2MU005_CHGR_OP_MODE_CHG\tBIT(1)\n+\n+/* S2MU005_REG_CHGR_CTRL1 */\n+#define S2MU005_CHGR_VIN_DROP\t\tGENMASK(6, 4)\n+\n+/* S2MU005_REG_CHGR_CTRL2 */\n+#define S2MU005_CHGR_IN_CURR_LIM\tGENMASK(5, 0)\n+\n+/* S2MU005_REG_CHGR_CTRL4 */\n+#define S2MU005_CHGR_OTG_OCP_ON\t\tBIT(5)\n+#define S2MU005_CHGR_OTG_OCP_OFF\tBIT(4)\n+#define S2MU005_CHGR_OTG_OCP\t\tGENMASK(3, 2)\n+\n+/* S2MU005_REG_CHGR_CTRL5 */\n+#define S2MU005_CHGR_VMID_BOOST\t\tGENMASK(4, 0)\n+\n+/* S2MU005_REG_CHGR_CTRL6 */\n+#define S2MU005_CHGR_COOL_CHG_CURR\tGENMASK(5, 0)\n+\n+/* S2MU005_REG_CHGR_CTRL7 */\n+#define S2MU005_CHGR_FAST_CHG_CURR\tGENMASK(5, 0)\n+\n+/* S2MU005_REG_CHGR_CTRL8 */\n+#define S2MU005_CHGR_VF_VBAT\t\tGENMASK(6, 1)\n+\n+/* S2MU005_REG_CHGR_CTRL10 */\n+#define S2MU005_CHGR_TOPOFF_CURR(x)\t(GENMASK(3, 0) << 4 * (x))\n+\n+/* S2MU005_REG_CHGR_CTRL11 */\n+#define S2MU005_CHGR_OSC_BOOST\t\tGENMASK(6, 5)\n+#define S2MU005_CHGR_OSC_BUCK\t\tGENMASK(4, 3)\n+\n+/* S2MU005_REG_CHGR_CTRL12 */\n+#define S2MU005_CHGR_WDT\t\tGENMASK(2, 0)\n+\n+#define S2MU005_CHGR_WDT_ON\t\tBIT(2)\n+#define S2MU005_CHGR_WDT_OFF\t\tBIT(1)\n+\n+/* S2MU005_REG_CHGR_CTRL15 */\n+#define S2MU005_CHGR_OTG_EN\t\tGENMASK(3, 2)\n+\n+/* S2MU005_REG_FLED_STATUS */\n+#define S2MU005_FLED_FLASH_STATUS(x)\t(BIT(7) >> 2 * (x))\n+#define S2MU005_FLED_TORCH_STATUS(x)\t(BIT(6) >> 2 * (x))\n+\n+/* S2MU005_REG_FLED_CHx_CTRL0 */\n+#define S2MU005_FLED_FLASH_IOUT\t\tGENMASK(3, 0)\n+\n+/* S2MU005_REG_FLED_CHx_CTRL1 */\n+#define S2MU005_FLED_TORCH_IOUT\t\tGENMASK(3, 0)\n+\n+/* S2MU005_REG_FLED_CHx_CTRL2 */\n+#define S2MU005_FLED_TORCH_TIMEOUT\tGENMASK(3, 0)\n+\n+/* S2MU005_REG_FLED_CHx_CTRL3 */\n+#define S2MU005_FLED_FLASH_TIMEOUT\tGENMASK(3, 0)\n+\n+/* S2MU005_REG_FLED_CTRL1 */\n+#define S2MU005_FLED_CH_EN\t\tBIT(7)\n+\n+/*\n+ * S2MU005_REG_FLED_CTRL4 - Rev. EVT0\n+ * S2MU005_REG_FLED_CTRL6 - Rev. EVT1 and later\n+ */\n+#define S2MU005_FLED_FLASH_EN(x)\t(GENMASK(7, 6) >> 4 * (x))\n+#define S2MU005_FLED_TORCH_EN(x)\t(GENMASK(5, 4) >> 4 * (x))\n+\n+/* S2MU005_REG_RGB_EN */\n+#define S2MU005_RGB_RESET\t\tBIT(6)\n+#define S2MU005_RGB_SLOPE\t\tGENMASK(5, 0)\n+\n+#define S2MU005_RGB_SLOPE_CONST\t\t(BIT(4) | BIT(2) | BIT(0))\n+#define S2MU005_RGB_SLOPE_SMOOTH\t(BIT(5) | BIT(3) | BIT(1))\n+\n+/* S2MU005_REG_RGB_CHx_RAMP */\n+#define S2MU005_RGB_CH_RAMP_UP\t\tGENMASK(7, 4)\n+#define S2MU005_RGB_CH_RAMP_DN\t\tGENMASK(3, 0)\n+\n+/* S2MU005_REG_RGB_CHx_STAY */\n+#define S2MU005_RGB_CH_STAY_HI\t\tGENMASK(7, 4)\n+#define S2MU005_RGB_CH_STAY_LO\t\tGENMASK(3, 0)\n+\n+/* S2MU005_REG_MUIC_DEV1 */\n+#define S2MU005_MUIC_OTG\t\tBIT(7)\n+#define S2MU005_MUIC_DCP\t\tBIT(6)\n+#define S2MU005_MUIC_CDP\t\tBIT(5)\n+#define S2MU005_MUIC_T1_T2_CHG\t\tBIT(4)\n+#define S2MU005_MUIC_UART\t\tBIT(3)\n+#define S2MU005_MUIC_SDP\t\tBIT(2)\n+#define S2MU005_MUIC_LANHUB\t\tBIT(1)\n+#define S2MU005_MUIC_AUDIO\t\tBIT(0)\n+\n+/* S2MU005_REG_MUIC_DEV2 */\n+#define S2MU005_MUIC_SDP_1P8S\t\tBIT(7)\n+#define S2MU005_MUIC_AV\t\t\tBIT(6)\n+#define S2MU005_MUIC_TTY\t\tBIT(5)\n+#define S2MU005_MUIC_PPD\t\tBIT(4)\n+#define S2MU005_MUIC_JIG_UART_OFF\tBIT(3)\n+#define S2MU005_MUIC_JIG_UART_ON\tBIT(2)\n+#define S2MU005_MUIC_JIG_USB_OFF\tBIT(1)\n+#define S2MU005_MUIC_JIG_USB_ON\t\tBIT(0)\n+\n+/* S2MU005_REG_MUIC_DEV3 */\n+#define S2MU005_MUIC_U200_CHG\t\tBIT(7)\n+#define S2MU005_MUIC_VBUS_AV\t\tBIT(4)\n+#define S2MU005_MUIC_VBUS_R255\t\tBIT(1)\n+#define S2MU005_MUIC_MHL\t\tBIT(0)\n+\n+/* S2MU005_REG_MUIC_DEVAPPLE */\n+#define S2MU005_MUIC_APPLE_CHG_0P5A\tBIT(7)\n+#define S2MU005_MUIC_APPLE_CHG_1P0A\tBIT(6)\n+#define S2MU005_MUIC_APPLE_CHG_2P0A\tBIT(5)\n+#define S2MU005_MUIC_APPLE_CHG_2P4A\tBIT(4)\n+#define S2MU005_MUIC_SDP_DCD_OUT\tBIT(3)\n+#define S2MU005_MUIC_RID_WAKEUP\t\tBIT(2)\n+#define S2MU005_MUIC_VBUS_WAKEUP\tBIT(1)\n+#define S2MU005_MUIC_BCV1P2_OR_OPEN\tBIT(0)\n+\n+/* S2MU005_REG_ID */\n+#define S2MU005_ID_MASK\t\t\tGENMASK(3, 0)\n+\n+/* S2MU005_REG_MUIC_SWCTRL */\n+#define S2MU005_MUIC_DM_DP\t\tGENMASK(7, 2)\n+#define S2MU005_MUIC_JIG\t\tBIT(0)\n+\n+#define S2MU005_MUIC_DM_DP_UART\t\t0x12\n+#define S2MU005_MUIC_DM_DP_USB\t\t0x09\n+\n+/* S2MU005_REG_MUIC_CTRL1 */\n+#define S2MU005_MUIC_OPEN\t\tBIT(4)\n+#define S2MU005_MUIC_RAW_DATA\t\tBIT(3)\n+#define S2MU005_MUIC_MAN_SW\t\tBIT(2)\n+#define S2MU005_MUIC_WAIT\t\tBIT(1)\n+#define S2MU005_MUIC_IRQ\t\tBIT(0)\n+\n+/* S2MU005_REG_MUIC_CTRL3 */\n+#define S2MU005_MUIC_ONESHOT_ADC\tBIT(2)\n+\n+/* S2MU005_REG_MUIC_LDOADC_L and S2MU005_REG_MUIC_LDOADC_H */\n+#define S2MU005_MUIC_VSET\t\tGENMASK(4, 0)\n+\n+#define S2MU005_MUIC_VSET_3P0V\t\t0x1f\n+#define S2MU005_MUIC_VSET_2P6V\t\t0x0e\n+#define S2MU005_MUIC_VSET_2P4V\t\t0x0c\n+#define S2MU005_MUIC_VSET_2P2V\t\t0x0a\n+#define S2MU005_MUIC_VSET_2P0V\t\t0x08\n+#define S2MU005_MUIC_VSET_1P5V\t\t0x03\n+#define S2MU005_MUIC_VSET_1P4V\t\t0x02\n+#define S2MU005_MUIC_VSET_1P2V\t\t0x00\n+\n+#endif /* __LINUX_MFD_S2MU005_H */\n", "prefixes": [ "v4", "06/13" ] }