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GET /api/patches/2222806/?format=api
{ "id": 2222806, "url": "http://patchwork.ozlabs.org/api/patches/2222806/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413182456.811543-3-prabhakar.mahadev-lad.rj@bp.renesas.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260413182456.811543-3-prabhakar.mahadev-lad.rj@bp.renesas.com>", "list_archive_url": null, "date": "2026-04-13T18:24:52", "name": "[v2,2/5] pinctrl: renesas: rzg2l: Add SR register cache for PM suspend/resume", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1155a704bd3d275d3bdd878d49c9ae303d247c9e", "submitter": { "id": 9539, "url": "http://patchwork.ozlabs.org/api/people/9539/?format=api", "name": "Prabhakar", "email": "prabhakar.csengg@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413182456.811543-3-prabhakar.mahadev-lad.rj@bp.renesas.com/mbox/", "series": [ { "id": 499739, "url": "http://patchwork.ozlabs.org/api/series/499739/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499739", "date": "2026-04-13T18:24:51", "name": "pinctrl: renesas: rzg2l: Fix PM register caching", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/499739/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222806/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222806/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-35125-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], 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2002:a05:600c:8907:b0:488:ab1d:dcc5 with SMTP id\n 5b1f17b1804b1-488d6ac1bafmr127735555e9.27.1776104707704;\n Mon, 13 Apr 2026 11:25:07 -0700 (PDT)", "From": "Prabhakar <prabhakar.csengg@gmail.com>", "X-Google-Original-From": "Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>", "To": "Geert Uytterhoeven <geert+renesas@glider.be>,\n\tLinus Walleij <linusw@kernel.org>", "Cc": "linux-renesas-soc@vger.kernel.org,\n\tlinux-gpio@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tPrabhakar <prabhakar.csengg@gmail.com>,\n\tBiju Das <biju.das.jz@bp.renesas.com>,\n\tFabrizio Castro <fabrizio.castro.jz@renesas.com>,\n\tLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>", "Subject": "[PATCH v2 2/5] pinctrl: renesas: rzg2l: Add SR register cache for PM\n suspend/resume", "Date": "Mon, 13 Apr 2026 19:24:52 +0100", "Message-ID": "<20260413182456.811543-3-prabhakar.mahadev-lad.rj@bp.renesas.com>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260413182456.811543-1-prabhakar.mahadev-lad.rj@bp.renesas.com>", "References": "<20260413182456.811543-1-prabhakar.mahadev-lad.rj@bp.renesas.com>", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>\n\nInclude the SR (Slew Rate) register in the PM suspend/resume register\ncache.\n\nSigned-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>\n---\nv1->v2:\n- Added dedicated cache for SR registers.\n---\n drivers/pinctrl/renesas/pinctrl-rzg2l.c | 38 +++++++++++++++++++++++--\n 1 file changed, 35 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\nindex 5722cd4c581d..1e8f631fcb66 100644\n--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n@@ -322,6 +322,7 @@ struct rzg2l_pinctrl_pin_settings {\n * @pupd: PUPD registers cache\n * @ien: IEN registers cache\n * @smt: SMT registers cache\n+ * @sr: SR registers cache\n * @sd_ch: SD_CH registers cache\n * @eth_poc: ET_POC registers cache\n * @oen: Output Enable register cache\n@@ -336,6 +337,7 @@ struct rzg2l_pinctrl_reg_cache {\n \tu32\t*ien[2];\n \tu32\t*pupd[2];\n \tu32\t*smt[2];\n+\tu32\t*sr[2];\n \tu8\tsd_ch[2];\n \tu8\teth_poc[2];\n \tu8\toen;\n@@ -2760,6 +2762,11 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)\n \t\tif (!cache->smt[i])\n \t\t\treturn -ENOMEM;\n \n+\t\tcache->sr[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->sr[i]),\n+\t\t\t\t\t GFP_KERNEL);\n+\t\tif (!cache->sr[i])\n+\t\t\treturn -ENOMEM;\n+\n \t\t/* Allocate dedicated cache. */\n \t\tdedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,\n \t\t\t\t\t\t\tsizeof(*dedicated_cache->iolh[i]),\n@@ -2772,6 +2779,12 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)\n \t\t\t\t\t\t GFP_KERNEL);\n \t\tif (!dedicated_cache->ien[i])\n \t\t\treturn -ENOMEM;\n+\n+\t\tdedicated_cache->sr[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,\n+\t\t\t\t\t\t sizeof(*dedicated_cache->sr[i]),\n+\t\t\t\t\t\t GFP_KERNEL);\n+\t\tif (!dedicated_cache->sr[i])\n+\t\t\treturn -ENOMEM;\n \t}\n \n \tpctrl->cache = cache;\n@@ -3003,7 +3016,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen\n \tstruct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;\n \n \tfor (u32 port = 0; port < nports; port++) {\n-\t\tbool has_iolh, has_ien, has_pupd, has_smt;\n+\t\tbool has_iolh, has_ien, has_pupd, has_smt, has_sr;\n \t\tu32 off, caps;\n \t\tu8 pincnt;\n \t\tu64 cfg;\n@@ -3024,6 +3037,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen\n \t\thas_ien = !!(caps & PIN_CFG_IEN);\n \t\thas_pupd = !!(caps & PIN_CFG_PUPD);\n \t\thas_smt = !!(caps & PIN_CFG_SMT);\n+\t\thas_sr = !!(caps & PIN_CFG_SR);\n \n \t\tif (suspend)\n \t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]);\n@@ -3075,6 +3089,15 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen\n \t\t\t\t\t\t\t cache->smt[1][port]);\n \t\t\t}\n \t\t}\n+\n+\t\tif (has_sr) {\n+\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off),\n+\t\t\t\t\t\t cache->sr[0][port]);\n+\t\t\tif (pincnt >= 4) {\n+\t\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off) + 4,\n+\t\t\t\t\t\t\t cache->sr[1][port]);\n+\t\t\t}\n+\t\t}\n \t}\n }\n \n@@ -3089,7 +3112,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b\n \t * port offset are close together.\n \t */\n \tfor (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) {\n-\t\tbool has_iolh, has_ien;\n+\t\tbool has_iolh, has_ien, has_sr;\n \t\tu32 off, next_off = 0;\n \t\tu64 cfg, next_cfg;\n \t\tu8 pincnt;\n@@ -3110,6 +3133,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b\n \t\t/* And apply them in a single shot. */\n \t\thas_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));\n \t\thas_ien = !!(caps & PIN_CFG_IEN);\n+\t\thas_sr = !!(caps & PIN_CFG_SR);\n \t\tpincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg));\n \n \t\tif (has_iolh) {\n@@ -3120,7 +3144,10 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b\n \t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off),\n \t\t\t\t\t\t cache->ien[0][i]);\n \t\t}\n-\n+\t\tif (has_sr) {\n+\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off),\n+\t\t\t\t\t\t cache->sr[0][i]);\n+\t\t}\n \t\tif (pincnt >= 4) {\n \t\t\tif (has_iolh) {\n \t\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend,\n@@ -3132,6 +3159,11 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b\n \t\t\t\t\t\t\t pctrl->base + IEN(off) + 4,\n \t\t\t\t\t\t\t cache->ien[1][i]);\n \t\t\t}\n+\t\t\tif (has_sr) {\n+\t\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend,\n+\t\t\t\t\t\t\t pctrl->base + SR(off) + 4,\n+\t\t\t\t\t\t\t cache->sr[1][i]);\n+\t\t\t}\n \t\t}\n \t\tcaps = 0;\n \t}\n", "prefixes": [ "v2", "2/5" ] }