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GET /api/patches/2222618/?format=api
{ "id": 2222618, "url": "http://patchwork.ozlabs.org/api/patches/2222618/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413073737.986219-13-gaurav.sharma_7@nxp.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260413073737.986219-13-gaurav.sharma_7@nxp.com>", "list_archive_url": null, "date": "2026-04-13T07:37:34", "name": "[PATCHv5,12/15] hw/arm/fsl-imx8mm: Adding support for General Purpose Timers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6b651f2aaf199c14ef1d45caaa840aec61793891", "submitter": { "id": 92057, "url": "http://patchwork.ozlabs.org/api/people/92057/?format=api", "name": "Gaurav Sharma", "email": "gaurav.sharma_7@nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413073737.986219-13-gaurav.sharma_7@nxp.com/mbox/", "series": [ { "id": 499658, "url": "http://patchwork.ozlabs.org/api/series/499658/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499658", "date": "2026-04-13T07:37:27", "name": "Adding comprehensive support for i.MX8MM EVK board", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499658/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222618/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222618/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvK6h1PRvz1yDF\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 13 Apr 2026 17:39:24 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wCBsG-000767-2i; Mon, 13 Apr 2026 03:38:24 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <gaurav.sharma_7@nxp.com>)\n id 1wCBrz-0006xb-Lm\n for qemu-devel@nongnu.org; Mon, 13 Apr 2026 03:38:08 -0400", "from inva020.nxp.com ([92.121.34.13])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <gaurav.sharma_7@nxp.com>)\n id 1wCBrv-0005e0-PN\n for qemu-devel@nongnu.org; Mon, 13 Apr 2026 03:38:06 -0400", "from inva020.nxp.com (localhost [127.0.0.1])\n by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id D83261A159F;\n Mon, 13 Apr 2026 09:37:45 +0200 (CEST)", "from aprdc01srsp001v.ap-rdc01.nxp.com\n (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16])\n by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id A30C71A1598;\n Mon, 13 Apr 2026 09:37:45 +0200 (CEST)", "from lsv031015.swis.in-blr01.nxp.com\n (lsv031015.swis.in-blr01.nxp.com [10.12.177.77])\n by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 2502E18000A4;\n Mon, 13 Apr 2026 15:37:45 +0800 (+08)" ], "From": "Gaurav Sharma <gaurav.sharma_7@nxp.com>", "To": "qemu-devel@nongnu.org", "Cc": "pbonzini@redhat.com, peter.maydell@linaro.org,\n Gaurav Sharma <gaurav.sharma_7@nxp.com>", "Subject": "[PATCHv5 12/15] hw/arm/fsl-imx8mm: Adding support for General Purpose\n Timers", "Date": "Mon, 13 Apr 2026 13:07:34 +0530", "Message-Id": "<20260413073737.986219-13-gaurav.sharma_7@nxp.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260413073737.986219-1-gaurav.sharma_7@nxp.com>", "References": "<20260413073737.986219-1-gaurav.sharma_7@nxp.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Virus-Scanned": "ClamAV using ClamSMTP", "Received-SPF": "pass client-ip=92.121.34.13;\n envelope-from=gaurav.sharma_7@nxp.com; helo=inva020.nxp.com", "X-Spam_score_int": "-41", "X-Spam_score": "-4.2", "X-Spam_bar": "----", "X-Spam_report": "(-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "It enables emulation of GPT in iMX8MM\nAdded GPT IRQ lines\n\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nSigned-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com>\n---\n hw/arm/Kconfig | 1 +\n hw/arm/fsl-imx8mm.c | 56 ++++++++++++++++++++++++++++++++++++-\n hw/timer/imx_gpt.c | 26 +++++++++++++++++\n include/hw/arm/fsl-imx8mm.h | 11 ++++++++\n include/hw/timer/imx_gpt.h | 2 ++\n 5 files changed, 95 insertions(+), 1 deletion(-)", "diff": "diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex b757557ac7..f84bf725be 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -635,6 +635,7 @@ config FSL_IMX8MM\n select FSL_IMX8MP_CCM\n select IMX\n select IMX_I2C\n+ select OR_IRQ\n select SDHCI\n select PCI_EXPRESS_DESIGNWARE\n select PCI_EXPRESS_FSL_IMX8M_PHY\ndiff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c\nindex a61ccbfdee..613996cfec 100644\n--- a/hw/arm/fsl-imx8mm.c\n+++ b/hw/arm/fsl-imx8mm.c\n@@ -180,6 +180,13 @@ static void fsl_imx8mm_init(Object *obj)\n object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);\n }\n \n+ for (i = 0; i < FSL_IMX8MM_NUM_GPTS; i++) {\n+ g_autofree char *name = g_strdup_printf(\"gpt%d\", i + 1);\n+ object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX8MM_GPT);\n+ }\n+ object_initialize_child(obj, \"gpt5-gpt6-irq\", &s->gpt5_gpt6_irq,\n+ TYPE_OR_IRQ);\n+\n for (i = 0; i < FSL_IMX8MM_NUM_I2CS; i++) {\n g_autofree char *name = g_strdup_printf(\"i2c%d\", i + 1);\n object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);\n@@ -385,6 +392,52 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n fsl_imx8mm_memmap[FSL_IMX8MM_OCRAM].addr,\n &s->ocram);\n \n+ /* GPTs */\n+ object_property_set_int(OBJECT(&s->gpt5_gpt6_irq), \"num-lines\", 2,\n+ &error_abort);\n+ if (!qdev_realize(DEVICE(&s->gpt5_gpt6_irq), NULL, errp)) {\n+ return;\n+ }\n+\n+ qdev_connect_gpio_out(DEVICE(&s->gpt5_gpt6_irq), 0,\n+ qdev_get_gpio_in(gicdev, FSL_IMX8MM_GPT5_GPT6_IRQ));\n+\n+ for (i = 0; i < FSL_IMX8MM_NUM_GPTS; i++) {\n+ hwaddr gpt_addrs[FSL_IMX8MM_NUM_GPTS] = {\n+ fsl_imx8mm_memmap[FSL_IMX8MM_GPT1].addr,\n+ fsl_imx8mm_memmap[FSL_IMX8MM_GPT2].addr,\n+ fsl_imx8mm_memmap[FSL_IMX8MM_GPT3].addr,\n+ fsl_imx8mm_memmap[FSL_IMX8MM_GPT4].addr,\n+ fsl_imx8mm_memmap[FSL_IMX8MM_GPT5].addr,\n+ fsl_imx8mm_memmap[FSL_IMX8MM_GPT6].addr,\n+ };\n+\n+ s->gpt[i].ccm = IMX_CCM(&s->ccm);\n+\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), errp)) {\n+ return;\n+ }\n+\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_addrs[i]);\n+\n+ if (i < FSL_IMX8MM_NUM_GPTS - 2) {\n+ static const unsigned int gpt_irqs[FSL_IMX8MM_NUM_GPTS - 2] = {\n+ FSL_IMX8MM_GPT1_IRQ,\n+ FSL_IMX8MM_GPT2_IRQ,\n+ FSL_IMX8MM_GPT3_IRQ,\n+ FSL_IMX8MM_GPT4_IRQ,\n+ };\n+\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,\n+ qdev_get_gpio_in(gicdev, gpt_irqs[i]));\n+ } else {\n+ int irq = i - FSL_IMX8MM_NUM_GPTS + 2;\n+\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,\n+ qdev_get_gpio_in(DEVICE(&s->gpt5_gpt6_irq), irq));\n+ }\n+ }\n+\n /* I2Cs */\n for (i = 0; i < FSL_IMX8MM_NUM_I2CS; i++) {\n static const struct {\n@@ -555,7 +608,8 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n case FSL_IMX8MM_GIC_DIST:\n case FSL_IMX8MM_GIC_REDIST:\n case FSL_IMX8MM_GPIO1 ... FSL_IMX8MM_GPIO5:\n- case FSL_IMX8MM_ECSPI1 ... FSL_IMX8MM_ECSPI3:\n+ case FSL_IMX8MM_GPT1 ... FSL_IMX8MM_GPT6:\n+\tcase FSL_IMX8MM_ECSPI1 ... FSL_IMX8MM_ECSPI3:\n case FSL_IMX8MM_I2C1 ... FSL_IMX8MM_I2C4:\n case FSL_IMX8MM_PCIE1:\n case FSL_IMX8MM_PCIE_PHY1:\ndiff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c\nindex 8c7cbfdeac..5eba637f7d 100644\n--- a/hw/timer/imx_gpt.c\n+++ b/hw/timer/imx_gpt.c\n@@ -6,6 +6,7 @@\n * Originally written by Hans Jiang\n * Updated by Peter Chubb\n * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>\n+ * Updated by Gaurav Sharma <gaurav.sharma_7@nxp.com>\n *\n * This code is licensed under GPL version 2 or later. See\n * the COPYING file in the top-level directory.\n@@ -137,6 +138,17 @@ static const IMXClk imx8mp_gpt_clocks[] = {\n CLK_NONE, /* 111 not defined */\n };\n \n+static const IMXClk imx8mm_gpt_clocks[] = {\n+ CLK_NONE, /* 000 No clock source */\n+ CLK_IPG, /* 001 ipg_clk, 532MHz */\n+ CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */\n+ CLK_EXT, /* 011 External clock */\n+ CLK_32k, /* 100 ipg_clk_32k */\n+ CLK_HIGH, /* 101 ipg_clk_16M */\n+ CLK_NONE, /* 110 not defined */\n+ CLK_NONE, /* 111 not defined */\n+};\n+\n /* Must be called from within ptimer_transaction_begin/commit block */\n static void imx_gpt_set_freq(IMXGPTState *s)\n {\n@@ -570,6 +582,13 @@ static void imx8mp_gpt_init(Object *obj)\n s->clocks = imx8mp_gpt_clocks;\n }\n \n+static void imx8mm_gpt_init(Object *obj)\n+{\n+ IMXGPTState *s = IMX_GPT(obj);\n+\n+ s->clocks = imx8mm_gpt_clocks;\n+}\n+\n static const TypeInfo imx25_gpt_info = {\n .name = TYPE_IMX25_GPT,\n .parent = TYPE_SYS_BUS_DEVICE,\n@@ -608,6 +627,12 @@ static const TypeInfo imx8mp_gpt_info = {\n .instance_init = imx8mp_gpt_init,\n };\n \n+static const TypeInfo imx8mm_gpt_info = {\n+ .name = TYPE_IMX8MM_GPT,\n+ .parent = TYPE_IMX25_GPT,\n+ .instance_init = imx8mm_gpt_init,\n+};\n+\n static void imx_gpt_register_types(void)\n {\n type_register_static(&imx25_gpt_info);\n@@ -616,6 +641,7 @@ static void imx_gpt_register_types(void)\n type_register_static(&imx6ul_gpt_info);\n type_register_static(&imx7_gpt_info);\n type_register_static(&imx8mp_gpt_info);\n+ type_register_static(&imx8mm_gpt_info);\n }\n \n type_init(imx_gpt_register_types)\ndiff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h\nindex fd62b19a87..607ac86666 100644\n--- a/include/hw/arm/fsl-imx8mm.h\n+++ b/include/hw/arm/fsl-imx8mm.h\n@@ -18,10 +18,12 @@\n #include \"hw/misc/imx7_snvs.h\"\n #include \"hw/misc/imx8mp_analog.h\"\n #include \"hw/misc/imx8mp_ccm.h\"\n+#include \"hw/or-irq.h\"\n #include \"hw/pci-host/designware.h\"\n #include \"hw/pci-host/fsl_imx8m_phy.h\"\n #include \"hw/sd/sdhci.h\"\n #include \"hw/ssi/imx_spi.h\"\n+#include \"hw/timer/imx_gpt.h\"\n #include \"hw/watchdog/wdt_imx2.h\"\n #include \"qom/object.h\"\n #include \"qemu/units.h\"\n@@ -36,6 +38,7 @@ enum FslImx8mmConfiguration {\n FSL_IMX8MM_NUM_CPUS = 4,\n FSL_IMX8MM_NUM_ECSPIS = 3,\n FSL_IMX8MM_NUM_GPIOS = 5,\n+ FSL_IMX8MM_NUM_GPTS = 6,\n FSL_IMX8MM_NUM_I2CS = 4,\n FSL_IMX8MM_NUM_IRQS = 128,\n FSL_IMX8MM_NUM_UARTS = 4,\n@@ -48,6 +51,7 @@ struct FslImx8mmState {\n \n ARMCPU cpu[FSL_IMX8MM_NUM_CPUS];\n GICv3State gic;\n+ IMXGPTState gpt[FSL_IMX8MM_NUM_GPTS];\n IMXGPIOState gpio[FSL_IMX8MM_NUM_GPIOS];\n IMX8MPCCMState ccm;\n IMX8MPAnalogState analog;\n@@ -60,6 +64,7 @@ struct FslImx8mmState {\n IMX2WdtState wdt[FSL_IMX8MM_NUM_WDTS];\n DesignwarePCIEHost pcie;\n FslImx8mPciePhyState pcie_phy;\n+ OrIRQState gpt5_gpt6_irq;\n };\n \n enum FslImx8mmMemoryRegions {\n@@ -192,6 +197,12 @@ enum FslImx8mmIrqs {\n FSL_IMX8MM_I2C3_IRQ = 37,\n FSL_IMX8MM_I2C4_IRQ = 38,\n \n+ FSL_IMX8MM_GPT1_IRQ = 55,\n+ FSL_IMX8MM_GPT2_IRQ = 54,\n+ FSL_IMX8MM_GPT3_IRQ = 53,\n+ FSL_IMX8MM_GPT4_IRQ = 52,\n+ FSL_IMX8MM_GPT5_GPT6_IRQ = 51,\n+\n FSL_IMX8MM_GPIO1_LOW_IRQ = 64,\n FSL_IMX8MM_GPIO1_HIGH_IRQ = 65,\n FSL_IMX8MM_GPIO2_LOW_IRQ = 66,\ndiff --git a/include/hw/timer/imx_gpt.h b/include/hw/timer/imx_gpt.h\nindex 5488f7e4df..379ee5de75 100644\n--- a/include/hw/timer/imx_gpt.h\n+++ b/include/hw/timer/imx_gpt.h\n@@ -6,6 +6,7 @@\n * Originally written by Hans Jiang\n * Updated by Peter Chubb\n * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>\n+ * Updated by Gaurav Sharma <gaurav.sharma_7@nxp.com>\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n@@ -81,6 +82,7 @@\n #define TYPE_IMX6UL_GPT \"imx6ul.gpt\"\n #define TYPE_IMX7_GPT \"imx7.gpt\"\n #define TYPE_IMX8MP_GPT \"imx8mp.gpt\"\n+#define TYPE_IMX8MM_GPT \"imx8mm.gpt\"\n \n #define TYPE_IMX_GPT TYPE_IMX25_GPT\n \n", "prefixes": [ "PATCHv5", "12/15" ] }