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GET /api/patches/2222477/?format=api
HTTP 200 OK
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Content-Type: application/json
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{
    "id": 2222477,
    "url": "http://patchwork.ozlabs.org/api/patches/2222477/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260412064701.357997-1-s-vadapalli@ti.com/",
    "project": {
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        "name": "U-Boot",
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    "msgid": "<20260412064701.357997-1-s-vadapalli@ti.com>",
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    "date": "2026-04-12T06:46:17",
    "name": "doc: board: ti: j784s4_evm: Automate BAR address lookup for PCIe Boot",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "7166cc1aafddcf55bc00d9b9f4a3476a6bea1e6f",
    "submitter": {
        "id": 84157,
        "url": "http://patchwork.ozlabs.org/api/people/84157/?format=api",
        "name": "Siddharth Vadapalli",
        "email": "s-vadapalli@ti.com"
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        "username": "xypron",
        "first_name": "Heinrich",
        "last_name": "Schuchardt",
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    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260412064701.357997-1-s-vadapalli@ti.com/mbox/",
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            "url": "http://patchwork.ozlabs.org/api/series/499586/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=499586",
            "date": "2026-04-12T06:46:17",
            "name": "doc: board: ti: j784s4_evm: Automate BAR address lookup for PCIe Boot",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/499586/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2222477/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2222477/checks/",
    "tags": {},
    "related": [],
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        "From": "Siddharth Vadapalli <s-vadapalli@ti.com>",
        "To": "<trini@konsulko.com>, <mkorpershoek@kernel.org>, <u-kumar1@ti.com>,\n <anshuld@ti.com>",
        "CC": "<u-boot@lists.denx.de>, <srk@ti.com>, <s-vadapalli@ti.com>",
        "Subject": "[PATCH] doc: board: ti: j784s4_evm: Automate BAR address lookup for\n PCIe Boot",
        "Date": "Sun, 12 Apr 2026 12:16:17 +0530",
        "Message-ID": "<20260412064701.357997-1-s-vadapalli@ti.com>",
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    "content": "When the J784S4-EVM is configured for PCIe Boot, the Bootloaders are to\nbe written to the address specified by particular BARs. The existing\ndocumentation hard-codes the address corresponding to the BAR under the\nassumption that the Root-Complex transferring the Bootloaders is also\na J784S4-EVM. The Root-Complex assigns addresses to the BARs depending\non the currently available set of free system addresses. Since the free\nsystem addresses vary with the Root-Complex being used, instead of\nhard-coding the BARs, automate the process of identifying the appropriate\nBAR in the form of a command to be run by the user on the Root-Complex.\n\nSigned-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>\n---\n\nThis patch is based on commit\ne2fa3e570f8 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh\nof the master branch of U-Boot.\n\nPatch has been tested by running the following command to build the\ndocumentation:\nmake htmldocs\nfollowed by verifying that the update is reflected in the generated\ndocumentation with proper formatting.\n\nRegards,\nSiddharth.\n\n doc/board/ti/j784s4_evm.rst | 16 +++++++++-------\n 1 file changed, 9 insertions(+), 7 deletions(-)",
    "diff": "diff --git a/doc/board/ti/j784s4_evm.rst b/doc/board/ti/j784s4_evm.rst\nindex fb767bedbf6..f89def076c2 100644\n--- a/doc/board/ti/j784s4_evm.rst\n+++ b/doc/board/ti/j784s4_evm.rst\n@@ -456,12 +456,12 @@ The following steps describe the process of booting J784S4-EVM over PCIe:\n       0000:01:00.1 Non-VGA unclassified device: Texas Instruments Device 0100\n       0000:01:00.2 Non-VGA unclassified device: Texas Instruments Device 0100\n \n-4. Copy ``tiboot3.bin`` to the endpoint. Use ``lspci -vv`` to identify the BAR\n-   address:\n+4. Copy ``tiboot3.bin`` to BAR1 of Physical Function Zero of the endpoint:\n \n    .. prompt:: bash\n \n-      sudo ./pcie_boot_util 0x4007100000 tiboot3.bin\n+      tiboot3_bar_address=\"0x$(lspci -D -nnvv | awk '/^[0-9a-fA-F]{4}:/ {bdf=$1; ram=($0 ~ /RAM memory/ || $0 ~ /Memory controller/)} ram && /Region [1]+:/ {print bdf, $0}' | cut -d ' ' -f 6)\"\n+      sudo ./pcie_boot_util ${tiboot3_bar_address} tiboot3.bin\n \n    The sample program automatically writes the image start address to\n    ``0x41CF3FE0`` and the magic word ``0xB17CEAD9`` to ``0x41CF3FE4``.\n@@ -491,11 +491,12 @@ The following steps describe the process of booting J784S4-EVM over PCIe:\n       (with appropriate DOMAIN:BUS:DEVICE.FUNCTION corresponding to the Endpoint) to enable\n       the BAR.\n \n-6. Copy ``tispl.bin`` to the new BAR address (use ``lspci -vv`` to find):\n+6. Copy ``tispl.bin`` to BAR0 of Physical Function Zero of the endpoint:\n \n    .. prompt:: bash\n \n-      sudo ./pcie_boot_util 0x4000400000 tispl.bin\n+      tispl_bar_address=\"0x$(lspci -D -nnvv | awk '/^[0-9a-fA-F]{4}:/ {bdf=$1; ram=($0 ~ /RAM memory/ || $0 ~ /Memory controller/)} ram && /Region [0]+:/ {print bdf, $0}' | head -n1 | cut -d ' ' -f 6)\"\n+      sudo ./pcie_boot_util ${tispl_bar_address} tispl.bin\n \n 7. After ``tispl.bin`` is processed, the PCIe link will go down again. Remove\n    and rescan the PCIe device:\n@@ -505,11 +506,12 @@ The following steps describe the process of booting J784S4-EVM over PCIe:\n       echo 1 > /sys/bus/pci/devices/0000\\:01\\:00.0/remove\n       echo 1 > /sys/bus/pci/devices/0000\\:00\\:00.0/rescan\n \n-8. Copy ``u-boot.img``:\n+8. Copy ``u-boot.img`` to BAR0 of Physical Function Zero of the endpoint:\n \n    .. prompt:: bash\n \n-      sudo ./pcie_boot_util 0x4000400000 u-boot.img\n+      uboot_bar_address=\"0x$(lspci -D -nnvv | awk '/^[0-9a-fA-F]{4}:/ {bdf=$1; ram=($0 ~ /RAM memory/ || $0 ~ /Memory controller/)} ram && /Region [0]+:/ {print bdf, $0}' | head -n1 | cut -d ' ' -f 6)\"\n+      sudo ./pcie_boot_util ${uboot_bar_address} u-boot.img\n \n 9. After ``u-boot.img`` is successfully loaded, the boot process is complete\n    and endpoint should boot till U-Boot prompt.\n",
    "prefixes": []
}