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GET /api/patches/2222472/?format=api
{ "id": 2222472, "url": "http://patchwork.ozlabs.org/api/patches/2222472/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/cca288cd6fbd75ee1b84b6af8c3dad87a96c7357.1775959096.git.chao.liu.zevorn@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<cca288cd6fbd75ee1b84b6af8c3dad87a96c7357.1775959096.git.chao.liu.zevorn@gmail.com>", "list_archive_url": null, "date": "2026-04-12T02:20:23", "name": "[v6,6/7] target/riscv: add sdext single-step support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e828af63cfd8c23f1d3b6a49a1889a4ee56d53c1", "submitter": { "id": 92265, "url": "http://patchwork.ozlabs.org/api/people/92265/?format=api", "name": "Chao Liu", "email": "chao.liu.zevorn@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/cca288cd6fbd75ee1b84b6af8c3dad87a96c7357.1775959096.git.chao.liu.zevorn@gmail.com/mbox/", "series": [ { "id": 499584, "url": "http://patchwork.ozlabs.org/api/series/499584/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499584", "date": "2026-04-12T02:20:20", "name": "riscv: add initial sdext support", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/499584/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222472/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222472/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=ra14ZT42;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-qt1-x842.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "RISC-V Debug Specification:\nhttps://github.com/riscv/riscv-debug-spec/releases/tag/1.0\n\nUse a TB flag when dcsr.step is set (and we are not in Debug Mode).\nWhen the flag is on, build 1-insn TBs and do not chain to the next TB.\nAdd a TB-exit helper that enters Debug Mode with cause=step and sets\ndpc to the next pc, then stops with EXCP_DEBUG.\n\nIf dcsr.stepie is 0, do not take interrupts while stepping. Treat WFI\nas a nop so the hart does not sleep during a step.\n\nPS: This patch references Max Chou's handling of ext_tb_flags.\nhttps://lore.kernel.org/qemu-devel/20260108132631.9429-6-max.chou@sifive.com/\n\nSigned-off-by: Chao Liu <chao.liu.zevorn@gmail.com>\nReviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>\nTested-by: Tao Tang <tangtao1634@phytium.com.cn>\n---\n include/exec/translation-block.h | 4 ++--\n target/riscv/cpu.h | 2 ++\n target/riscv/cpu_helper.c | 6 ++++++\n target/riscv/helper.h | 1 +\n target/riscv/op_helper.c | 20 ++++++++++++++++++++\n target/riscv/tcg/tcg-cpu.c | 5 +++++\n target/riscv/translate.c | 15 +++++++++++++--\n 7 files changed, 49 insertions(+), 4 deletions(-)", "diff": "diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h\nindex 40cc699031..ee15608c89 100644\n--- a/include/exec/translation-block.h\n+++ b/include/exec/translation-block.h\n@@ -64,8 +64,8 @@ struct TranslationBlock {\n * x86: the original user, the Code Segment virtual base,\n * arm: an extension of tb->flags,\n * s390x: instruction data for EXECUTE,\n- * sparc: the next pc of the instruction queue (for delay slots).\n- * riscv: an extension of tb->flags,\n+ * sparc: the next pc of the instruction queue (for delay slots),\n+ * riscv: an extension of tb->flags.\n */\n uint64_t cs_base;\n \ndiff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 62732957a4..0d6b70c9f0 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -712,6 +712,8 @@ FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1)\n \n FIELD(EXT_TB_FLAGS, MISA_EXT, 0, 32)\n FIELD(EXT_TB_FLAGS, ALTFMT, 32, 1)\n+/* sdext single-step needs a TB flag to build 1-insn TBs */\n+FIELD(EXT_TB_FLAGS, SDEXT_STEP, 33, 1)\n \n #ifdef TARGET_RISCV32\n #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)\ndiff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c\nindex 0ff11a45de..cefab2b131 100644\n--- a/target/riscv/cpu_helper.c\n+++ b/target/riscv/cpu_helper.c\n@@ -635,6 +635,12 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)\n if (interrupt_request & mask) {\n RISCVCPU *cpu = RISCV_CPU(cs);\n CPURISCVState *env = &cpu->env;\n+\n+ if (cpu->cfg.ext_sdext && !env->debug_mode &&\n+ (env->dcsr & DCSR_STEP) && !(env->dcsr & DCSR_STEPIE)) {\n+ return false;\n+ }\n+\n int interruptno = riscv_cpu_local_irq_pending(env);\n if (interruptno >= 0) {\n cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;\ndiff --git a/target/riscv/helper.h b/target/riscv/helper.h\nindex 9538e816f0..68e9796289 100644\n--- a/target/riscv/helper.h\n+++ b/target/riscv/helper.h\n@@ -143,6 +143,7 @@ DEF_HELPER_1(tlb_flush_all, void, env)\n DEF_HELPER_4(ctr_add_entry, void, env, tl, tl, tl)\n /* Native Debug */\n DEF_HELPER_1(itrigger_match, void, env)\n+DEF_HELPER_1(sdext_step, void, env)\n DEF_HELPER_2(sdext_ebreak, void, env, tl)\n #endif\n \ndiff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c\nindex 58d47b88c1..0165e98d16 100644\n--- a/target/riscv/op_helper.c\n+++ b/target/riscv/op_helper.c\n@@ -456,6 +456,22 @@ target_ulong helper_dret(CPURISCVState *env)\n #endif\n }\n \n+void helper_sdext_step(CPURISCVState *env)\n+{\n+#ifndef CONFIG_USER_ONLY\n+ CPUState *cs = env_cpu(env);\n+\n+ if (!riscv_cpu_cfg(env)->ext_sdext || env->debug_mode ||\n+ !(env->dcsr & DCSR_STEP)) {\n+ return;\n+ }\n+\n+ riscv_cpu_enter_debug_mode(env, env->pc, DCSR_CAUSE_STEP);\n+ cs->exception_index = EXCP_DEBUG;\n+ cpu_loop_exit_restore(cs, GETPC());\n+#endif\n+}\n+\n void helper_sdext_ebreak(CPURISCVState *env, target_ulong pc)\n {\n CPUState *cs = env_cpu(env);\n@@ -588,6 +604,10 @@ void helper_wfi(CPURISCVState *env)\n (prv_u || (prv_s && get_field(env->hstatus, HSTATUS_VTW)))) {\n riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());\n } else {\n+ if (riscv_cpu_cfg(env)->ext_sdext && !env->debug_mode &&\n+ (env->dcsr & DCSR_STEP)) {\n+ return;\n+ }\n cs->halted = 1;\n cs->exception_index = EXCP_HLT;\n cpu_loop_exit(cs);\ndiff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex 4b17fbb611..cb464c13cd 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -193,6 +193,11 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)\n flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext);\n \n ext_flags = FIELD_DP64(ext_flags, EXT_TB_FLAGS, MISA_EXT, env->misa_ext);\n+#ifndef CONFIG_USER_ONLY\n+ if (cpu->cfg.ext_sdext && !env->debug_mode && (env->dcsr & DCSR_STEP)) {\n+ ext_flags = FIELD_DP64(ext_flags, EXT_TB_FLAGS, SDEXT_STEP, 1);\n+ }\n+#endif\n \n return (TCGTBCPUState){\n .pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc,\ndiff --git a/target/riscv/translate.c b/target/riscv/translate.c\nindex 81087e0a5d..d850aaee89 100644\n--- a/target/riscv/translate.c\n+++ b/target/riscv/translate.c\n@@ -111,6 +111,8 @@ typedef struct DisasContext {\n bool ztso;\n /* Use icount trigger for native debug */\n bool itrigger;\n+ /* Enter Debug Mode after next instruction (sdext single-step). */\n+ bool sdext_step;\n /* FRM is known to contain a valid value. */\n bool frm_valid;\n bool insn_start_updated;\n@@ -293,6 +295,9 @@ static void lookup_and_goto_ptr(DisasContext *ctx)\n if (ctx->itrigger) {\n gen_helper_itrigger_match(tcg_env);\n }\n+ if (ctx->sdext_step) {\n+ gen_helper_sdext_step(tcg_env);\n+ }\n #endif\n tcg_gen_lookup_and_goto_ptr();\n }\n@@ -303,6 +308,9 @@ static void exit_tb(DisasContext *ctx)\n if (ctx->itrigger) {\n gen_helper_itrigger_match(tcg_env);\n }\n+ if (ctx->sdext_step) {\n+ gen_helper_sdext_step(tcg_env);\n+ }\n #endif\n tcg_gen_exit_tb(NULL, 0);\n }\n@@ -316,7 +324,8 @@ static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,\n * Under itrigger, instruction executes one by one like singlestep,\n * direct block chain benefits will be small.\n */\n- if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) {\n+ if (translator_use_goto_tb(&ctx->base, dest) &&\n+ !ctx->itrigger && !ctx->sdext_step) {\n /*\n * For pcrel, the pc must always be up-to-date on entry to\n * the linked TB, so that it can use simple additions for all\n@@ -1357,6 +1366,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)\n ctx->bcfi_enabled = FIELD_EX32(tb_flags, TB_FLAGS, BCFI_ENABLED);\n ctx->fcfi_lp_expected = FIELD_EX32(tb_flags, TB_FLAGS, FCFI_LP_EXPECTED);\n ctx->fcfi_enabled = FIELD_EX32(tb_flags, TB_FLAGS, FCFI_ENABLED);\n+ ctx->sdext_step = FIELD_EX64(ext_tb_flags, EXT_TB_FLAGS, SDEXT_STEP);\n ctx->zero = tcg_constant_tl(0);\n ctx->virt_inst_excp = false;\n ctx->decoders = cpu->decoders;\n@@ -1407,7 +1417,8 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n \n /* Only the first insn within a TB is allowed to cross a page boundary. */\n if (ctx->base.is_jmp == DISAS_NEXT) {\n- if (ctx->itrigger || !translator_is_same_page(&ctx->base, ctx->base.pc_next)) {\n+ if (ctx->itrigger || ctx->sdext_step ||\n+ !translator_is_same_page(&ctx->base, ctx->base.pc_next)) {\n ctx->base.is_jmp = DISAS_TOO_MANY;\n } else {\n unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK;\n", "prefixes": [ "v6", "6/7" ] }