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GET /api/patches/2221951/?format=api
{ "id": 2221951, "url": "http://patchwork.ozlabs.org/api/patches/2221951/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260410-sdxi-base-v1-18-1d184cb5c60a@amd.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260410-sdxi-base-v1-18-1d184cb5c60a@amd.com>", "list_archive_url": null, "date": "2026-04-10T13:07:28", "name": "[18/23] dmaengine: sdxi: Encode context start, stop, and sync descriptors", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "92c80874b0aea96b0dc2382a226140e920f67b80", "submitter": { "id": 91626, "url": "http://patchwork.ozlabs.org/api/people/91626/?format=api", "name": "Nathan Lynch via B4 Relay", "email": "devnull+nathan.lynch.amd.com@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260410-sdxi-base-v1-18-1d184cb5c60a@amd.com/mbox/", "series": [ { "id": 499458, "url": "http://patchwork.ozlabs.org/api/series/499458/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=499458", "date": "2026-04-10T13:07:10", "name": "dmaengine: Smart Data Accelerator Interface (SDXI) basic support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499458/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2221951/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221951/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-52329-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=EaMYLDPb;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52329-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"EaMYLDPb\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fscf13XFMz1yGS\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 10 Apr 2026 23:12:09 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 464B43096135\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 10 Apr 2026 13:08:05 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 193573BFE34;\n\tFri, 10 Apr 2026 13:07:51 +0000 (UTC)", "from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id CBFEC3BC69F;\n\tFri, 10 Apr 2026 13:07:50 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPS id AFCB4C2BCB3;\n\tFri, 10 Apr 2026 13:07:50 +0000 (UTC)", "from aws-us-west-2-korg-lkml-1.web.codeaurora.org\n (localhost.localdomain [127.0.0.1])\n\tby smtp.lore.kernel.org (Postfix) with ESMTP id A84A2F44858;\n\tFri, 10 Apr 2026 13:07:50 +0000 (UTC)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775826470; cv=none;\n b=FQQL1166rSVszDB8ChojiBeaBUpQleyjv9JHrtUTmIUtiwRlq/7i4Xf9haUUoMpiuYGnOVoUjeTifqyH4FtWwb88XoJNa34sdkv2LnNEcvqKM7lsi5OnbaJvrmwaPtCXqraU6BI24J9WN10QWRWmc3wfi9S+Xj72tZqYuVRGiJY=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775826470; c=relaxed/simple;\n\tbh=7PTNiXfzmMoMijKL1CDJ0UFESoKkLV2cE1k6DxUXCXA=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=i5hFNW2Nxs9+l+tZhqlxn7FCwBAVEfXxkn1orMzdmSbKJMrY0hxbRnDkU/RoqMV0ihrOj9TCSoQFEHrEYviRoe1VWh/BWOfbIjjpSCV63q1l2XDpAKu/tgi8ZPw5n99iKOF/0RKPVSLrOcoantnCyJM5SbSf8aYAO2Snxkrvex4=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=EaMYLDPb; arc=none smtp.client-ip=10.30.226.201", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1775826470;\n\tbh=7PTNiXfzmMoMijKL1CDJ0UFESoKkLV2cE1k6DxUXCXA=;\n\th=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From;\n\tb=EaMYLDPbCazumhkaq0ZuUNth6IRcQLlNQ/4ADPojXJ+ST63OOYbDwt2m1v3h0/NWl\n\t HDO1P1Yx9qfxWNLsBExVmDjogswTl8IMClvv067VmeBc2wj25H4R2LNS69Jp0XaE8q\n\t K+4sYb8zs5rhr14oBsoQ1PFrzq/vQkeF+fvrPHgqhzq+pg/B9tGpHJqV55I1+q1lB2\n\t znJ1n33fGWtXpxuOhEOY/9/9qW8ubQiEoT9HiD3uiTbyoPaDFE0aGe0PdckU4fhrk9\n\t A7z6l2B/zTNfUIqNL6o8MQ66y1To03nhaNfsdLnrF/4dhS2q+MOd/2wIEYGubNyr6r\n\t a1JJiF9j9WfrA==", "From": "Nathan Lynch via B4 Relay <devnull+nathan.lynch.amd.com@kernel.org>", "Date": "Fri, 10 Apr 2026 08:07:28 -0500", "Subject": "[PATCH 18/23] dmaengine: sdxi: Encode context start, stop, and\n sync descriptors", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260410-sdxi-base-v1-18-1d184cb5c60a@amd.com>", "References": "<20260410-sdxi-base-v1-0-1d184cb5c60a@amd.com>", "In-Reply-To": "<20260410-sdxi-base-v1-0-1d184cb5c60a@amd.com>", "To": "Vinod Koul <vkoul@kernel.org>", "Cc": "Wei Huang <wei.huang2@amd.com>,\n Mario Limonciello <mario.limonciello@amd.com>,\n Bjorn Helgaas <bhelgaas@google.com>,\n Jonathan Cameron <jonathan.cameron@huawei.com>,\n Stephen Bates <Stephen.Bates@amd.com>, PradeepVineshReddy.Kodamati@amd.com,\n John.Kariuki@amd.com, linux-pci@vger.kernel.org,\n linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,\n Nathan Lynch <nathan.lynch@amd.com>", "X-Mailer": "b4 0.15.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1775826467; l=8319;\n i=nathan.lynch@amd.com; s=20260410; h=from:subject:message-id;\n bh=aP4nY50fmTC+U42HpUPYey6ozJaTcvXeGf14jxN1QZw=;\n b=G8tZCJfk8AZQ+Dlp7Mlx0nO+YGl0o10HWWNn7NewbZuQ/SYoeBd3qu2EAErvWHJ9xhYTfe3Gf\n 7j4J6NIhIs1C7ERodZ8QJfCqy7ap51/9btdhId37P9hRC7v07pmeTog", "X-Developer-Key": "i=nathan.lynch@amd.com; a=ed25519;\n pk=PK4ozhq+/z9/2Jl5rgDmvHa9raVomv79qM8p1RAFpEw=", "X-Endpoint-Received": "by B4 Relay for nathan.lynch@amd.com/20260410 with\n auth_id=728", "X-Original-From": "Nathan Lynch <nathan.lynch@amd.com>", "Reply-To": "nathan.lynch@amd.com" }, "content": "From: Nathan Lynch <nathan.lynch@amd.com>\n\nIntroduce the low-level support for serializing three operation types\nto the descriptor ring of the admin context: context start, context\nstop, and sync. Each operation has its own distinct type that overlays\nthe generic struct sdxi_desc, along with a dedicated encoder function\nthat accepts an operation-specific parameter struct.\n\nThe parameter structs (sdxi_cxt_start, sdxi_cxt_stop, sdxi_sync)\nexpose only a necessary subset of the available descriptor fields to\ncallers, i.e. the target context range. These can be expanded over\ntime as needed.\n\nEach encoder function is intended to 1) set any mandatory field values\nfor the descriptor type (e.g. SDXI_DSC_FE=1 for context start); and 2)\ntranslate conventional kernel types (dma_addr_t, CPU-endian values)\nfrom the parameter block to the descriptor in memory. While they're\nexpected to operate directly on descriptor ring memory, they do not\nset the descriptor validity bit. That is left to the caller, which may\nneed to make other modifictions to the descriptor, such as attaching a\ncompletion block, before releasing it to the SDXI implementation.\n\nCo-developed-by: Wei Huang <wei.huang2@amd.com>\nSigned-off-by: Wei Huang <wei.huang2@amd.com>\nSigned-off-by: Nathan Lynch <nathan.lynch@amd.com>\n---\n drivers/dma/sdxi/Makefile | 1 +\n drivers/dma/sdxi/descriptor.c | 91 +++++++++++++++++++++++++++++++++++++++++++\n drivers/dma/sdxi/descriptor.h | 46 ++++++++++++++++++++++\n drivers/dma/sdxi/hw.h | 64 ++++++++++++++++++++++++++++++\n 4 files changed, 202 insertions(+)", "diff": "diff --git a/drivers/dma/sdxi/Makefile b/drivers/dma/sdxi/Makefile\nindex dd08f4a5f723..08dd73a45dc7 100644\n--- a/drivers/dma/sdxi/Makefile\n+++ b/drivers/dma/sdxi/Makefile\n@@ -4,6 +4,7 @@ obj-$(CONFIG_SDXI) += sdxi.o\n sdxi-objs += \\\n \tcompletion.o \\\n \tcontext.o \\\n+\tdescriptor.o \\\n \tdevice.o \\\n \tring.o\n \ndiff --git a/drivers/dma/sdxi/descriptor.c b/drivers/dma/sdxi/descriptor.c\nnew file mode 100644\nindex 000000000000..be2a9244ce19\n--- /dev/null\n+++ b/drivers/dma/sdxi/descriptor.c\n@@ -0,0 +1,91 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * SDXI descriptor encoding.\n+ *\n+ * Copyright Advanced Micro Devices, Inc.\n+ */\n+\n+#include <kunit/visibility.h>\n+#include <linux/bitfield.h>\n+#include <linux/types.h>\n+#include <asm/byteorder.h>\n+\n+#include \"hw.h\"\n+#include \"descriptor.h\"\n+\n+int sdxi_encode_cxt_start(struct sdxi_desc *desc,\n+\t\t\t const struct sdxi_cxt_start *params)\n+{\n+\tu64 csb_ptr;\n+\tu32 opcode;\n+\n+\topcode = (FIELD_PREP(SDXI_DSC_FE, 1) |\n+\t\t FIELD_PREP(SDXI_DSC_SUBTYPE, SDXI_DSC_OP_SUBTYPE_CXT_START_NM) |\n+\t\t FIELD_PREP(SDXI_DSC_TYPE, SDXI_DSC_OP_TYPE_ADMIN));\n+\n+\tcsb_ptr = FIELD_PREP(SDXI_DSC_NP, 1);\n+\n+\t*desc = (typeof(*desc)) {\n+\t\t.cxt_start = (typeof(desc->cxt_start)) {\n+\t\t\t.opcode = cpu_to_le32(opcode),\n+\t\t\t.cxt_start = cpu_to_le16(params->range.cxt_start),\n+\t\t\t.cxt_end = cpu_to_le16(params->range.cxt_end),\n+\t\t\t.csb_ptr = cpu_to_le64(csb_ptr),\n+\t\t},\n+\t};\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL_IF_KUNIT(sdxi_encode_cxt_start);\n+\n+int sdxi_encode_cxt_stop(struct sdxi_desc *desc,\n+\t\t\t const struct sdxi_cxt_stop *params)\n+{\n+\tu64 csb_ptr;\n+\tu32 opcode;\n+\n+\topcode = (FIELD_PREP(SDXI_DSC_FE, 1) |\n+\t\t FIELD_PREP(SDXI_DSC_SUBTYPE, SDXI_DSC_OP_SUBTYPE_CXT_STOP) |\n+\t\t FIELD_PREP(SDXI_DSC_TYPE, SDXI_DSC_OP_TYPE_ADMIN));\n+\n+\tcsb_ptr = FIELD_PREP(SDXI_DSC_NP, 1);\n+\n+\t*desc = (typeof(*desc)) {\n+\t\t.cxt_stop = (typeof(desc->cxt_stop)) {\n+\t\t\t.opcode = cpu_to_le32(opcode),\n+\t\t\t.cxt_start = cpu_to_le16(params->range.cxt_start),\n+\t\t\t.cxt_end = cpu_to_le16(params->range.cxt_end),\n+\t\t\t.csb_ptr = cpu_to_le64(csb_ptr),\n+\t\t},\n+\t};\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL_IF_KUNIT(sdxi_encode_cxt_stop);\n+\n+int sdxi_encode_sync(struct sdxi_desc *desc, const struct sdxi_sync *params)\n+{\n+\tu64 csb_ptr;\n+\tu32 opcode;\n+\tu8 cflags;\n+\n+\topcode = (FIELD_PREP(SDXI_DSC_SUBTYPE, SDXI_DSC_OP_SUBTYPE_SYNC) |\n+\t\t FIELD_PREP(SDXI_DSC_TYPE, SDXI_DSC_OP_TYPE_ADMIN));\n+\n+\tcflags = FIELD_PREP(SDXI_DSC_SYNC_FLT, params->filter);\n+\n+\tcsb_ptr = FIELD_PREP(SDXI_DSC_NP, 1);\n+\n+\t*desc = (typeof(*desc)) {\n+\t\t.sync = (typeof(desc->sync)) {\n+\t\t\t.opcode = cpu_to_le32(opcode),\n+\t\t\t.cflags = cflags,\n+\t\t\t.cxt_start = cpu_to_le16(params->range.cxt_start),\n+\t\t\t.cxt_end = cpu_to_le16(params->range.cxt_end),\n+\t\t\t.csb_ptr = cpu_to_le64(csb_ptr),\n+\t\t},\n+\t};\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL_IF_KUNIT(sdxi_encode_sync);\ndiff --git a/drivers/dma/sdxi/descriptor.h b/drivers/dma/sdxi/descriptor.h\nindex c0f01b1be726..5b8fd7cbaa03 100644\n--- a/drivers/dma/sdxi/descriptor.h\n+++ b/drivers/dma/sdxi/descriptor.h\n@@ -9,6 +9,7 @@\n */\n \n #include <linux/bitfield.h>\n+#include <linux/minmax.h>\n #include <linux/ratelimit.h>\n #include <linux/types.h>\n #include <asm/byteorder.h>\n@@ -61,4 +62,49 @@ static inline void sdxi_desc_set_sequential(struct sdxi_desc *desc)\n \tdesc->opcode = cpu_to_le32(opcode);\n }\n \n+struct sdxi_cxt_range {\n+\tu16 cxt_start;\n+\tu16 cxt_end;\n+};\n+\n+static inline struct sdxi_cxt_range sdxi_cxt_range(u16 a, u16 b)\n+{\n+\treturn (struct sdxi_cxt_range) {\n+\t\t.cxt_start = min(a, b),\n+\t\t.cxt_end = max(a, b),\n+\t};\n+}\n+\n+static inline struct sdxi_cxt_range sdxi_cxt_range_single(u16 nr)\n+{\n+\treturn sdxi_cxt_range(nr, nr);\n+}\n+\n+struct sdxi_cxt_start {\n+\tstruct sdxi_cxt_range range;\n+};\n+\n+int sdxi_encode_cxt_start(struct sdxi_desc *desc,\n+\t\t\t const struct sdxi_cxt_start *params);\n+\n+struct sdxi_cxt_stop {\n+\tstruct sdxi_cxt_range range;\n+};\n+\n+int sdxi_encode_cxt_stop(struct sdxi_desc *desc,\n+\t\t\t const struct sdxi_cxt_stop *params);\n+\n+struct sdxi_sync {\n+\tenum sdxi_sync_filter {\n+\t\tSDXI_SYNC_FLT_CXT = 0x0,\n+\t\tSDXI_SYNC_FLT_STOP = 0x1,\n+\t\tSDXI_SYNC_FLT_AKEY = 0x2,\n+\t\tSDXI_SYNC_FLT_RKEY = 0x3,\n+\t\tSDXI_SYNC_FLT_FN = 0x4,\n+\t} filter;\n+\tstruct sdxi_cxt_range range;\n+};\n+\n+int sdxi_encode_sync(struct sdxi_desc *desc, const struct sdxi_sync *params);\n+\n #endif /* DMA_SDXI_DESCRIPTOR_H */\ndiff --git a/drivers/dma/sdxi/hw.h b/drivers/dma/sdxi/hw.h\nindex 178161588bd0..4dcd0a3ff0fd 100644\n--- a/drivers/dma/sdxi/hw.h\n+++ b/drivers/dma/sdxi/hw.h\n@@ -146,12 +146,76 @@ struct sdxi_desc {\n #define SDXI_DSC_VL BIT(0)\n #define SDXI_DSC_SE BIT(1)\n #define SDXI_DSC_FE BIT(2)\n+#define SDXI_DSC_SUBTYPE GENMASK(15, 8)\n+#define SDXI_DSC_TYPE GENMASK(26, 16)\n \n /* For csb_ptr field */\n+#define SDXI_DSC_NP BIT_ULL(0)\n #define SDXI_DSC_CSB_PTR GENMASK_ULL(63, 5)\n \n+#define define_sdxi_dsc(tag_, name_, op_body_)\t\t\t\t\\\n+\tstruct tag_ {\t\t\t\t\t\t\t\\\n+\t\t__le32 opcode;\t\t\t\t\t\t\\\n+\t\top_body_\t\t\t\t\t\t\\\n+\t\t__le64 csb_ptr;\t\t\t\t\t\t\\\n+\t} __packed name_;\t\t\t\t\t\t\\\n+\tstatic_assert(sizeof(struct tag_) ==\t\t\t\t\\\n+\t\t sizeof(struct sdxi_dsc_generic));\t\t\t\\\n+\tstatic_assert(offsetof(struct tag_, csb_ptr) ==\t\t\t\\\n+\t\t offsetof(struct sdxi_dsc_generic, csb_ptr))\n+\n+\t\t/* SDXI 1.0 Table 6-14: DSC_CXT_START Descriptor Format */\n+\t\tdefine_sdxi_dsc(sdxi_dsc_cxt_start, cxt_start,\n+\t\t\t__u8 rsvd_0;\n+\t\t\t__u8 vflags;\n+\t\t\t__le16 vf_num;\n+\t\t\t__le16 cxt_start;\n+\t\t\t__le16 cxt_end;\n+\t\t\t__u8 rsvd_1[4];\n+\t\t\t__le64 db_value;\n+\t\t\t__u8 rsvd_2[32];\n+\t\t);\n+\n+\t\t/* SDXI 1.0 Table 6-15: DSC_CXT_STOP Descriptor Format */\n+\t\tdefine_sdxi_dsc(sdxi_dsc_cxt_stop, cxt_stop,\n+\t\t\t__u8 rsvd_0;\n+\t\t\t__u8 vflags;\n+\t\t\t__le16 vf_num;\n+\t\t\t__le16 cxt_start;\n+\t\t\t__le16 cxt_end;\n+\t\t\t__u8 rsvd_1[44];\n+\t\t);\n+\n+\t\t/* SDXI 1.0 Table 6-22: DSC_SYNC Descriptor Format */\n+\t\tdefine_sdxi_dsc(sdxi_dsc_sync, sync,\n+\t\t\t__u8 cflags;\n+\t\t\t__u8 vflags;\n+\t\t\t__le16 vf_num;\n+\t\t\t__le16 cxt_start;\n+\t\t\t__le16 cxt_end;\n+\t\t\t__le16 key_start;\n+\t\t\t__le16 key_end;\n+\t\t\t__u8 rsvd_0[40];\n+\t\t);\n+/* For use with sync.cflags */\n+#define SDXI_DSC_SYNC_FLT GENMASK(2, 0)\n+\n+#undef define_sdxi_dsc\n \t};\n } __packed;\n static_assert(sizeof(struct sdxi_desc) == 64);\n \n+/* SDXI 1.0 Table 6-1: SDXI Operation Groups */\n+enum sdxi_dsc_type {\n+\tSDXI_DSC_OP_TYPE_ADMIN = 0x002,\n+};\n+\n+/* SDXI 1.0 Table 6-2: SDXI Operation Groups, Types, and Subtypes */\n+enum sdxi_dsc_subtype {\n+\t/* Administrative */\n+\tSDXI_DSC_OP_SUBTYPE_CXT_START_NM = 0x03,\n+\tSDXI_DSC_OP_SUBTYPE_CXT_STOP = 0x04,\n+\tSDXI_DSC_OP_SUBTYPE_SYNC = 0x06,\n+};\n+\n #endif /* DMA_SDXI_HW_H */\n", "prefixes": [ "18/23" ] }