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GET /api/patches/2221934/?format=api
{ "id": 2221934, "url": "http://patchwork.ozlabs.org/api/patches/2221934/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260410-sdxi-base-v1-16-1d184cb5c60a@amd.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260410-sdxi-base-v1-16-1d184cb5c60a@amd.com>", "list_archive_url": null, "date": "2026-04-10T13:07:26", "name": "[16/23] dmaengine: sdxi: Generic descriptor manipulation helpers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b886442c644b9d07fef3f31db5697565e7959156", "submitter": { "id": 91626, "url": "http://patchwork.ozlabs.org/api/people/91626/?format=api", "name": "Nathan Lynch via B4 Relay", "email": "devnull+nathan.lynch.amd.com@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260410-sdxi-base-v1-16-1d184cb5c60a@amd.com/mbox/", "series": [ { "id": 499458, "url": "http://patchwork.ozlabs.org/api/series/499458/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=499458", "date": "2026-04-10T13:07:10", "name": "dmaengine: Smart Data Accelerator Interface (SDXI) basic support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499458/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2221934/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221934/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-52328-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=oZxD/Mjm;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-52328-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"oZxD/Mjm\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fscYp6jPYz1yGb\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 10 Apr 2026 23:08:30 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id DFD703039FFE\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 10 Apr 2026 13:08:03 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 1827E3BFE31;\n\tFri, 10 Apr 2026 13:07:51 +0000 (UTC)", "from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id A54F13B2FD5;\n\tFri, 10 Apr 2026 13:07:50 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPS id 89AF6C2BCF4;\n\tFri, 10 Apr 2026 13:07:50 +0000 (UTC)", "from aws-us-west-2-korg-lkml-1.web.codeaurora.org\n (localhost.localdomain [127.0.0.1])\n\tby smtp.lore.kernel.org (Postfix) with ESMTP id 83173F44861;\n\tFri, 10 Apr 2026 13:07:50 +0000 (UTC)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775826470; cv=none;\n b=IbFXGxY3wg6XcBwA/5yrs0MNsgN1YtZ6knFyUp/MwdyKX+QeMS3SxjD/KN7lpMtFarqFBGOoiibpFb3lsp3EYlcjsOoJLawZdncIB6Vfm24lgFTlLe82q45jM1ocVzb9gCc+Q+yV6UIXepV49kR8AHNM6bGxB3Fw/YlYYH6Hy0Q=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775826470; c=relaxed/simple;\n\tbh=SrdVR/zASpBIWlniEiIxoO0qyZvZr0iZfP+wJLzN6zk=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=jUVJXYRuvMObKZQfJUlJykRvS0AlNoJLJpQTyjfgr1qNst0fJD0aCEmZ0Fypv0HYq2EfjcBb0TrRe6SjWUUGcMy2wZdNcUxCOlyjaEkf2b3E/B/kXz13glByUyNVR67+dxJmsPbkTmc16Qb5y3WCwCNQa3+8W5JJvtCEgOHHEfk=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=oZxD/Mjm; arc=none smtp.client-ip=10.30.226.201", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1775826470;\n\tbh=SrdVR/zASpBIWlniEiIxoO0qyZvZr0iZfP+wJLzN6zk=;\n\th=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From;\n\tb=oZxD/MjmjiyABwcLxqXy+JOXPiNq9vQRaLf7Sb7z1vAsQYHdj+nVwPFkdJuKz/jME\n\t l/8/OqqYn8XPV73uaJ+xxnJft7edRUChoI5zRWQm2PDS36EgMZoth5EpvoJ/LyTE+I\n\t nP7zhBaRPsuc9K3IyyEBmOgoBApG4BJcTPORnuwLiaxj8d1HFBVEPsphBL/CcIC7+X\n\t rUr2Qq46/y5tfHJR4ARcfzKasxpm+LT0q771YvG3Qj6AjsZfMU9EoZYBLajwLffvKT\n\t ozI2pQYfPVpCZXlvPB1dirl3PgkaTtCPJtcdO+1yBxlZsm20T1nCdCgl+cogwM4Yh+\n\t 6C7W/wLshm3GA==", "From": "Nathan Lynch via B4 Relay <devnull+nathan.lynch.amd.com@kernel.org>", "Date": "Fri, 10 Apr 2026 08:07:26 -0500", "Subject": "[PATCH 16/23] dmaengine: sdxi: Generic descriptor manipulation\n helpers", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260410-sdxi-base-v1-16-1d184cb5c60a@amd.com>", "References": "<20260410-sdxi-base-v1-0-1d184cb5c60a@amd.com>", "In-Reply-To": "<20260410-sdxi-base-v1-0-1d184cb5c60a@amd.com>", "To": "Vinod Koul <vkoul@kernel.org>", "Cc": "Wei Huang <wei.huang2@amd.com>,\n Mario Limonciello <mario.limonciello@amd.com>,\n Bjorn Helgaas <bhelgaas@google.com>,\n Jonathan Cameron <jonathan.cameron@huawei.com>,\n Stephen Bates <Stephen.Bates@amd.com>, PradeepVineshReddy.Kodamati@amd.com,\n John.Kariuki@amd.com, linux-pci@vger.kernel.org,\n linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,\n Nathan Lynch <nathan.lynch@amd.com>", "X-Mailer": "b4 0.15.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1775826467; l=3976;\n i=nathan.lynch@amd.com; s=20260410; h=from:subject:message-id;\n bh=Lszd5dFpwIf8x9JZPBSkgBuvGWv9C1XzwrHoWKMViVE=;\n b=0RRy/1dL9AMFLIZJJ2oQ3qAPzAbErPl2xIHzjlVvUswvgk87MV9ZeramCKECR2+PXTRca1BTg\n sVfko36kstwAR3dNijg2HbLPD8Ze7Q2WULh499jkZawK3GM39j2BQRi", "X-Developer-Key": "i=nathan.lynch@amd.com; a=ed25519;\n pk=PK4ozhq+/z9/2Jl5rgDmvHa9raVomv79qM8p1RAFpEw=", "X-Endpoint-Received": "by B4 Relay for nathan.lynch@amd.com/20260410 with\n auth_id=728", "X-Original-From": "Nathan Lynch <nathan.lynch@amd.com>", "Reply-To": "nathan.lynch@amd.com" }, "content": "From: Nathan Lynch <nathan.lynch@amd.com>\n\nIntroduce small helper functions for manipulating certain common\nproperties of descriptors after their operation-specific encoding has\nbeen performed but before they are submitted.\n\nsdxi_desc_set_csb() associates an optional completion status block\nwith a descriptor.\n\nsdxi_desc_set_fence() forces retirement of any prior descriptors in\nthe ring before the target descriptor is executed. This is useful for\ninterrupt descriptors that signal the completion of an operation.\n\nsdxi_desc_set_sequential() ensures that all writes from prior\ndescriptor operations in the same context are made globally visible\nprior to making writes from the target descriptor globally visible.\n\nsdxi_desc_make_valid() sets the descriptor validity bit, transferring\nownership of the descriptor from software to the SDXI\nimplementation. (The implementation is allowed to execute the\ndescriptor at this point, but the caller is still obligated to push\nthe doorbell to ensure execution occurs.)\n\nEach of the preceding functions will warn if invoked on a descriptor\nthat has already been released to the SDXI implementation (i.e. had\nits validity bit set).\n\nCo-developed-by: Wei Huang <wei.huang2@amd.com>\nSigned-off-by: Wei Huang <wei.huang2@amd.com>\nSigned-off-by: Nathan Lynch <nathan.lynch@amd.com>\n---\n drivers/dma/sdxi/descriptor.h | 64 +++++++++++++++++++++++++++++++++++++++++++\n drivers/dma/sdxi/hw.h | 9 ++++++\n 2 files changed, 73 insertions(+)", "diff": "diff --git a/drivers/dma/sdxi/descriptor.h b/drivers/dma/sdxi/descriptor.h\nnew file mode 100644\nindex 000000000000..c0f01b1be726\n--- /dev/null\n+++ b/drivers/dma/sdxi/descriptor.h\n@@ -0,0 +1,64 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+#ifndef DMA_SDXI_DESCRIPTOR_H\n+#define DMA_SDXI_DESCRIPTOR_H\n+\n+/*\n+ * Facilities for encoding SDXI descriptors.\n+ *\n+ * Copyright Advanced Micro Devices, Inc.\n+ */\n+\n+#include <linux/bitfield.h>\n+#include <linux/ratelimit.h>\n+#include <linux/types.h>\n+#include <asm/byteorder.h>\n+\n+#include \"hw.h\"\n+\n+static inline void sdxi_desc_vl_expect(const struct sdxi_desc *desc, bool expected)\n+{\n+\tu8 vl = FIELD_GET(SDXI_DSC_VL, le32_to_cpu(desc->opcode));\n+\n+\tWARN_RATELIMIT(vl != expected, \"expected vl=%u but got %u\\n\", expected, vl);\n+}\n+\n+static inline void sdxi_desc_set_csb(struct sdxi_desc *desc, dma_addr_t addr)\n+{\n+\tsdxi_desc_vl_expect(desc, 0);\n+\tdesc->csb_ptr = cpu_to_le64(FIELD_PREP(SDXI_DSC_CSB_PTR, addr >> 5));\n+}\n+\n+static inline void sdxi_desc_make_valid(struct sdxi_desc *desc)\n+{\n+\tu32 opcode = le32_to_cpu(desc->opcode);\n+\n+\tsdxi_desc_vl_expect(desc, 0);\n+\tFIELD_MODIFY(SDXI_DSC_VL, &opcode, 1);\n+\t/*\n+\t * Once vl is set, no more modifications to the descriptor\n+\t * payload are allowed. Ensure the vl update is ordered after\n+\t * all other initialization of the descriptor.\n+\t */\n+\tdma_wmb();\n+\tWRITE_ONCE(desc->opcode, cpu_to_le32(opcode));\n+}\n+\n+static inline void sdxi_desc_set_fence(struct sdxi_desc *desc)\n+{\n+\tu32 opcode = le32_to_cpu(desc->opcode);\n+\n+\tsdxi_desc_vl_expect(desc, 0);\n+\tFIELD_MODIFY(SDXI_DSC_FE, &opcode, 1);\n+\tdesc->opcode = cpu_to_le32(opcode);\n+}\n+\n+static inline void sdxi_desc_set_sequential(struct sdxi_desc *desc)\n+{\n+\tu32 opcode = le32_to_cpu(desc->opcode);\n+\n+\tsdxi_desc_vl_expect(desc, 0);\n+\tFIELD_MODIFY(SDXI_DSC_SE, &opcode, 1);\n+\tdesc->opcode = cpu_to_le32(opcode);\n+}\n+\n+#endif /* DMA_SDXI_DESCRIPTOR_H */\ndiff --git a/drivers/dma/sdxi/hw.h b/drivers/dma/sdxi/hw.h\nindex 46424376f26f..cb1bed2f83f2 100644\n--- a/drivers/dma/sdxi/hw.h\n+++ b/drivers/dma/sdxi/hw.h\n@@ -140,6 +140,15 @@ struct sdxi_desc {\n \t\t\t__u8 operation[52];\n \t\t\t__le64 csb_ptr;\n \t\t);\n+\n+/* For opcode field */\n+#define SDXI_DSC_VL BIT(0)\n+#define SDXI_DSC_SE BIT(1)\n+#define SDXI_DSC_FE BIT(2)\n+\n+/* For csb_ptr field */\n+#define SDXI_DSC_CSB_PTR GENMASK_ULL(63, 5)\n+\n \t};\n } __packed;\n static_assert(sizeof(struct sdxi_desc) == 64);\n", "prefixes": [ "16/23" ] }