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GET /api/patches/2221931/?format=api
{ "id": 2221931, "url": "http://patchwork.ozlabs.org/api/patches/2221931/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260410-sdxi-base-v1-8-1d184cb5c60a@amd.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260410-sdxi-base-v1-8-1d184cb5c60a@amd.com>", "list_archive_url": null, "date": "2026-04-10T13:07:18", "name": "[08/23] dmaengine: sdxi: Install administrative context", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "22db385f28e6d68d53794cb90ec8e0b8e2ac7187", "submitter": { "id": 91626, "url": "http://patchwork.ozlabs.org/api/people/91626/?format=api", "name": "Nathan Lynch via B4 Relay", "email": "devnull+nathan.lynch.amd.com@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260410-sdxi-base-v1-8-1d184cb5c60a@amd.com/mbox/", "series": [ { "id": 499458, "url": "http://patchwork.ozlabs.org/api/series/499458/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=499458", "date": "2026-04-10T13:07:10", "name": "dmaengine: Smart Data Accelerator Interface (SDXI) basic support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499458/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2221931/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221931/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-52319-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=l28k8Jt4;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-52319-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"l28k8Jt4\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fscYL68Fpz1yGb\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 10 Apr 2026 23:08:06 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 086B53029C28\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 10 Apr 2026 13:07:57 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 8BF023A75BD;\n\tFri, 10 Apr 2026 13:07:50 +0000 (UTC)", "from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 24780345740;\n\tFri, 10 Apr 2026 13:07:50 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPS id 03614C19421;\n\tFri, 10 Apr 2026 13:07:50 +0000 (UTC)", "from aws-us-west-2-korg-lkml-1.web.codeaurora.org\n (localhost.localdomain [127.0.0.1])\n\tby smtp.lore.kernel.org (Postfix) with ESMTP id F078FF4485D;\n\tFri, 10 Apr 2026 13:07:49 +0000 (UTC)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775826470; cv=none;\n b=lJbPRvYxSSk0RY1z4zXEXyftugs9qfPbAp46MfbqF70GDBEICpSnVa9cy65jwXpC4f6YJtVbmfSQc0815Bz4uQCIuoP79y0T0aqqdrn070swkIZf+gsZI+iXkeO1k87hT1ZLy9FrsgB5nKv8rpmzpJEZqMuw/vM95ZBzoQ0Eigk=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775826470; c=relaxed/simple;\n\tbh=o4CczMmB0uKw2Q7FShkkYeYEWX3YJgkcsAuiDHhXLlI=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=JFPW1+Zosw0ep1wPREBX023n5wfD/tCLnlpNp5xviPjkLsNVp/880+uIweiSBzr8ReF+Xt9ptXtvi/5Y3W+t1zaSw1cTinbDqdwDN6YITZF3dv24q8LEj2tH9jma6tfgqOnVqV48fkGZbymbDhDDwP276XwD7n8huwks4KjNgdE=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=l28k8Jt4; arc=none smtp.client-ip=10.30.226.201", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1775826470;\n\tbh=o4CczMmB0uKw2Q7FShkkYeYEWX3YJgkcsAuiDHhXLlI=;\n\th=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From;\n\tb=l28k8Jt4Y2ipiMNUG7Q8Iu86FeEe6gztmzl60938flEY0vjqcX0bAE9+lzWGnvVGj\n\t 8TMrwW1W330jujvQt5EjK7GOXEz8HOjqLhiOcxexO5gYkWlpkrchWFxYiAgr2fhXqD\n\t 76K73t1PKoqwkVHD65cZJm4i67A1BJxjU9K1zl+ADMWXcRT5sVBb8bzY6f1/EJr17f\n\t mnG3Q5mS8my+mo4m/jEJ9DYlS1Rge7i2qjtblkxuQ7v9FQgpm9pp1OeRjt+ImcZFme\n\t DahLtqSheqQ+OPtoyCujZXk/uJQAHz9/MQ4RVs2tetwzbSna+E7HLgY1fhgK7v1qbg\n\t 1PSNtnlMMuiWg==", "From": "Nathan Lynch via B4 Relay <devnull+nathan.lynch.amd.com@kernel.org>", "Date": "Fri, 10 Apr 2026 08:07:18 -0500", "Subject": "[PATCH 08/23] dmaengine: sdxi: Install administrative context", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260410-sdxi-base-v1-8-1d184cb5c60a@amd.com>", "References": "<20260410-sdxi-base-v1-0-1d184cb5c60a@amd.com>", "In-Reply-To": "<20260410-sdxi-base-v1-0-1d184cb5c60a@amd.com>", "To": "Vinod Koul <vkoul@kernel.org>", "Cc": "Wei Huang <wei.huang2@amd.com>,\n Mario Limonciello <mario.limonciello@amd.com>,\n Bjorn Helgaas <bhelgaas@google.com>,\n Jonathan Cameron <jonathan.cameron@huawei.com>,\n Stephen Bates <Stephen.Bates@amd.com>, PradeepVineshReddy.Kodamati@amd.com,\n John.Kariuki@amd.com, linux-pci@vger.kernel.org,\n linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,\n Nathan Lynch <nathan.lynch@amd.com>", "X-Mailer": "b4 0.15.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1775826467; l=9127;\n i=nathan.lynch@amd.com; s=20260410; h=from:subject:message-id;\n bh=/Fx8iXeI3HhobtRV06Z9oEZi8ZGsAE/ooN/wWY95pT4=;\n b=I+EfpuSbb6B3BwWS4qy9I1U0djZdk/TtIBgr8BNLJ7nq3Vq2T6NwRkd+KhgzujLvaEMpcxouo\n gIOsRq/j1YlAg5LKpf44DxX67HFzjrcYC/nDKTDWcYUIq/tX3gp9p6u", "X-Developer-Key": "i=nathan.lynch@amd.com; a=ed25519;\n pk=PK4ozhq+/z9/2Jl5rgDmvHa9raVomv79qM8p1RAFpEw=", "X-Endpoint-Received": "by B4 Relay for nathan.lynch@amd.com/20260410 with\n auth_id=728", "X-Original-From": "Nathan Lynch <nathan.lynch@amd.com>", "Reply-To": "nathan.lynch@amd.com" }, "content": "From: Nathan Lynch <nathan.lynch@amd.com>\n\nSerialize the context control block, akey table, and L1 entry for the\nadmin context, making its descriptor ring, write index, and context\nstatus block visible to the SDXI implementation once it is activated.\n\nCo-developed-by: Wei Huang <wei.huang2@amd.com>\nSigned-off-by: Wei Huang <wei.huang2@amd.com>\nSigned-off-by: Nathan Lynch <nathan.lynch@amd.com>\n---\n drivers/dma/sdxi/context.c | 162 +++++++++++++++++++++++++++++++++++++++++++++\n drivers/dma/sdxi/context.h | 7 ++\n drivers/dma/sdxi/hw.h | 15 +++++\n drivers/dma/sdxi/sdxi.h | 9 +++\n 4 files changed, 193 insertions(+)", "diff": "diff --git a/drivers/dma/sdxi/context.c b/drivers/dma/sdxi/context.c\nindex 0a6821992776..097d871e530f 100644\n--- a/drivers/dma/sdxi/context.c\n+++ b/drivers/dma/sdxi/context.c\n@@ -7,16 +7,22 @@\n \n #define pr_fmt(fmt) \"SDXI: \" fmt\n \n+#include <linux/align.h>\n+#include <linux/bitfield.h>\n #include <linux/bug.h>\n #include <linux/cleanup.h>\n #include <linux/device/devres.h>\n #include <linux/dma-mapping.h>\n #include <linux/dmapool.h>\n #include <linux/errno.h>\n+#include <linux/iommu.h>\n #include <linux/slab.h>\n #include <linux/types.h>\n+#include <asm/barrier.h>\n+#include <asm/rwonce.h>\n \n #include \"context.h\"\n+#include \"hw.h\"\n #include \"sdxi.h\"\n \n #define DEFAULT_DESC_RING_ENTRIES 1024\n@@ -106,6 +112,152 @@ static struct sdxi_cxt *sdxi_alloc_cxt(struct sdxi_dev *sdxi)\n \treturn_ptr(cxt);\n }\n \n+struct sdxi_cxt_ctl_cfg {\n+\tdma_addr_t ds_ring_ptr;\n+\tdma_addr_t cxt_sts_ptr;\n+\tdma_addr_t write_index_ptr;\n+\tu32 ds_ring_sz;\n+\tu8 qos;\n+\tu8 csa;\n+\tbool se;\n+};\n+\n+static int configure_cxt_ctl(struct sdxi_cxt_ctl *ctl, const struct sdxi_cxt_ctl_cfg *cfg)\n+{\n+\tu64 ds_ring_ptr, cxt_sts_ptr, write_index_ptr;\n+\n+\twrite_index_ptr = FIELD_PREP(SDXI_CXT_CTL_WRITE_INDEX_PTR,\n+\t\t\t\t cfg->write_index_ptr >> WRT_INDEX_PTR_SHIFT);\n+\tcxt_sts_ptr = FIELD_PREP(SDXI_CXT_CTL_CXT_STS_PTR,\n+\t\t\t\t cfg->cxt_sts_ptr >> CXT_STATUS_PTR_SHIFT);\n+\n+\t*ctl = (typeof(*ctl)) {\n+\t\t/*\n+\t\t * ds_ring_ptr contains the validity bit and is updated\n+\t\t * after a barrier is issued.\n+\t\t */\n+\t\t.ds_ring_sz = cpu_to_le32(cfg->ds_ring_sz),\n+\t\t.cxt_sts_ptr = cpu_to_le64(cxt_sts_ptr),\n+\t\t.write_index_ptr = cpu_to_le64(write_index_ptr),\n+\t};\n+\n+\tds_ring_ptr = FIELD_PREP(SDXI_CXT_CTL_VL, 1) |\n+\t\tFIELD_PREP(SDXI_CXT_CTL_QOS, cfg->qos) |\n+\t\tFIELD_PREP(SDXI_CXT_CTL_SE, cfg->se) |\n+\t\tFIELD_PREP(SDXI_CXT_CTL_CSA, cfg->csa) |\n+\t\tFIELD_PREP(SDXI_CXT_CTL_DS_RING_PTR,\n+\t\t\t cfg->ds_ring_ptr >> DESC_RING_BASE_PTR_SHIFT);\n+\t/* Ensure other fields are visible before hw sees vl=1. */\n+\tdma_wmb();\n+\tWRITE_ONCE(ctl->ds_ring_ptr, cpu_to_le64(ds_ring_ptr));\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * Logical representation of CXT_L1_ENT subfields.\n+ */\n+struct sdxi_cxt_L1_cfg {\n+\tdma_addr_t cxt_ctl_ptr;\n+\tdma_addr_t akey_ptr;\n+\tu32 cxt_pasid;\n+\tu32 opb_000_enb;\n+\tu16 max_buffer;\n+\tu8 akey_sz;\n+\tbool ka;\n+\tbool pv;\n+};\n+\n+static int configure_L1_entry(struct sdxi_cxt_L1_ent *ent,\n+\t\t\t const struct sdxi_cxt_L1_cfg *cfg)\n+{\n+\tu64 cxt_ctl_ptr, akey_ptr;\n+\tu32 misc0;\n+\n+\tif (WARN_ON_ONCE(!IS_ALIGNED(cfg->cxt_ctl_ptr, SZ_64)))\n+\t\treturn -EFAULT;\n+\tif (WARN_ON_ONCE(!IS_ALIGNED(cfg->akey_ptr, SZ_4K)))\n+\t\treturn -EFAULT;\n+\n+\takey_ptr = FIELD_PREP(SDXI_CXT_L1_ENT_AKEY_SZ, cfg->akey_sz) |\n+\t\tFIELD_PREP(SDXI_CXT_L1_ENT_AKEY_PTR,\n+\t\t\t cfg->akey_ptr >> L1_CXT_AKEY_PTR_SHIFT);\n+\n+\tmisc0 = FIELD_PREP(SDXI_CXT_L1_ENT_PASID, cfg->cxt_pasid) |\n+\t\tFIELD_PREP(SDXI_CXT_L1_ENT_MAX_BUFFER, cfg->max_buffer);\n+\n+\t*ent = (typeof(*ent)) {\n+\t\t/*\n+\t\t * cxt_ctl_ptr contains the validity bit and is\n+\t\t * updated after a barrier is issued.\n+\t\t */\n+\t\t.akey_ptr = cpu_to_le64(akey_ptr),\n+\t\t.misc0 = cpu_to_le32(misc0),\n+\t\t.opb_000_enb = cpu_to_le32(cfg->opb_000_enb),\n+\t};\n+\n+\tcxt_ctl_ptr = FIELD_PREP(SDXI_CXT_L1_ENT_VL, 1) |\n+\t\tFIELD_PREP(SDXI_CXT_L1_ENT_KA, cfg->ka) |\n+\t\tFIELD_PREP(SDXI_CXT_L1_ENT_PV, cfg->pv) |\n+\t\tFIELD_PREP(SDXI_CXT_L1_ENT_CXT_CTL_PTR,\n+\t\t\t cfg->cxt_ctl_ptr >> L1_CXT_CTRL_PTR_SHIFT);\n+\t/* Ensure other fields are visible before hw sees vl=1. */\n+\tdma_wmb();\n+\tWRITE_ONCE(ent->cxt_ctl_ptr, cpu_to_le64(cxt_ctl_ptr));\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * Make the context control structure hierarchy valid from the POV of\n+ * the SDXI implementation. This may eventually involve allocation of\n+ * a L1 table page, so it needs to be fallible.\n+ */\n+static int sdxi_publish_cxt(const struct sdxi_cxt *cxt)\n+{\n+\tstruct sdxi_cxt_ctl_cfg ctl_cfg;\n+\tstruct sdxi_cxt_L1_cfg L1_cfg;\n+\tstruct sdxi_cxt_L1_ent *ent;\n+\tu8 l1_idx;\n+\tint err;\n+\n+\tif (WARN_ONCE(cxt->id > cxt->sdxi->max_cxtid,\n+\t\t \"can't install cxt with id %u (limit %u)\",\n+\t\t cxt->id, cxt->sdxi->max_cxtid))\n+\t\treturn -EINVAL;\n+\n+\tctl_cfg = (typeof(ctl_cfg)) {\n+\t\t.se = 1,\n+\t\t.csa = 1,\n+\t\t.ds_ring_ptr = cxt->sq->ring_dma,\n+\t\t.ds_ring_sz = cxt->sq->ring_size >> 6,\n+\t\t.cxt_sts_ptr = cxt->sq->cxt_sts_dma,\n+\t\t.write_index_ptr = cxt->sq->write_index_dma,\n+\t};\n+\n+\terr = configure_cxt_ctl(cxt->cxt_ctl, &ctl_cfg);\n+\tif (err)\n+\t\treturn err;\n+\n+\tl1_idx = ID_TO_L1_INDEX(cxt->id);\n+\n+\tent = &cxt->sdxi->L1_table->entry[l1_idx];\n+\n+\tL1_cfg = (typeof(L1_cfg)) {\n+\t\t.ka = 1,\n+\t\t.pv = 0,\n+\t\t.cxt_ctl_ptr = cxt->cxt_ctl_dma,\n+\t\t.akey_sz = akey_table_order(cxt->akey_table),\n+\t\t.akey_ptr = cxt->akey_table_dma,\n+\t\t.cxt_pasid = IOMMU_NO_PASID,\n+\t\t.max_buffer = 11, /* 4GB */\n+\t\t.opb_000_enb = cxt->sdxi->op_grp_cap,\n+\t};\n+\n+\treturn configure_L1_entry(ent, &L1_cfg);\n+\t/* todo: need to send DSC_CXT_UPD to admin */\n+}\n+\n static void free_admin_cxt(void *ptr)\n {\n \tstruct sdxi_dev *sdxi = ptr;\n@@ -115,13 +267,23 @@ static void free_admin_cxt(void *ptr)\n \n int sdxi_admin_cxt_init(struct sdxi_dev *sdxi)\n {\n+\tint err;\n+\tstruct sdxi_sq *sq;\n+\n \tstruct sdxi_cxt *cxt __free(sdxi_cxt) = sdxi_alloc_cxt(sdxi);\n \tif (!cxt)\n \t\treturn -ENOMEM;\n \n+\tsq = cxt->sq;\n+\t/* SDXI 1.0 4.1.8.4.b: Set CXT_STS.state to CXTV_RUN. */\n+\tsq->cxt_sts->state = FIELD_PREP(SDXI_CXT_STS_STATE, CXTV_RUN);\n \tcxt->id = SDXI_ADMIN_CXT_ID;\n \tcxt->db = sdxi->dbs + cxt->id * sdxi->db_stride;\n \n+\terr = sdxi_publish_cxt(cxt);\n+\tif (err)\n+\t\treturn err;\n+\n \tsdxi->admin_cxt = no_free_ptr(cxt);\n \n \treturn devm_add_action_or_reset(sdxi_to_dev(sdxi), free_admin_cxt, sdxi);\ndiff --git a/drivers/dma/sdxi/context.h b/drivers/dma/sdxi/context.h\nindex 800b4ead1dd9..bbde1fd49af3 100644\n--- a/drivers/dma/sdxi/context.h\n+++ b/drivers/dma/sdxi/context.h\n@@ -20,6 +20,13 @@ struct sdxi_akey_table {\n \tstruct sdxi_akey_ent entry[SZ_4K / sizeof(struct sdxi_akey_ent)];\n };\n \n+/* For encoding the akey table size in CXT_L1_ENT's akey_sz. */\n+static inline u8 akey_table_order(const struct sdxi_akey_table *tbl)\n+{\n+\tstatic_assert(sizeof(*tbl) == SZ_4K);\n+\treturn 0;\n+}\n+\n /* Submission Queue */\n struct sdxi_sq {\n \tu32 ring_entries;\ndiff --git a/drivers/dma/sdxi/hw.h b/drivers/dma/sdxi/hw.h\nindex b66eb22f7f90..46424376f26f 100644\n--- a/drivers/dma/sdxi/hw.h\n+++ b/drivers/dma/sdxi/hw.h\n@@ -45,8 +45,16 @@ static_assert(sizeof(struct sdxi_cxt_L2_table) == 4096);\n /* SDXI 1.0 Table 3-3: Context Level 1 Table Entry (CXT_L1_ENT) */\n struct sdxi_cxt_L1_ent {\n \t__le64 cxt_ctl_ptr;\n+#define SDXI_CXT_L1_ENT_VL BIT_ULL(0)\n+#define SDXI_CXT_L1_ENT_KA BIT_ULL(1)\n+#define SDXI_CXT_L1_ENT_PV BIT_ULL(2)\n+#define SDXI_CXT_L1_ENT_CXT_CTL_PTR GENMASK_ULL(63, 6)\n \t__le64 akey_ptr;\n+#define SDXI_CXT_L1_ENT_AKEY_SZ GENMASK_ULL(3, 0)\n+#define SDXI_CXT_L1_ENT_AKEY_PTR GENMASK_ULL(63, 12)\n \t__le32 misc0;\n+#define SDXI_CXT_L1_ENT_PASID GENMASK(19, 0)\n+#define SDXI_CXT_L1_ENT_MAX_BUFFER GENMASK(23, 20)\n \t__le32 opb_000_enb;\n \t__u8 rsvd_0[8];\n } __packed;\n@@ -62,10 +70,17 @@ static_assert(sizeof(struct sdxi_cxt_L1_table) == 4096);\n /* SDXI 1.0 Table 3-4: Context Control (CXT_CTL) */\n struct sdxi_cxt_ctl {\n \t__le64 ds_ring_ptr;\n+#define SDXI_CXT_CTL_VL BIT_ULL(0)\n+#define SDXI_CXT_CTL_QOS GENMASK_ULL(3, 2)\n+#define SDXI_CXT_CTL_SE BIT_ULL(4)\n+#define SDXI_CXT_CTL_CSA BIT_ULL(5)\n+#define SDXI_CXT_CTL_DS_RING_PTR GENMASK_ULL(63, 6)\n \t__le32 ds_ring_sz;\n \t__u8 rsvd_0[4];\n \t__le64 cxt_sts_ptr;\n+#define SDXI_CXT_CTL_CXT_STS_PTR GENMASK_ULL(63, 4)\n \t__le64 write_index_ptr;\n+#define SDXI_CXT_CTL_WRITE_INDEX_PTR GENMASK_ULL(63, 3)\n \t__u8 rsvd_1[32];\n } __packed;\n static_assert(sizeof(struct sdxi_cxt_ctl) == 64);\ndiff --git a/drivers/dma/sdxi/sdxi.h b/drivers/dma/sdxi/sdxi.h\nindex 4ef893ae15f3..bbc14364a5c9 100644\n--- a/drivers/dma/sdxi/sdxi.h\n+++ b/drivers/dma/sdxi/sdxi.h\n@@ -17,6 +17,15 @@\n \n #define SDXI_DRV_DESC\t\t\"SDXI driver\"\n \n+#define ID_TO_L1_INDEX(id)\t((id) & 0x7F)\n+\n+#define DESC_RING_BASE_PTR_SHIFT\t6\n+#define CXT_STATUS_PTR_SHIFT\t\t4\n+#define WRT_INDEX_PTR_SHIFT\t\t3\n+\n+#define L1_CXT_CTRL_PTR_SHIFT\t\t6\n+#define L1_CXT_AKEY_PTR_SHIFT\t\t12\n+\n struct sdxi_dev;\n \n /**\n", "prefixes": [ "08/23" ] }