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GET /api/patches/2220212/?format=api
{ "id": 2220212, "url": "http://patchwork.ozlabs.org/api/patches/2220212/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260406155717.880246-4-den@valinux.co.jp/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260406155717.880246-4-den@valinux.co.jp>", "list_archive_url": null, "date": "2026-04-06T15:57:13", "name": "[v13,3/7] PCI: dwc: ep: Expose integrated eDMA resources via EPC aux-resource API", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3fe2ad9acb2c236add5abb91ddef1b0ac5a98f5f", "submitter": { "id": 91573, "url": "http://patchwork.ozlabs.org/api/people/91573/?format=api", "name": "Koichiro Den", "email": "den@valinux.co.jp" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260406155717.880246-4-den@valinux.co.jp/mbox/", "series": [ { "id": 498879, "url": "http://patchwork.ozlabs.org/api/series/498879/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=498879", "date": "2026-04-06T15:57:10", "name": "PCI: endpoint: pci-ep-msi: Add embedded doorbell fallback", "version": 13, "mbox": "http://patchwork.ozlabs.org/series/498879/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220212/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220212/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51958-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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dkim=pass header.d=valinux.co.jp; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=valinux.co.jp;\n s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=m+YcyJrVo9PcebSFe1ize+OnskN6MubzU5t/jCWFzdE=;\n b=MIBRLviaCd0lSnxkc+aRBsPH/i2WfVN4435m54CQkgl9VlCyktAshl5Cv7OTAOgswnEMmGvhYa/Zeem5RZ6pxScP8fLYrdozyJO1ZRQcNkuxzw/2UfBE/fIj+fd/ulnNKMYNrJffee6rVEhVdL5osh3IyfhgzXI/MLQy7i1TYEA=", "From": "Koichiro Den <den@valinux.co.jp>", "To": "Jingoo Han <jingoohan1@gmail.com>,\n Manivannan Sadhasivam <mani@kernel.org>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>,\n Kishon Vijay Abraham I <kishon@kernel.org>, Jon Mason <jdmason@kudzu.us>,\n Dave Jiang <dave.jiang@intel.com>, Allen Hubbe <allenbh@gmail.com>,\n Niklas Cassel <cassel@kernel.org>, Frank Li <Frank.Li@nxp.com>,\n Bhanu Seshu Kumar Valluri <bhanuseshukumar@gmail.com>,\n Marco Crivellari <marco.crivellari@suse.com>,\n Shin'ichiro Kawasaki <shinichiro.kawasaki@wdc.com>,\n Manikanta Maddireddy <mmaddireddy@nvidia.com>", "Cc": "linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tntb@lists.linux.dev", "Subject": "[PATCH v13 3/7] PCI: dwc: ep: Expose integrated eDMA resources via\n EPC aux-resource API", "Date": "Tue, 7 Apr 2026 00:57:13 +0900", "Message-ID": "<20260406155717.880246-4-den@valinux.co.jp>", "X-Mailer": "git-send-email 2.51.0", "In-Reply-To": "<20260406155717.880246-1-den@valinux.co.jp>", "References": "<20260406155717.880246-1-den@valinux.co.jp>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "TYCP286CA0043.JPNP286.PROD.OUTLOOK.COM\n (2603:1096:400:29d::14) To TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM\n (2603:1096:405:38f::10)", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", 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"X-OriginatorOrg": "valinux.co.jp", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 42edc950-ab05-4642-532d-08de93f53191", "X-MS-Exchange-CrossTenant-AuthSource": "TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Apr 2026 15:57:24.1578\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "7a57bee8-f73d-4c5f-a4f7-d72c91c8c111", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n kZZiVPYjWWWyQDgxk/JJrqcUorIKp38TkevwgZ1eas6gzLtpOfe46cR/4hHJQUe3NjXH5Qqm0UiOpbYo8XaHXQ==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "TYYP286MB4187" }, "content": "Implement the EPC aux-resource API for DesignWare endpoint controllers\nwith integrated eDMA.\n\nCurrently, only report an interrupt-emulation doorbell register\n(PCI_EPC_AUX_DOORBELL_MMIO), including its Linux IRQ and the write data\nneeded to trigger the interrupt.\n\nIf the DMA controller MMIO window is already exposed via a\nplatform-owned fixed BAR subregion, also provide the BAR number and\noffset so EPF drivers can reuse it without reprogramming the BAR.\n\nSigned-off-by: Koichiro Den <den@valinux.co.jp>\n---\nChanges in v13:\n - Updated to use the revised direct-count aux-resource API.\n\n .../pci/controller/dwc/pcie-designware-ep.c | 119 ++++++++++++++++++\n 1 file changed, 119 insertions(+)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c\nindex 386bfb7b2bf6..c3c354265307 100644\n--- a/drivers/pci/controller/dwc/pcie-designware-ep.c\n+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c\n@@ -9,6 +9,7 @@\n #include <linux/align.h>\n #include <linux/bitfield.h>\n #include <linux/of.h>\n+#include <linux/overflow.h>\n #include <linux/platform_device.h>\n \n #include \"pcie-designware.h\"\n@@ -817,6 +818,122 @@ dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no)\n \treturn ep->ops->get_features(ep);\n }\n \n+static const struct pci_epc_bar_rsvd_region *\n+dw_pcie_ep_find_bar_rsvd_region(struct dw_pcie_ep *ep,\n+\t\t\t\tenum pci_epc_bar_rsvd_region_type type,\n+\t\t\t\tenum pci_barno *bar,\n+\t\t\t\tresource_size_t *bar_offset)\n+{\n+\tconst struct pci_epc_features *features;\n+\tconst struct pci_epc_bar_desc *bar_desc;\n+\tconst struct pci_epc_bar_rsvd_region *r;\n+\tint i, j;\n+\n+\tif (!ep->ops->get_features)\n+\t\treturn NULL;\n+\n+\tfeatures = ep->ops->get_features(ep);\n+\tif (!features)\n+\t\treturn NULL;\n+\n+\tfor (i = BAR_0; i <= BAR_5; i++) {\n+\t\tbar_desc = &features->bar[i];\n+\n+\t\tif (!bar_desc->nr_rsvd_regions || !bar_desc->rsvd_regions)\n+\t\t\tcontinue;\n+\n+\t\tfor (j = 0; j < bar_desc->nr_rsvd_regions; j++) {\n+\t\t\tr = &bar_desc->rsvd_regions[j];\n+\n+\t\t\tif (r->type != type)\n+\t\t\t\tcontinue;\n+\n+\t\t\tif (bar)\n+\t\t\t\t*bar = i;\n+\t\t\tif (bar_offset)\n+\t\t\t\t*bar_offset = r->offset;\n+\t\t\treturn r;\n+\t\t}\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static int\n+dw_pcie_ep_get_aux_resources_count(struct pci_epc *epc, u8 func_no,\n+\t\t\t\t u8 vfunc_no)\n+{\n+\tstruct dw_pcie_ep *ep = epc_get_drvdata(epc);\n+\tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n+\tstruct dw_edma_chip *edma = &pci->edma;\n+\n+\tif (!pci->edma_reg_size)\n+\t\treturn 0;\n+\n+\tif (edma->db_offset == ~0)\n+\t\treturn 0;\n+\n+\treturn 1;\n+}\n+\n+static int\n+dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 func_no, u8 vfunc_no,\n+\t\t\t struct pci_epc_aux_resource *resources,\n+\t\t\t int num_resources)\n+{\n+\tstruct dw_pcie_ep *ep = epc_get_drvdata(epc);\n+\tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n+\tconst struct pci_epc_bar_rsvd_region *rsvd;\n+\tstruct dw_edma_chip *edma = &pci->edma;\n+\tenum pci_barno dma_ctrl_bar = NO_BAR;\n+\tresource_size_t db_offset = edma->db_offset;\n+\tresource_size_t dma_ctrl_bar_offset = 0;\n+\tresource_size_t dma_reg_size;\n+\tint count;\n+\n+\tcount = dw_pcie_ep_get_aux_resources_count(epc, func_no, vfunc_no);\n+\tif (count < 0)\n+\t\treturn count;\n+\n+\tif (num_resources < count)\n+\t\treturn -ENOSPC;\n+\n+\tif (!count)\n+\t\treturn 0;\n+\n+\tdma_reg_size = pci->edma_reg_size;\n+\n+\trsvd = dw_pcie_ep_find_bar_rsvd_region(ep,\n+\t\t\t\t\t PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO,\n+\t\t\t\t\t &dma_ctrl_bar,\n+\t\t\t\t\t &dma_ctrl_bar_offset);\n+\tif (rsvd && rsvd->size < dma_reg_size)\n+\t\tdma_reg_size = rsvd->size;\n+\n+\t/*\n+\t * For interrupt-emulation doorbells, report a standalone resource\n+\t * instead of bundling it into the DMA controller MMIO resource.\n+\t */\n+\tif (range_end_overflows_t(resource_size_t, db_offset,\n+\t\t\t\t sizeof(u32), dma_reg_size))\n+\t\treturn -EINVAL;\n+\n+\tresources[0] = (struct pci_epc_aux_resource) {\n+\t\t.type = PCI_EPC_AUX_DOORBELL_MMIO,\n+\t\t.phys_addr = pci->edma_reg_phys + db_offset,\n+\t\t.size = sizeof(u32),\n+\t\t.bar = dma_ctrl_bar,\n+\t\t.bar_offset = dma_ctrl_bar != NO_BAR ?\n+\t\t\t\tdma_ctrl_bar_offset + db_offset : 0,\n+\t\t.u.db_mmio = {\n+\t\t\t.irq = edma->db_irq,\n+\t\t\t.data = 0, /* write 0 to assert */\n+\t\t},\n+\t};\n+\n+\treturn 0;\n+}\n+\n static const struct pci_epc_ops epc_ops = {\n \t.write_header\t\t= dw_pcie_ep_write_header,\n \t.set_bar\t\t= dw_pcie_ep_set_bar,\n@@ -832,6 +949,8 @@ static const struct pci_epc_ops epc_ops = {\n \t.start\t\t\t= dw_pcie_ep_start,\n \t.stop\t\t\t= dw_pcie_ep_stop,\n \t.get_features\t\t= dw_pcie_ep_get_features,\n+\t.get_aux_resources_count\t= dw_pcie_ep_get_aux_resources_count,\n+\t.get_aux_resources\t= dw_pcie_ep_get_aux_resources,\n };\n \n /**\n", "prefixes": [ "v13", "3/7" ] }