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GET /api/patches/2220204/?format=api
{ "id": 2220204, "url": "http://patchwork.ozlabs.org/api/patches/2220204/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406154935.144674-5-djordje.todorovic@htecgroup.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260406154935.144674-5-djordje.todorovic@htecgroup.com>", "list_archive_url": null, "date": "2026-04-06T15:49:42", "name": "[v6,4/7] target/riscv: Implement runtime data endianness via MSTATUS bits", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f032e9e903d6305a247a6d4e640276bccd331ff1", "submitter": { "id": 90738, "url": "http://patchwork.ozlabs.org/api/people/90738/?format=api", "name": "Djordje Todorovic", "email": "Djordje.Todorovic@htecgroup.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406154935.144674-5-djordje.todorovic@htecgroup.com/mbox/", "series": [ { "id": 498877, "url": "http://patchwork.ozlabs.org/api/series/498877/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498877", "date": "2026-04-06T15:49:42", "name": "Add RISC-V big-endian target support", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/498877/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220204/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220204/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass 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b=r/Heu4SNvq2y24x195D19SyW1bRtzuzQxFvvlS/YKKjZ/x2ZwrRFUvpUuyin9/x3+kN8/PtbyAO2ybWk+d+pTUy4anASePRrpjK74XIcNEwjX1XMQ1+M2tpLxDgxX+BSnh2kTTV+sRiJVxIQkTlvrfOZwUY656umYmagWUa50x/Dnyw0YvnUtQn+Na3Pcu16i5nuvuoz5bKIdeh/j7/STm8pvvK5DxCbLw2kphRo1RDUNvogUZM5bI2KkSi7CffZN4kvN6vJc+Ns+0aqdOSGKvJA32v/S6biBfj+GRkYFYkZGPWVXDyR1Kq9jFyXHjysO08grG4qcf6j+g3JPeDRvA==", "From": "Djordje Todorovic <Djordje.Todorovic@htecgroup.com>", "To": "\"qemu-devel@nongnu.org\" <qemu-devel@nongnu.org>", "CC": "\"qemu-riscv@nongnu.org\" <qemu-riscv@nongnu.org>, \"cfu@mips.com\"\n <cfu@mips.com>, \"mst@redhat.com\" <mst@redhat.com>,\n \"marcel.apfelbaum@gmail.com\" <marcel.apfelbaum@gmail.com>,\n \"dbarboza@ventanamicro.com\" <dbarboza@ventanamicro.com>, \"philmd@linaro.org\"\n <philmd@linaro.org>, \"alistair23@gmail.com\" <alistair23@gmail.com>,\n \"thuth@redhat.com\" <thuth@redhat.com>, Djordje Todorovic\n <Djordje.Todorovic@htecgroup.com>", "Subject": "[PATCH v6 4/7] target/riscv: Implement runtime data endianness via\n MSTATUS bits", "Thread-Topic": "[PATCH v6 4/7] target/riscv: Implement runtime data endianness\n via MSTATUS bits", "Thread-Index": "AQHcxdz70J0jqOWNlUqTEQuyJ5XzXw==", "Date": "Mon, 6 Apr 2026 15:49:42 +0000", "Message-ID": "<20260406154935.144674-5-djordje.todorovic@htecgroup.com>", "References": "<20260406154935.144674-1-djordje.todorovic@htecgroup.com>", "In-Reply-To": "<20260406154935.144674-1-djordje.todorovic@htecgroup.com>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "authentication-results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=htecgroup.com header.i=@htecgroup.com\n header.a=rsa-sha256 header.s=selector1 header.b=r/Heu4SN;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n 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"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Implement runtime big-endian data support by reading the MSTATUS\nUBE/SBE/MBE bits to determine data endianness per privilege level.\n\nThe key changes are:\n\n- Add riscv_cpu_data_is_big_endian() helper in cpu.h that checks\n the appropriate MSTATUS endianness bit based on current privilege\n level (MBE for M-mode, SBE for S-mode, UBE for U-mode).\n\n- Update mo_endian() in translate.c to return MO_BE or MO_LE based\n on a new 'big_endian' field in DisasContext, rather than the\n previous hardcoded MO_TE.\n\n- Update mo_endian_env() in op_helper.c to call the new helper,\n giving hypervisor load/store helpers correct runtime endianness.\n\n- Pack the endianness flag into cs_base bit 32 (alongside misa_ext\n in bits 0-25) in riscv_get_tb_cpu_state(), ensuring translation\n blocks are correctly separated by data endianness.\n\nNote: instruction fetches continue to use MO_LE unconditionally\n(from the previous patch), as RISC-V instructions are always\nlittle-endian per the ISA specification.\n\nSigned-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>\n---\n target/riscv/cpu.h | 28 ++++++++++++++++++++++++++++\n target/riscv/internals.h | 9 +--------\n target/riscv/tcg/tcg-cpu.c | 7 ++++++-\n target/riscv/translate.c | 13 +++++--------\n 4 files changed, 40 insertions(+), 17 deletions(-)", "diff": "diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 35d1f6362c..ef870d05b3 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -703,6 +703,12 @@ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1)\n FIELD(TB_FLAGS, PM_PMM, 29, 2)\n FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1)\n \n+/*\n+ * cs_base carries misa_ext (bits 0-25) plus additional flags.\n+ * Bit 32 is used for data endianness since TB_FLAGS has no free bits.\n+ */\n+#define TB_CSBASE_BIG_ENDIAN (1ULL << 32)\n+\n #ifdef TARGET_RISCV32\n #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)\n #else\n@@ -718,6 +724,28 @@ static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env)\n return &env_archcpu(env)->cfg;\n }\n \n+/*\n+ * Return true if data accesses are big-endian for the current privilege\n+ * level, based on the MSTATUS MBE/SBE/UBE bits.\n+ */\n+static inline bool riscv_cpu_data_is_big_endian(CPURISCVState *env)\n+{\n+#if defined(CONFIG_USER_ONLY)\n+ return false;\n+#else\n+ switch (env->priv) {\n+ case PRV_M:\n+ return env->mstatus & MSTATUS_MBE;\n+ case PRV_S:\n+ return env->mstatus & MSTATUS_SBE;\n+ case PRV_U:\n+ return env->mstatus & MSTATUS_UBE;\n+ default:\n+ g_assert_not_reached();\n+ }\n+#endif\n+}\n+\n #if !defined(CONFIG_USER_ONLY)\n static inline int cpu_address_mode(CPURISCVState *env)\n {\ndiff --git a/target/riscv/internals.h b/target/riscv/internals.h\nindex 460346dd6d..e2f0334da8 100644\n--- a/target/riscv/internals.h\n+++ b/target/riscv/internals.h\n@@ -64,14 +64,7 @@ static inline bool mmuidx_2stage(int mmu_idx)\n \n static inline MemOp mo_endian_env(CPURISCVState *env)\n {\n- /*\n- * A couple of bits in MSTATUS set the endianness:\n- * - MSTATUS_UBE (User-mode),\n- * - MSTATUS_SBE (Supervisor-mode),\n- * - MSTATUS_MBE (Machine-mode)\n- * but we don't implement that yet.\n- */\n- return MO_LE;\n+ return riscv_cpu_data_is_big_endian(env) ? MO_BE : MO_LE;\n }\n \n /* share data between vector helpers and decode code */\ndiff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex 3407191c22..d73b749bae 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -189,10 +189,15 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)\n flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env));\n flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext);\n \n+ uint64_t cs_base = env->misa_ext;\n+ if (riscv_cpu_data_is_big_endian(env)) {\n+ cs_base |= TB_CSBASE_BIG_ENDIAN;\n+ }\n+\n return (TCGTBCPUState){\n .pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc,\n .flags = flags,\n- .cs_base = env->misa_ext,\n+ .cs_base = cs_base,\n };\n }\n \ndiff --git a/target/riscv/translate.c b/target/riscv/translate.c\nindex 5df5b73849..77f36906e8 100644\n--- a/target/riscv/translate.c\n+++ b/target/riscv/translate.c\n@@ -119,6 +119,8 @@ typedef struct DisasContext {\n bool fcfi_lp_expected;\n /* zicfiss extension, if shadow stack was enabled during TB gen */\n bool bcfi_enabled;\n+ /* Data endianness from MSTATUS UBE/SBE/MBE */\n+ MemOp mo_endianness;\n } DisasContext;\n \n static inline bool has_ext(DisasContext *ctx, uint32_t ext)\n@@ -128,14 +130,7 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)\n \n static inline MemOp mo_endian(DisasContext *ctx)\n {\n- /*\n- * A couple of bits in MSTATUS set the endianness:\n- * - MSTATUS_UBE (User-mode),\n- * - MSTATUS_SBE (Supervisor-mode),\n- * - MSTATUS_MBE (Machine-mode)\n- * but we don't implement that yet.\n- */\n- return MO_LE;\n+ return ctx->mo_endianness;\n }\n \n #ifdef TARGET_RISCV32\n@@ -1346,6 +1341,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)\n ctx->zero = tcg_constant_tl(0);\n ctx->virt_inst_excp = false;\n ctx->decoders = cpu->decoders;\n+ ctx->mo_endianness = (ctx->base.tb->cs_base & TB_CSBASE_BIG_ENDIAN)\n+ ? MO_BE : MO_LE;\n }\n \n static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)\n", "prefixes": [ "v6", "4/7" ] }