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Update a patch.
put:
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GET /api/patches/2220202/?format=api
{ "id": 2220202, "url": "http://patchwork.ozlabs.org/api/patches/2220202/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260406-clk-pwm-gpio-v1-1-40d2f3a20aff@radxa.com/", "project": { "id": 38, "url": "http://patchwork.ozlabs.org/api/projects/38/?format=api", "name": "Linux PWM development", "link_name": "linux-pwm", "list_id": "linux-pwm.vger.kernel.org", "list_email": "linux-pwm@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260406-clk-pwm-gpio-v1-1-40d2f3a20aff@radxa.com>", "list_archive_url": null, "date": "2026-04-06T15:50:01", "name": "[1/2] dt-bindings: pwm: clk-pwm: add optional GPIO and pinctrl properties", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8ca74828017327ffb61d6a1afd66cbec8f0d0b6f", "submitter": { "id": 90715, "url": "http://patchwork.ozlabs.org/api/people/90715/?format=api", "name": "Xilin Wu", "email": "sophon@radxa.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260406-clk-pwm-gpio-v1-1-40d2f3a20aff@radxa.com/mbox/", "series": [ { "id": 498878, "url": "http://patchwork.ozlabs.org/api/series/498878/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=498878", "date": "2026-04-06T15:50:00", "name": "pwm: clk-pwm: Add GPIO support for constant output levels", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498878/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220202/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220202/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pwm+bounces-8496-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pwm@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pwm+bounces-8496-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=54.206.16.166", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=radxa.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=radxa.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fqDMR3N0Lz1yFt\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 07 Apr 2026 01:51:15 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 70547300EF91\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 6 Apr 2026 15:51:08 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 81176330648;\n\tMon, 6 Apr 2026 15:51:06 +0000 (UTC)", "from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CD1F2D0614;\n\tMon, 6 Apr 2026 15:51:02 +0000 (UTC)", "from [192.168.30.32] ( [116.234.14.100])\n\tby bizesmtp.qq.com (ESMTP) with\n\tid ; Mon, 06 Apr 2026 23:50:09 +0800 (CST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775490666; cv=none;\n b=nVUSpRjPj2nitlMjNGxt/L3JV3NMWfGS+tZdoXj7vNQQW0QYeyR2S1M4WQr2XLgh/CFufA+uzbtdykAhXqPp9P/rET8YHohSev2cY2GtEsB+Phm9xObyCNzwQTNxcZdtMtdEH4+ECrlgA65cRNQcgaVKw1t6NU4YrA31YPL0nIk=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775490666; c=relaxed/simple;\n\tbh=hyoSGNKO8z6d1axQ29oBEAL7xl1kP5y9LqcBAulHLMQ=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=U/TRO5IFZ/jcP9G1pndzGryIkcqoVZMzlJd6VKVTNgjQ799n0mHj65p8Xd3vWU0sTknBX/hQnEk784C1HfA9/DWl9GXDlIbYXtZJx3Sn22rdGJ03qOQZINnwVOzmOHxNruon8UttAt54xg7S8jO6D+mW8HI+pccXQSHFpuljBIA=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=radxa.com;\n spf=pass smtp.mailfrom=radxa.com; arc=none smtp.client-ip=54.206.16.166", "X-QQ-mid": "zesmtpsz5t1775490611t88c1fc21", "X-QQ-Originating-IP": "O33DW5ODZGKddTF7xRQ7Ge2Lc2xYEoUlTwU0BzXScsQ=", "X-QQ-SSF": "0000000000000000000000000000000", "X-QQ-GoodBg": "0", "X-BIZMAIL-ID": "13515617376988754846", "EX-QQ-RecipientCnt": "10", "From": "Xilin Wu <sophon@radxa.com>", "Date": "Mon, 06 Apr 2026 23:50:01 +0800", "Subject": "[PATCH 1/2] dt-bindings: pwm: clk-pwm: add optional GPIO and\n pinctrl properties", "Precedence": "bulk", "X-Mailing-List": "linux-pwm@vger.kernel.org", "List-Id": "<linux-pwm.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pwm+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pwm+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260406-clk-pwm-gpio-v1-1-40d2f3a20aff@radxa.com>", "References": "<20260406-clk-pwm-gpio-v1-0-40d2f3a20aff@radxa.com>", "In-Reply-To": "<20260406-clk-pwm-gpio-v1-0-40d2f3a20aff@radxa.com>", "To": "=?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <ukleinek@kernel.org>,\n Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>, Nikita Travkin <nikita@trvn.ru>", "Cc": "linux-pwm@vger.kernel.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n Xilin Wu <sophon@radxa.com>", "X-Mailer": "b4 0.15.1", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=2512; i=sophon@radxa.com;\n h=from:subject:message-id; bh=hyoSGNKO8z6d1axQ29oBEAL7xl1kP5y9LqcBAulHLMQ=;\n b=owGbwMvMwCVmdFg0fe08Iz/G02pJDJmXr+lpz6zwPig603O36Y01rG92GuQbLL22/F3exIhDM\n +ZqJnM97ihlYRDjYpAVU2RRiGeYy16Ze+2pWKkezBxWJpAhDFycAjARfilGhnMfXbY9Y5qecXqP\n bpyVtt9TtUtui1+Z2vj5BE1h+3tonSojQ2Nl8f3PZayTn729HX3u4uSXczjWC8xJPS4Verb445d\n gXX4A", "X-Developer-Key": "i=sophon@radxa.com; a=openpgp;\n fpr=205F009D07796DD6E516752E32C31567AD9E324E", "X-QQ-SENDSIZE": "520", "Feedback-ID": "zesmtpsz:radxa.com:qybglogicsvrsz:qybglogicsvrsz3b-0", "X-QQ-XMAILINFO": "Ob+yvR0lmunCxlEdJ5yqfcfe8D1O7uVqXJxhN3Hhst+k/5IQeBIBSRM3\n\t+3E2ec4Wc1MlrG32fFTxY3WUlFtXsOcmUyBH1eShzav/1q0vFc9LJtvujKXsJKMCXk4RkbN\n\tp4kgrmLqTRTTn8qYPKoRv5mzJeZI71rL7Wi/lIN73AWDhP4Vk7qFY1EX4H1cDW5kiBU8jUQ\n\tM2c+nmM7qNb3Q3U2KcAcdlhSStCvXYu+KWU4dc+2vVcl6KgkolxVRJHpr6JGRAa0nMGxlIy\n\tJq37eEkjz3nmOZ49UfS9bs24pmUFKh23V6+hLKsaMEVY4zenBrNzDRaF97r8IBygcTwKbjA\n\tPON12jYLZYkBu/0jJeZm1x/tEvQBDO4GgBRVM/zGS4MOyKEYRbf6Xk9HJasdrcdqChsA9w6\n\t+gclveBuOMOPqq7Q+8wc8Znboi3/YTWAo3c3i4QvG3vVaz+mujYO2gDkSbtgpLz3UmUgDX8\n\tHwS1UeW731icaVKqclJIZ1D3cPinN0mRtNvrqF5K7d0lbZ6ebpMmzXI6MmnUnKy/ruAORQl\n\tTSaoJYNg0zzL323Zbp2Xhc568VXFK+UIwhA+dqu6Wq/Bv2s3xdwCVwgSOLuqQNFv2f9sc4L\n\tMoXQhHCuHruYVfcIAUBTq2Gk3bfwt2tWpPTssqSQvh/0WEYBENK05ylu+q3sRNVcD2CaXuU\n\th2qipZP6kBzkvCkQuNoVSKIiMMXg3giiUvMmyWsXJDrAG32Mot3cUmnNvhjg5/uw0Y+sdnB\n\t6jAmsZ7g5x8oNXKR1FN742ULKglIjP8sBTKLA/nHYosk9FJjWRM7vP9vW+6eVsXQoInOr7g\n\tvwdG7Y+HCXxE52sD/A/L22PWKBw1yn2/ZzTTTm2nK8JOLaOCGMCb9mSjwOBN5bIFVt1Goek\n\tg671OtWHJcdBAJR7gAPSUrLTju8vFvSOX6xexrOKrBdsQJJrea1JDclGeTHD4vFjWeQHakX\n\tH9T8ZAikdH60rzfzly0H9wfXzBavhQduqvJiA3EweqTPMticSePv9gcxV1EaQzwkVp020ig\n\tVuKU+cCdgKOEG8dM4BIZKWfwCeu4vzcVctX8lIs7xw0/rvkpVIvBAZfhFvF9qErQFQ58nWp\n\tnKcX6iTvtlNgiCNMz5YtJE/AC2sRysPqQ==", "X-QQ-XMRINFO": "Mp0Kj//9VHAxzExpfF+O8yhSrljjwrznVg==", "X-QQ-RECHKSPAM": "0" }, "content": "The clk-pwm driver cannot produce constant output levels (0% or 100%\nduty cycle, or disabled state) through the clock hardware alone - the\nactual pin level when the clock is off is undefined and\nhardware-dependent.\n\nDocument optional gpios, pinctrl-names, pinctrl-0, and pinctrl-1\nproperties that allow the driver to switch the pin between clock\nfunction mux (for normal PWM output) and GPIO mode (to drive a\ndeterministic constant level).\n\nSigned-off-by: Xilin Wu <sophon@radxa.com>\n---\n Documentation/devicetree/bindings/pwm/clk-pwm.yaml | 36 +++++++++++++++++++++-\n 1 file changed, 35 insertions(+), 1 deletion(-)", "diff": "diff --git a/Documentation/devicetree/bindings/pwm/clk-pwm.yaml b/Documentation/devicetree/bindings/pwm/clk-pwm.yaml\nindex ec1768291503..2a0e3e02d27b 100644\n--- a/Documentation/devicetree/bindings/pwm/clk-pwm.yaml\n+++ b/Documentation/devicetree/bindings/pwm/clk-pwm.yaml\n@@ -15,6 +15,11 @@ description: |\n It's often possible to control duty-cycle of such clocks which makes them\n suitable for generating PWM signal.\n \n+ Optionally, a GPIO and pinctrl states can be provided. When a constant\n+ output level is needed (0%, 100%, or disabled), the pin is switched to\n+ GPIO mode to drive the level directly. For normal PWM output the pin is\n+ switched back to its clock function mux.\n+\n allOf:\n - $ref: pwm.yaml#\n \n@@ -29,6 +34,26 @@ properties:\n \"#pwm-cells\":\n const: 2\n \n+ gpios:\n+ description:\n+ Optional GPIO used to drive a constant level when the PWM output is\n+ disabled or set to 0% / 100% duty cycle. When provided, pinctrl states\n+ \"default\" (clock mux) and \"gpio\" must also be defined.\n+ maxItems: 1\n+\n+ pinctrl-names: true\n+\n+ pinctrl-0:\n+ description: Pin configuration for clock function mux (normal PWM).\n+ maxItems: 1\n+\n+ pinctrl-1:\n+ description: Pin configuration for GPIO mode (constant level output).\n+ maxItems: 1\n+\n+dependencies:\n+ gpios: [ pinctrl-0, pinctrl-1 ]\n+\n unevaluatedProperties: false\n \n required:\n@@ -41,6 +66,15 @@ examples:\n compatible = \"clk-pwm\";\n #pwm-cells = <2>;\n clocks = <&gcc 0>;\n- pinctrl-names = \"default\";\n+ };\n+\n+ - |\n+ pwm {\n+ compatible = \"clk-pwm\";\n+ #pwm-cells = <2>;\n+ clocks = <&gcc 0>;\n+ pinctrl-names = \"default\", \"gpio\";\n pinctrl-0 = <&pwm_clk_flash_default>;\n+ pinctrl-1 = <&pwm_clk_flash_gpio>;\n+ gpios = <&tlmm 32 0>;\n };\n", "prefixes": [ "1/2" ] }