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GET /api/patches/2220196/?format=api
{ "id": 2220196, "url": "http://patchwork.ozlabs.org/api/patches/2220196/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406154935.144674-6-djordje.todorovic@htecgroup.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260406154935.144674-6-djordje.todorovic@htecgroup.com>", "list_archive_url": null, "date": "2026-04-06T15:49:42", "name": "[v6,5/7] hw/riscv: Make boot code endianness-aware at runtime", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ba0ccfb5dd48d0afcbd389d69a86934930c7dc8a", "submitter": { "id": 90738, "url": "http://patchwork.ozlabs.org/api/people/90738/?format=api", "name": "Djordje Todorovic", "email": "Djordje.Todorovic@htecgroup.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406154935.144674-6-djordje.todorovic@htecgroup.com/mbox/", "series": [ { "id": 498877, "url": "http://patchwork.ozlabs.org/api/series/498877/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498877", "date": "2026-04-06T15:49:42", "name": "Add RISC-V big-endian target support", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/498877/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220196/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220196/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=htecgroup.com header.i=@htecgroup.com\n header.a=rsa-sha256 header.s=selector1 header.b=u7rMRZLK;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-OriginatorOrg": "htecgroup.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "GV2PR09MB8755.eurprd09.prod.outlook.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a2bc9e86-62f0-4003-f899-08de93f41ede", "X-MS-Exchange-CrossTenant-originalarrivaltime": "06 Apr 2026 15:49:42.5185 (UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "9f85665b-7efd-4776-9dfe-b6bfda2565ee", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n q2PuC5JEp54zRQE79BSUCHRvYSuQU8Z9lJUIm43c1jbXI9JjewO1SOrirDJJZSl+zScwbxVvuDE1CVZ5A3tZ95cvHgPU8LPjk0E1yjqQnnM=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "VI1PR09MB6903", "Received-SPF": "pass client-ip=2a01:111:f403:c202::7;\n envelope-from=Djordje.Todorovic@htecgroup.com;\n helo=GVXPR05CU001.outbound.protection.outlook.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add riscv_is_big_endian() helper that checks the hart's big-endian CPU\nproperty and use it throughout the boot code:\n\n- ELF loading: pass ELFDATA2MSB or ELFDATA2LSB based on endianness\n- Firmware dynamic info: use cpu_to_be* or cpu_to_le* based on endianness\n- Reset vector: instructions (entries 0-5) remain always little-endian,\n data words (entries 6-9) use target data endianness. For RV64 BE, the\n hi/lo word pairs within each dword are swapped since LD reads as BE.\n\nThis is part of the runtime big-endian support series which avoids\nseparate BE binaries by handling endianness as a CPU property.\n\nSigned-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>\n---\n hw/riscv/boot.c | 82 +++++++++++++++++++++++++++++++++++------\n include/hw/riscv/boot.h | 2 +\n 2 files changed, 72 insertions(+), 12 deletions(-)", "diff": "diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c\nindex e5490beda0..c7558b904f 100644\n--- a/hw/riscv/boot.c\n+++ b/hw/riscv/boot.c\n@@ -40,6 +40,28 @@ bool riscv_is_32bit(RISCVHartArrayState *harts)\n return mcc->def->misa_mxl_max == MXL_RV32;\n }\n \n+bool riscv_is_big_endian(RISCVHartArrayState *harts)\n+{\n+ return harts->harts[0].cfg.big_endian;\n+}\n+\n+/*\n+ * Convert a pair of 32-bit words forming a 64-bit dword to target data\n+ * endianness. For big-endian, the hi/lo word order is swapped since LD\n+ * interprets bytes as BE.\n+ */\n+static void riscv_boot_data_dword(uint32_t *data, bool big_endian)\n+{\n+ if (big_endian) {\n+ uint32_t tmp = data[0];\n+ data[0] = cpu_to_be32(data[1]);\n+ data[1] = cpu_to_be32(tmp);\n+ } else {\n+ data[0] = cpu_to_le32(data[0]);\n+ data[1] = cpu_to_le32(data[1]);\n+ }\n+}\n+\n /*\n * Return the per-socket PLIC hart topology configuration string\n * (caller must free with g_free())\n@@ -72,6 +94,7 @@ void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts)\n info->kernel_size = 0;\n info->initrd_size = 0;\n info->is_32bit = riscv_is_32bit(harts);\n+ info->is_big_endian = riscv_is_big_endian(harts);\n }\n \n vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,\n@@ -247,8 +270,9 @@ void riscv_load_kernel(MachineState *machine,\n */\n kernel_size = load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL,\n &info->image_low_addr, &info->image_high_addr,\n- NULL, ELFDATA2LSB, EM_RISCV,\n- 1, 0, NULL, true, sym_cb);\n+ NULL,\n+ ELFDATA2LSB,\n+ EM_RISCV, 1, 0, NULL, true, sym_cb);\n if (kernel_size > 0) {\n info->kernel_size = kernel_size;\n goto out;\n@@ -391,21 +415,32 @@ void riscv_rom_copy_firmware_info(MachineState *machine,\n struct fw_dynamic_info64 dinfo64;\n void *dinfo_ptr = NULL;\n size_t dinfo_len;\n+ bool big_endian = riscv_is_big_endian(harts);\n \n if (riscv_is_32bit(harts)) {\n- dinfo32.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE);\n- dinfo32.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION);\n- dinfo32.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S);\n- dinfo32.next_addr = cpu_to_le32(kernel_entry);\n+ dinfo32.magic = big_endian ? cpu_to_be32(FW_DYNAMIC_INFO_MAGIC_VALUE)\n+ : cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE);\n+ dinfo32.version = big_endian ? cpu_to_be32(FW_DYNAMIC_INFO_VERSION)\n+ : cpu_to_le32(FW_DYNAMIC_INFO_VERSION);\n+ dinfo32.next_mode = big_endian\n+ ? cpu_to_be32(FW_DYNAMIC_INFO_NEXT_MODE_S)\n+ : cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S);\n+ dinfo32.next_addr = big_endian ? cpu_to_be32(kernel_entry)\n+ : cpu_to_le32(kernel_entry);\n dinfo32.options = 0;\n dinfo32.boot_hart = 0;\n dinfo_ptr = &dinfo32;\n dinfo_len = sizeof(dinfo32);\n } else {\n- dinfo64.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE);\n- dinfo64.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION);\n- dinfo64.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S);\n- dinfo64.next_addr = cpu_to_le64(kernel_entry);\n+ dinfo64.magic = big_endian ? cpu_to_be64(FW_DYNAMIC_INFO_MAGIC_VALUE)\n+ : cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE);\n+ dinfo64.version = big_endian ? cpu_to_be64(FW_DYNAMIC_INFO_VERSION)\n+ : cpu_to_le64(FW_DYNAMIC_INFO_VERSION);\n+ dinfo64.next_mode = big_endian\n+ ? cpu_to_be64(FW_DYNAMIC_INFO_NEXT_MODE_S)\n+ : cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S);\n+ dinfo64.next_addr = big_endian ? cpu_to_be64(kernel_entry)\n+ : cpu_to_le64(kernel_entry);\n dinfo64.options = 0;\n dinfo64.boot_hart = 0;\n dinfo_ptr = &dinfo64;\n@@ -474,10 +509,33 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts\n reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */\n }\n \n- /* copy in the reset vector in little_endian byte order */\n- for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {\n+ /* RISC-V instructions are always little-endian */\n+ for (i = 0; i < 6; i++) {\n reset_vec[i] = cpu_to_le32(reset_vec[i]);\n }\n+\n+ /*\n+ * Data words (addresses at entries 6-9) must match the firmware's data\n+ * endianness.\n+ */\n+ if (riscv_is_32bit(harts)) {\n+ for (i = 6; i < ARRAY_SIZE(reset_vec); i++) {\n+ if (riscv_is_big_endian(harts)) {\n+ reset_vec[i] = cpu_to_be32(reset_vec[i]);\n+ } else {\n+ reset_vec[i] = cpu_to_le32(reset_vec[i]);\n+ }\n+ }\n+ } else {\n+ /*\n+ * For RV64, each pair of 32-bit words forms a dword. For big-endian,\n+ * the hi/lo word order within each dword must be swapped since LD\n+ * interprets bytes as BE.\n+ */\n+ for (i = 6; i < ARRAY_SIZE(reset_vec); i += 2) {\n+ riscv_boot_data_dword(reset_vec + i, riscv_is_big_endian(harts));\n+ }\n+ }\n rom_add_blob_fixed_as(\"mrom.reset\", reset_vec, sizeof(reset_vec),\n rom_base, &address_space_memory);\n riscv_rom_copy_firmware_info(machine, harts,\ndiff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h\nindex f00b3ca122..a54c2b397d 100644\n--- a/include/hw/riscv/boot.h\n+++ b/include/hw/riscv/boot.h\n@@ -36,9 +36,11 @@ typedef struct RISCVBootInfo {\n ssize_t initrd_size;\n \n bool is_32bit;\n+ bool is_big_endian;\n } RISCVBootInfo;\n \n bool riscv_is_32bit(RISCVHartArrayState *harts);\n+bool riscv_is_big_endian(RISCVHartArrayState *harts);\n \n char *riscv_plic_hart_config_string(int hart_count);\n \n", "prefixes": [ "v6", "5/7" ] }