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GET /api/patches/2220180/?format=api
{ "id": 2220180, "url": "http://patchwork.ozlabs.org/api/patches/2220180/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406150434.407201-15-pierrick.bouvier@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260406150434.407201-15-pierrick.bouvier@linaro.org>", "list_archive_url": null, "date": "2026-04-06T15:04:34", "name": "[v7,14/14] target/arm/tcg/translate.c: replace TCGv with TCGv_va", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bb9760eef88398210091b105f31c3a6ccdc22912", "submitter": { "id": 85798, "url": "http://patchwork.ozlabs.org/api/people/85798/?format=api", "name": "Pierrick Bouvier", "email": "pierrick.bouvier@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406150434.407201-15-pierrick.bouvier@linaro.org/mbox/", "series": [ { "id": 498869, "url": "http://patchwork.ozlabs.org/api/series/498869/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498869", "date": "2026-04-06T15:04:20", "name": "target/arm: single-binary", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/498869/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220180/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220180/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) 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csfFtacQ4z/bBPGxQjdL9iGTNomUmf2WEOGa96fKNrZVgRkVrM/ssHPA1IaP7Yk1qYuRnefj9lC\n mjct2kC64HXojSFK1W6alS3StTNoaTOjxwGkYe03Cdh2JEj0x5CVo4u6DmBXWjNEBZ8wQXcYeDn\n P8g", "X-Received": "by 2002:a17:902:ce0b:b0:2b0:c060:aab8 with SMTP id\n d9443c01a7336-2b277d9b788mr144035945ad.9.1775487907068;\n Mon, 06 Apr 2026 08:05:07 -0700 (PDT)", "From": "Pierrick Bouvier <pierrick.bouvier@linaro.org>", "To": "qemu-devel@nongnu.org", "Cc": "qemu-arm@nongnu.org, Pierrick Bouvier <pierrick.bouvier@linaro.org>,\n Peter Maydell <peter.maydell@linaro.org>, philmd@linaro.org,\n jim.macarthur@linaro.org, Paolo Bonzini <pbonzini@redhat.com>,\n Richard Henderson <richard.henderson@linaro.org>", "Subject": "[PATCH v7 14/14] target/arm/tcg/translate.c: replace TCGv with\n TCGv_va", "Date": "Mon, 6 Apr 2026 08:04:34 -0700", "Message-ID": "<20260406150434.407201-15-pierrick.bouvier@linaro.org>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260406150434.407201-1-pierrick.bouvier@linaro.org>", "References": "<20260406150434.407201-1-pierrick.bouvier@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::633;\n envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x633.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "We know this file is for 32-bit runtime target, so we can set\nTCG_ADDRESS_BITS and pass the correct addr_type to translator_loop.\n\nSigned-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>\n---\n target/arm/tcg/translate.c | 33 +++++++++++++++++----------------\n 1 file changed, 17 insertions(+), 16 deletions(-)", "diff": "diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\nindex ebcf68aea97..6ea48efbac2 100644\n--- a/target/arm/tcg/translate.c\n+++ b/target/arm/tcg/translate.c\n@@ -22,7 +22,8 @@\n \n #include \"translate.h\"\n #include \"translate-a32.h\"\n-#include \"tcg/tcg-op.h\"\n+#define TCG_ADDRESS_BITS 32\n+#include \"tcg/tcg-op-mem.h\"\n #include \"qemu/log.h\"\n #include \"arm_ldst.h\"\n #include \"semihosting/semihost.h\"\n@@ -909,14 +910,14 @@ MemOp pow2_align(unsigned i)\n * that the address argument is TCGv_i32 rather than TCGv.\n */\n \n-static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)\n+static TCGv_va gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)\n {\n- TCGv addr = tcg_temp_new();\n- tcg_gen_extu_i32_tl(addr, a32);\n+ TCGv_va addr = tcgv_va_temp_new();\n+ tcg_gen_mov_i32(addr, a32);\n \n /* Not needed for user-mode BE32, where we use MO_BE instead. */\n if (!IS_USER_ONLY && s->sctlr_b && (op & MO_SIZE) < MO_32) {\n- tcg_gen_xori_tl(addr, addr, 4 - (1 << (op & MO_SIZE)));\n+ tcg_gen_xori_i32(addr, addr, 4 - (1 << (op & MO_SIZE)));\n }\n return addr;\n }\n@@ -928,21 +929,21 @@ static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)\n void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,\n TCGv_i32 a32, int index, MemOp opc)\n {\n- TCGv addr = gen_aa32_addr(s, a32, opc);\n+ TCGv_va addr = gen_aa32_addr(s, a32, opc);\n tcg_gen_qemu_ld_i32(val, addr, index, opc);\n }\n \n void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,\n TCGv_i32 a32, int index, MemOp opc)\n {\n- TCGv addr = gen_aa32_addr(s, a32, opc);\n+ TCGv_va addr = gen_aa32_addr(s, a32, opc);\n tcg_gen_qemu_st_i32(val, addr, index, opc);\n }\n \n void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,\n TCGv_i32 a32, int index, MemOp opc)\n {\n- TCGv addr = gen_aa32_addr(s, a32, opc);\n+ TCGv_va addr = gen_aa32_addr(s, a32, opc);\n \n tcg_gen_qemu_ld_i64(val, addr, index, opc);\n \n@@ -955,7 +956,7 @@ void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,\n void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,\n TCGv_i32 a32, int index, MemOp opc)\n {\n- TCGv addr = gen_aa32_addr(s, a32, opc);\n+ TCGv_va addr = gen_aa32_addr(s, a32, opc);\n \n /* Not needed for user-mode BE32, where we use MO_BE instead. */\n if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {\n@@ -2035,7 +2036,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,\n * architecturally 64-bit access, but instead do a 64-bit access\n * using MO_BE if appropriate and then split the two halves.\n */\n- TCGv taddr = gen_aa32_addr(s, addr, opc);\n+ TCGv_va taddr = gen_aa32_addr(s, addr, opc);\n \n tcg_gen_qemu_ld_i64(t64, taddr, get_mem_index(s), opc);\n tcg_gen_mov_i64(cpu_exclusive_val, t64);\n@@ -2064,7 +2065,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,\n {\n TCGv_i32 t0, t1, t2;\n TCGv_i64 extaddr;\n- TCGv taddr;\n+ TCGv_va taddr;\n TCGLabel *done_label;\n TCGLabel *fail_label;\n MemOp opc = size | MO_ALIGN | s->be_data;\n@@ -3791,7 +3792,7 @@ static void do_ldrd_load(DisasContext *s, TCGv_i32 addr, int rt, int rt2)\n */\n int mem_idx = get_mem_index(s);\n MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data;\n- TCGv taddr = gen_aa32_addr(s, addr, opc);\n+ TCGv_va taddr = gen_aa32_addr(s, addr, opc);\n TCGv_i64 t64 = tcg_temp_new_i64();\n TCGv_i32 tmp = tcg_temp_new_i32();\n TCGv_i32 tmp2 = tcg_temp_new_i32();\n@@ -3846,7 +3847,7 @@ static void do_strd_store(DisasContext *s, TCGv_i32 addr, int rt, int rt2)\n */\n int mem_idx = get_mem_index(s);\n MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data;\n- TCGv taddr = gen_aa32_addr(s, addr, opc);\n+ TCGv_va taddr = gen_aa32_addr(s, addr, opc);\n TCGv_i32 t1 = load_reg(s, rt);\n TCGv_i32 t2 = load_reg(s, rt2);\n TCGv_i64 t64 = tcg_temp_new_i64();\n@@ -4067,7 +4068,7 @@ DO_LDST(STRH, store, MO_UW)\n static bool op_swp(DisasContext *s, arg_SWP *a, MemOp opc)\n {\n TCGv_i32 addr, tmp;\n- TCGv taddr;\n+ TCGv_va taddr;\n \n opc |= s->be_data;\n addr = load_reg(s, a->rn);\n@@ -6881,6 +6882,7 @@ void arm_translate_code(CPUState *cpu, TranslationBlock *tb,\n DisasContext dc = { };\n const TranslatorOps *ops = &arm_translator_ops;\n CPUARMTBFlags tb_flags = arm_tbflags_from_tb(tb);\n+ TCGType addr_type = is_a64(cpu_env(cpu)) ? TCG_TYPE_I64 : TCG_TYPE_I32;\n \n if (EX_TBFLAG_AM32(tb_flags, THUMB)) {\n ops = &thumb_translator_ops;\n@@ -6891,6 +6893,5 @@ void arm_translate_code(CPUState *cpu, TranslationBlock *tb,\n }\n #endif\n \n- translator_loop(cpu, tb, max_insns, pc, host_pc, ops, &dc.base,\n- tcg_default_addr_type());\n+ translator_loop(cpu, tb, max_insns, pc, host_pc, ops, &dc.base, addr_type);\n }\n", "prefixes": [ "v7", "14/14" ] }