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GET /api/patches/2220093/?format=api
{ "id": 2220093, "url": "http://patchwork.ozlabs.org/api/patches/2220093/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260406103237.1203127-3-18255117159@163.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260406103237.1203127-3-18255117159@163.com>", "list_archive_url": null, "date": "2026-04-06T10:32:37", "name": "[v3,2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e12e2ec38daa23abe755ce4f0d1c18f07b860b8f", "submitter": { "id": 89937, "url": "http://patchwork.ozlabs.org/api/people/89937/?format=api", "name": "Hans Zhang", "email": "18255117159@163.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260406103237.1203127-3-18255117159@163.com/mbox/", "series": [ { "id": 498837, "url": "http://patchwork.ozlabs.org/api/series/498837/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=498837", "date": "2026-04-06T10:32:36", "name": "PCI: cadence: Add LTSSM debugfs", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/498837/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220093/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220093/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51941-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=163.com header.i=@163.com header.a=rsa-sha256\n header.s=s110527 header.b=nNl/ZAWJ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; helo=sin.lore.kernel.org;\n envelope-from=linux-pci+bounces-51941-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=163.com header.i=@163.com\n header.b=\"nNl/ZAWJ\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=220.197.31.3", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=163.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=163.com" ], "Received": [ "from sin.lore.kernel.org (sin.lore.kernel.org\n [IPv6:2600:3c15:e001:75::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fq5Jt4fwrz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 06 Apr 2026 20:33:34 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id D7E2230046B4\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 6 Apr 2026 10:33:23 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 4D77B32AAA8;\n\tMon, 6 Apr 2026 10:33:19 +0000 (UTC)", "from m16.mail.163.com (m16.mail.163.com [220.197.31.3])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CD5129AAEA;\n\tMon, 6 Apr 2026 10:33:15 +0000 (UTC)", "from Precision-7960.. (unknown [])\n\tby gzga-smtp-mtada-g0-4 (Coremail) with SMTP id\n _____wAHyuPNi9NplrBRDg--.19284S4;\n\tMon, 06 Apr 2026 18:32:49 +0800 (CST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775471599; cv=none;\n b=XCZ43dxC221DDkOlc18vXBPels2p7BMJV4/1abEq3PWRC020yP9JlJOaiIDfi7ro4cilRvZ3qivno3IUSspFxWsgUZLKk/v7xrWncqrghGsKeRBV1t4ovH0HFzbVZOZGIh/cTh1HUc2QUOEIa8QubRBw1AwWDLxv3s05OU1dLdk=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775471599; c=relaxed/simple;\n\tbh=sibVIwts8mXY1+F3N3YZ3ak+RtDfrOUOetjvGaHEyRQ=;\n\th=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:\n\t MIME-Version;\n b=Wm+lcABtLj+QxsWo1F9V6mlYRGc9xIuVglv8ESZbUFTPS5nIrVFw/VhtNu2v+2HKnumaeja7wbWbCnKqFKlBCqq1PaKyTZj6WvERIAGpnlg6mMYB8Ox0tncik73mpdEF59vMfe9Jg2GfdZldAE3EbDIDx3tgDChDCd3gcHPeCYE=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=163.com;\n spf=pass smtp.mailfrom=163.com;\n dkim=pass (1024-bit key) header.d=163.com header.i=@163.com\n header.b=nNl/ZAWJ; arc=none smtp.client-ip=220.197.31.3", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com;\n\ts=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=us\n\t/i8Eao212ooyYrytu0ImA6mNEV1mY4tpF8uHeZagA=; b=nNl/ZAWJ0J682R5s04\n\tNUluzo2aqgj2nFKPzdfV8RJmA/97TrPceMYnPIGHIFsBU+GKYZJ0c+6+8a4I+ZlP\n\tAlTWJum1J/m5b/hgfldouMb5wQaJuyMnavDTUDj+WVH7RH3ocV4kmJIuiJyEnF7f\n\tDxYpzYNCN7BX2oxC8TEkRgA40=", "From": "Hans Zhang <18255117159@163.com>", "To": "bhelgaas@google.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\thans.zhang@cixtech.com", "Cc": "robh@kernel.org,\n\tmpillai@cadence.com,\n\tlinux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tHans Zhang <18255117159@163.com>", "Subject": "[PATCH v3 2/2] PCI: cadence: Add debugfs property to provide LTSSM\n status of the PCIe link", "Date": "Mon, 6 Apr 2026 18:32:37 +0800", "Message-Id": "<20260406103237.1203127-3-18255117159@163.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260406103237.1203127-1-18255117159@163.com>", "References": "<20260406103237.1203127-1-18255117159@163.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "_____wAHyuPNi9NplrBRDg--.19284S4", "X-Coremail-Antispam": "1Uf129KBjvAXoWfXr43Jr43tFWfWF1UXr1DZFb_yoW5JF1rAo\n\tW3Gw4fW3WxZa4DAas3W3ZrGFyxXr1293W7ta18KF1rGFsFkFnrtrWUXr18ta1Fgr1UArW5\n\tAr1DZ3W2kr4xWwsrn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3\n\tAaLaJ3UbIYCTnIWIevJa73UjIFyTuYvj4iNVy7UUUUU", "X-CM-SenderInfo": "rpryjkyvrrlimvzbiqqrwthudrp/xtbCwxFmCmnTi9F1EAAA37" }, "content": "Add the debugfs property to provide a view of the current link's LTSSM\nstatus from the Root Port device.\n\nTest example:\n # cat /sys/kernel/debug/cdns_pcie_a0c0000.pcie/ltssm_status\n L0_STATE (0x29)\n\nSigned-off-by: Hans Zhang <18255117159@163.com>\n---\n Documentation/ABI/testing/debugfs-cdns-pcie | 5 +\n drivers/pci/controller/cadence/Kconfig | 9 +\n drivers/pci/controller/cadence/Makefile | 1 +\n drivers/pci/controller/cadence/pci-sky1.c | 3 +\n .../controller/cadence/pcie-cadence-debugfs.c | 215 ++++++++++++++++++\n .../pci/controller/cadence/pcie-cadence-ep.c | 3 +\n .../cadence/pcie-cadence-host-hpa.c | 8 +-\n .../controller/cadence/pcie-cadence-host.c | 9 +-\n drivers/pci/controller/cadence/pcie-cadence.h | 145 ++++++++++++\n 9 files changed, 396 insertions(+), 2 deletions(-)\n create mode 100644 Documentation/ABI/testing/debugfs-cdns-pcie\n create mode 100644 drivers/pci/controller/cadence/pcie-cadence-debugfs.c", "diff": "diff --git a/Documentation/ABI/testing/debugfs-cdns-pcie b/Documentation/ABI/testing/debugfs-cdns-pcie\nnew file mode 100644\nindex 000000000000..659ad2ab70e4\n--- /dev/null\n+++ b/Documentation/ABI/testing/debugfs-cdns-pcie\n@@ -0,0 +1,5 @@\n+What:\t\t/sys/kernel/debug/cdns_pcie_<dev>/ltssm_status\n+Date:\t\tMarch 2026\n+Contact:\tHans Zhang <18255117159@163.com>\n+Description:\t(RO) Read will return the current PCIe LTSSM state in both\n+\t\tstring and raw value.\ndiff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig\nindex 9e651d545973..b277c5f6e196 100644\n--- a/drivers/pci/controller/cadence/Kconfig\n+++ b/drivers/pci/controller/cadence/Kconfig\n@@ -6,6 +6,15 @@ menu \"Cadence-based PCIe controllers\"\n config PCIE_CADENCE\n \ttristate\n \n+config PCIE_CADENCE_DEBUGFS\n+\tbool \"Cadence PCIe debugfs entries\"\n+\tdepends on DEBUG_FS\n+\tdepends on PCIE_CADENCE_HOST || PCIE_CADENCE_EP\n+\thelp\n+\t Say Y here to enable debugfs entries for the PCIe controller. These\n+\t entries provide various debug features related to the controller and\n+\t the LTSSM status of link can be displayed.\n+\n config PCIE_CADENCE_HOST\n \ttristate\n \tdepends on OF\ndiff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile\nindex b8ec1cecfaa8..2cdc4617e0c2 100644\n--- a/drivers/pci/controller/cadence/Makefile\n+++ b/drivers/pci/controller/cadence/Makefile\n@@ -4,6 +4,7 @@ pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o pcie-c\n pcie-cadence-ep-mod-y := pcie-cadence-ep.o\n \n obj-$(CONFIG_PCIE_CADENCE) = pcie-cadence-mod.o\n+obj-$(CONFIG_PCIE_CADENCE_DEBUGFS) += pcie-cadence-debugfs.o\n obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host-mod.o\n obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep-mod.o\n obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o\ndiff --git a/drivers/pci/controller/cadence/pci-sky1.c b/drivers/pci/controller/cadence/pci-sky1.c\nindex e1f4a98e2ab6..093f20466339 100644\n--- a/drivers/pci/controller/cadence/pci-sky1.c\n+++ b/drivers/pci/controller/cadence/pci-sky1.c\n@@ -221,7 +221,10 @@ MODULE_DEVICE_TABLE(of, of_sky1_pcie_match);\n static void sky1_pcie_remove(struct platform_device *pdev)\n {\n \tstruct sky1_pcie *pcie = platform_get_drvdata(pdev);\n+\tstruct cdns_pcie_rc *rc;\n \n+\trc = container_of(pcie->cdns_pcie, struct cdns_pcie_rc, pcie);\n+\tcdns_pcie_debugfs_deinit(&rc->pcie);\n \tpci_ecam_free(pcie->cfg);\n }\n \ndiff --git a/drivers/pci/controller/cadence/pcie-cadence-debugfs.c b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c\nnew file mode 100644\nindex 000000000000..d83007ae218e\n--- /dev/null\n+++ b/drivers/pci/controller/cadence/pcie-cadence-debugfs.c\n@@ -0,0 +1,215 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Cadence PCIe controller debugfs driver\n+ *\n+ * Copyright (C) 2026 Hans Zhang <18255117159@163.com>\n+ * Author: Hans Zhang <18255117159@163.com>\n+ */\n+\n+#include <linux/debugfs.h>\n+\n+#include \"pcie-cadence.h\"\n+\n+#define CDNS_DEBUGFS_BUF_MAX\t\t128\n+#define CDNS_PCIE_LGA_LTSSM_STATUS_MASK\tGENMASK(29, 24)\n+#define CDNS_PCIE_HPA_LTSSM_STATUS_MASK\tGENMASK(27, 20)\n+\n+static const char *cdns_pcie_ltssm_status_string(enum cdns_pcie_ltssm ltssm)\n+{\n+\tconst char *str;\n+\n+\tswitch (ltssm) {\n+#define CDNS_PCIE_LTSSM_NAME(n) case n: str = #n; break\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DETECT_QUIET);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DETECT_QUIET_ENTRY);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DETECT_ACTIVE);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DETECT_ACTIVE_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DETECT_ACTIVE_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DETECT_ACTIVE_3);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RCVR_DETECTED_ST);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RCVR_DETECTED_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_ACTIVE);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_ACTIVE_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_ACTIVE_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_ACTIVE_3);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_CONFIG);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_CONFIG_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_CONFIG_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LW_START_RC);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LW_START_RC_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LW_ACC_RC);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_RC);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LW_START_EP);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LW_START_EP_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LW_ACC_EP);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DUMMY_STATE_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_COMPLETE);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_COMPLETE_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_COMPLETE_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_IDLE);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_CONFIG_IDLE_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DUMMY_STATE_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DUMMY_STATE_3);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DUMMY_STATE_4);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L0_STATE);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_IDLE);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_IDLE_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DISABLE_LINK);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DISABLE_LINK_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DISABLE_LINK_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DISABLE_LINK_3);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DISABLE_LINK_4);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DISABLE_LINK_5);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DISABLE_LINK_6);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_DISABLE_LINK_7);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_HOT_RESET);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_HOT_RESET_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_HOT_RESET_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_HOT_RESET_3);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L0S_ENTRY);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L0S_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L0S_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L0S_3);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L0S_4);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L0S_5);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_WAIT_FOR_LINK_TX);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_TX_FTS_ENTRY);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_TX_FTS_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_TX_FTS_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_TX_ELEC_IDLE_ST);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_TX_ELEC_IDLE_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_TX_ELEC_IDLE_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_TX_ELEC_IDLE_3);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_SPEED);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_SPEED_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_SPEED_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_SPEED_3);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_3);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_4);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_5);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_6);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_7);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_8);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY_FROM_RECOVERY);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_3);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_4);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_5);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ACTIVE);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L1_ENTRY);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L1_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L1_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L1_3);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L1_4);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L1_IDLE);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L1_EXIT);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L2_ENTRY);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L2_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L2_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L2_3);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L2_4);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L2_5);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_L2_IDLE);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_3);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_4);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_5);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_FROM_RECOVERY);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_ACTIVE);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE0);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_2);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_1);\n+\tCDNS_PCIE_LTSSM_NAME(CDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_2);\n+\tdefault:\n+\t\tstr = \"CDNS_PCIE_LTSSM_UNKNOWN\";\n+\t\tbreak;\n+\t}\n+\n+\treturn str + strlen(\"CDNS_PCIE_LTSSM_\");\n+}\n+\n+static int ltssm_status_show(struct seq_file *s, void *v)\n+{\n+\tstruct cdns_pcie *pci = s->private;\n+\tenum cdns_pcie_ltssm ltssm;\n+\tu32 reg;\n+\n+\tif (pci->is_hpa) {\n+\t\treg = cdns_pcie_hpa_readl(pci, REG_BANK_IP_REG,\n+\t\t\t\t\tCDNS_PCIE_HPA_PHY_DBG_STS_REG0);\n+\t\tltssm = FIELD_GET(CDNS_PCIE_HPA_LTSSM_STATUS_MASK, reg);\n+\t} else {\n+\t\treg = cdns_pcie_readl(pci, CDNS_PCIE_LM_BASE);\n+\t\tltssm = FIELD_GET(CDNS_PCIE_LGA_LTSSM_STATUS_MASK, reg);\n+\t}\n+\n+\tseq_printf(s, \"%s (0x%02x)\\n\", cdns_pcie_ltssm_status_string(ltssm), ltssm);\n+\n+\treturn 0;\n+}\n+\n+static int ltssm_status_open(struct inode *inode, struct file *file)\n+{\n+\treturn single_open(file, ltssm_status_show, inode->i_private);\n+}\n+\n+static const struct file_operations cdns_pcie_ltssm_status_ops = {\n+\t.open = ltssm_status_open,\n+\t.read = seq_read,\n+};\n+\n+static void cdns_pcie_ltssm_debugfs_init(struct cdns_pcie *pci, struct dentry *dir)\n+{\n+\tdebugfs_create_file(\"ltssm_status\", 0444, dir, pci,\n+\t\t\t &cdns_pcie_ltssm_status_ops);\n+}\n+\n+void cdns_pcie_debugfs_deinit(struct cdns_pcie *pci)\n+{\n+\tif (!pci->debug_dir)\n+\t\treturn;\n+\n+\tdebugfs_remove_recursive(pci->debug_dir);\n+}\n+EXPORT_SYMBOL_GPL(cdns_pcie_debugfs_deinit);\n+\n+void cdns_pcie_debugfs_init(struct cdns_pcie *pci)\n+{\n+\tchar dirname[CDNS_DEBUGFS_BUF_MAX];\n+\tstruct device *dev = pci->dev;\n+\n+\t/* Create main directory for each platform driver. */\n+\tsnprintf(dirname, CDNS_DEBUGFS_BUF_MAX, \"cdns_pcie_%s\", dev_name(dev));\n+\tpci->debug_dir = debugfs_create_dir(dirname, NULL);\n+\n+\tcdns_pcie_ltssm_debugfs_init(pci, pci->debug_dir);\n+}\n+EXPORT_SYMBOL_GPL(cdns_pcie_debugfs_init);\ndiff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c\nindex c0e1194a936b..38a0157b60dc 100644\n--- a/drivers/pci/controller/cadence/pcie-cadence-ep.c\n+++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c\n@@ -659,6 +659,7 @@ void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep)\n \tpci_epc_mem_free_addr(epc, ep->irq_phys_addr, ep->irq_cpu_addr,\n \t\t\t SZ_128K);\n \tpci_epc_mem_exit(epc);\n+\tcdns_pcie_debugfs_deinit(&ep->pcie);\n }\n EXPORT_SYMBOL_GPL(cdns_pcie_ep_disable);\n \n@@ -761,6 +762,8 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)\n \n \tpci_epc_init_notify(epc);\n \n+\tcdns_pcie_debugfs_init(pcie);\n+\n \treturn 0;\n \n free_epc_mem:\ndiff --git a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c\nindex 0f540bed58e8..38bd74d9e071 100644\n--- a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c\n+++ b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c\n@@ -360,7 +360,13 @@ int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc)\n \tif (!bridge->ops)\n \t\tbridge->ops = &cdns_pcie_hpa_host_ops;\n \n-\treturn pci_host_probe(bridge);\n+\tret = pci_host_probe(bridge);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tcdns_pcie_debugfs_init(pcie);\n+\n+\treturn 0;\n }\n EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_setup);\n \ndiff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c\nindex db3154c1eccb..bcc1374b6762 100644\n--- a/drivers/pci/controller/cadence/pcie-cadence-host.c\n+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c\n@@ -363,6 +363,7 @@ void cdns_pcie_host_disable(struct cdns_pcie_rc *rc)\n \n \tcdns_pcie_host_deinit(rc);\n \tcdns_pcie_host_link_disable(rc);\n+\tcdns_pcie_debugfs_deinit(&rc->pcie);\n }\n EXPORT_SYMBOL_GPL(cdns_pcie_host_disable);\n \n@@ -416,7 +417,13 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)\n \tif (!bridge->ops)\n \t\tbridge->ops = &cdns_pcie_host_ops;\n \n-\treturn pci_host_probe(bridge);\n+\tret = pci_host_probe(bridge);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tcdns_pcie_debugfs_init(pcie);\n+\n+\treturn 0;\n }\n EXPORT_SYMBOL_GPL(cdns_pcie_host_setup);\n \ndiff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h\nindex c8cb19f7622f..6db98b7d24cb 100644\n--- a/drivers/pci/controller/cadence/pcie-cadence.h\n+++ b/drivers/pci/controller/cadence/pcie-cadence.h\n@@ -42,6 +42,137 @@ enum cdns_pcie_reg_bank {\n \tREG_BANKS_MAX,\n };\n \n+enum cdns_pcie_ltssm {\n+\tCDNS_PCIE_LTSSM_DETECT_QUIET\t\t= 0,\n+\tCDNS_PCIE_LTSSM_DETECT_QUIET_ENTRY\t= 1,\n+\tCDNS_PCIE_LTSSM_DETECT_ACTIVE\t\t= 2,\n+\tCDNS_PCIE_LTSSM_DETECT_ACTIVE_1\t\t= 3,\n+\tCDNS_PCIE_LTSSM_DETECT_ACTIVE_2\t\t= 4,\n+\tCDNS_PCIE_LTSSM_DETECT_ACTIVE_3\t\t= 5,\n+\tCDNS_PCIE_LTSSM_RCVR_DETECTED_ST\t= 6,\n+\tCDNS_PCIE_LTSSM_RCVR_DETECTED_1\t\t= 7,\n+\tCDNS_PCIE_LTSSM_POLLING_ACTIVE\t\t= 8,\n+\tCDNS_PCIE_LTSSM_POLLING_ACTIVE_1\t= 9,\n+\tCDNS_PCIE_LTSSM_POLLING_ACTIVE_2\t= 10,\n+\tCDNS_PCIE_LTSSM_POLLING_ACTIVE_3\t= 11,\n+\tCDNS_PCIE_LTSSM_POLLING_COMPLIANCE\t= 12,\n+\tCDNS_PCIE_LTSSM_POLLING_COMPLIANCE_1\t= 13,\n+\tCDNS_PCIE_LTSSM_POLLING_CONFIG\t\t= 14,\n+\tCDNS_PCIE_LTSSM_POLLING_CONFIG_1\t= 15,\n+\tCDNS_PCIE_LTSSM_POLLING_CONFIG_2\t= 16,\n+\tCDNS_PCIE_LTSSM_CONFIG_LW_START_RC\t= 17,\n+\tCDNS_PCIE_LTSSM_CONFIG_LW_START_RC_1\t= 18,\n+\tCDNS_PCIE_LTSSM_CONFIG_LW_START_RC_2\t= 19,\n+\tCDNS_PCIE_LTSSM_CONFIG_LW_ACC_RC\t= 20,\n+\tCDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC\t= 21,\n+\tCDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_RC_1 = 22,\n+\tCDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_RC\t= 23,\n+\tCDNS_PCIE_LTSSM_CONFIG_LW_START_EP\t= 24,\n+\tCDNS_PCIE_LTSSM_CONFIG_LW_START_EP_1\t= 25,\n+\tCDNS_PCIE_LTSSM_CONFIG_LW_START_EP_2\t= 26,\n+\tCDNS_PCIE_LTSSM_CONFIG_LW_ACC_EP\t= 27,\n+\tCDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP\t= 28,\n+\tCDNS_PCIE_LTSSM_CONFIG_LANENUM_WAIT_EP_1 = 29,\n+\tCDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP\t= 30,\n+\tCDNS_PCIE_LTSSM_CONFIG_LANENUM_ACC_EP_1\t= 31,\n+\tCDNS_PCIE_LTSSM_DUMMY_STATE_1\t\t= 32,\n+\tCDNS_PCIE_LTSSM_CONFIG_COMPLETE\t\t= 33,\n+\tCDNS_PCIE_LTSSM_CONFIG_COMPLETE_1\t= 34,\n+\tCDNS_PCIE_LTSSM_CONFIG_COMPLETE_2\t= 35,\n+\tCDNS_PCIE_LTSSM_CONFIG_IDLE\t\t= 36,\n+\tCDNS_PCIE_LTSSM_CONFIG_IDLE_1\t\t= 37,\n+\tCDNS_PCIE_LTSSM_DUMMY_STATE_2\t\t= 38,\n+\tCDNS_PCIE_LTSSM_DUMMY_STATE_3\t\t= 39,\n+\tCDNS_PCIE_LTSSM_DUMMY_STATE_4\t\t= 40,\n+\tCDNS_PCIE_LTSSM_L0_STATE\t\t= 41,\n+\tCDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK\t= 42,\n+\tCDNS_PCIE_LTSSM_RECOVERY_RCVR_LOCK_1\t= 43,\n+\tCDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG\t= 44,\n+\tCDNS_PCIE_LTSSM_RECOVERY_RCVR_CFG_1\t= 45,\n+\tCDNS_PCIE_LTSSM_RECOVERY_IDLE\t\t= 46,\n+\tCDNS_PCIE_LTSSM_RECOVERY_IDLE_1\t\t= 47,\n+\tCDNS_PCIE_LTSSM_DISABLE_LINK\t\t= 48,\n+\tCDNS_PCIE_LTSSM_DISABLE_LINK_1\t\t= 49,\n+\tCDNS_PCIE_LTSSM_DISABLE_LINK_2\t\t= 50,\n+\tCDNS_PCIE_LTSSM_DISABLE_LINK_3\t\t= 51,\n+\tCDNS_PCIE_LTSSM_DISABLE_LINK_4\t\t= 52,\n+\tCDNS_PCIE_LTSSM_DISABLE_LINK_5\t\t= 53,\n+\tCDNS_PCIE_LTSSM_DISABLE_LINK_6\t\t= 54,\n+\tCDNS_PCIE_LTSSM_DISABLE_LINK_7\t\t= 55,\n+\tCDNS_PCIE_LTSSM_HOT_RESET\t\t= 56,\n+\tCDNS_PCIE_LTSSM_HOT_RESET_1\t\t= 57,\n+\tCDNS_PCIE_LTSSM_HOT_RESET_2\t\t= 58,\n+\tCDNS_PCIE_LTSSM_HOT_RESET_3\t\t= 59,\n+\tCDNS_PCIE_LTSSM_L0S_ENTRY\t\t= 60,\n+\tCDNS_PCIE_LTSSM_L0S_1\t\t\t= 61,\n+\tCDNS_PCIE_LTSSM_L0S_2\t\t\t= 62,\n+\tCDNS_PCIE_LTSSM_L0S_3\t\t\t= 63,\n+\tCDNS_PCIE_LTSSM_L0S_4\t\t\t= 64,\n+\tCDNS_PCIE_LTSSM_L0S_5\t\t\t= 65,\n+\tCDNS_PCIE_LTSSM_WAIT_FOR_LINK_TX\t= 66,\n+\tCDNS_PCIE_LTSSM_TX_FTS_ENTRY\t\t= 67,\n+\tCDNS_PCIE_LTSSM_TX_FTS_1\t\t= 68,\n+\tCDNS_PCIE_LTSSM_TX_FTS_2\t\t= 69,\n+\tCDNS_PCIE_LTSSM_TX_ELEC_IDLE_ST\t\t= 70,\n+\tCDNS_PCIE_LTSSM_TX_ELEC_IDLE_1\t\t= 71,\n+\tCDNS_PCIE_LTSSM_TX_ELEC_IDLE_2\t\t= 72,\n+\tCDNS_PCIE_LTSSM_TX_ELEC_IDLE_3\t\t= 73,\n+\tCDNS_PCIE_LTSSM_RECOVERY_SPEED\t\t= 74,\n+\tCDNS_PCIE_LTSSM_RECOVERY_SPEED_1\t= 75,\n+\tCDNS_PCIE_LTSSM_RECOVERY_SPEED_2\t= 76,\n+\tCDNS_PCIE_LTSSM_RECOVERY_SPEED_3\t= 77,\n+\tCDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23 = 78,\n+\tCDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_1 = 79,\n+\tCDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_2 = 80,\n+\tCDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_3 = 81,\n+\tCDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_4 = 82,\n+\tCDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_5 = 83,\n+\tCDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_6 = 84,\n+\tCDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_7 = 85,\n+\tCDNS_PCIE_LTSSM_POLLING_COMPLIANCE_GEN23_8 = 86,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY\t= 87,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ENTRY_FROM_RECOVERY = 88,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT_1\t= 89,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_SLAVE_EXIT\t= 90,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_1\t= 91,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_2\t= 92,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_3\t= 93,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_4\t= 94,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_SLAVE_GEN2_5\t= 95,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_SLAVE_ACTIVE\t= 96,\n+\tCDNS_PCIE_LTSSM_L1_ENTRY\t\t= 97,\n+\tCDNS_PCIE_LTSSM_L1_1\t\t\t= 98,\n+\tCDNS_PCIE_LTSSM_L1_2\t\t\t= 99,\n+\tCDNS_PCIE_LTSSM_L1_3\t\t\t= 100,\n+\tCDNS_PCIE_LTSSM_L1_4\t\t\t= 101,\n+\tCDNS_PCIE_LTSSM_L1_IDLE\t\t\t= 102,\n+\tCDNS_PCIE_LTSSM_L1_EXIT\t\t\t= 103,\n+\tCDNS_PCIE_LTSSM_L2_ENTRY\t\t= 104,\n+\tCDNS_PCIE_LTSSM_L2_1\t\t\t= 105,\n+\tCDNS_PCIE_LTSSM_L2_2\t\t\t= 106,\n+\tCDNS_PCIE_LTSSM_L2_3\t\t\t= 107,\n+\tCDNS_PCIE_LTSSM_L2_4\t\t\t= 108,\n+\tCDNS_PCIE_LTSSM_L2_5\t\t\t= 109,\n+\tCDNS_PCIE_LTSSM_L2_IDLE\t\t\t= 110,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY\t= 111,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_1\t= 112,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_2\t= 113,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_3\t= 114,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_4\t= 115,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_5\t= 116,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_MASTER_ENTRY_FROM_RECOVERY = 117,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_MASTER_ACTIVE\t= 118,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT\t= 119,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_1\t= 120,\n+\tCDNS_PCIE_LTSSM_LOOPBACK_MASTER_EXIT_2\t= 121,\n+\tCDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 122,\n+\tCDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 123,\n+\tCDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_1 = 124,\n+\tCDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE2_2 = 125,\n+\tCDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_1 = 126,\n+\tCDNS_PCIE_LTSSM_RECOVERY_EQUALIZATION_PHASE3_2 = 127,\n+};\n+\n struct cdns_pcie_ops {\n \tint (*start_link)(struct cdns_pcie *pcie);\n \tvoid (*stop_link)(struct cdns_pcie *pcie);\n@@ -87,6 +218,7 @@ struct cdns_plat_pcie_of_data {\n * @ops: Platform-specific ops to control various inputs from Cadence PCIe\n * wrapper\n * @cdns_pcie_reg_offsets: Register bank offsets for different SoC\n+ * @debug_dir: debugfs node\n */\n struct cdns_pcie {\n \tvoid __iomem\t\t *reg_base;\n@@ -100,6 +232,7 @@ struct cdns_pcie {\n \tstruct device_link\t **link;\n \tconst struct cdns_pcie_ops *ops;\n \tconst struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets;\n+\tstruct dentry\t\t\t *debug_dir;\n };\n \n /**\n@@ -522,4 +655,16 @@ bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie);\n \n extern const struct dev_pm_ops cdns_pcie_pm_ops;\n \n+#ifdef CONFIG_PCIE_CADENCE_DEBUGFS\n+void cdns_pcie_debugfs_deinit(struct cdns_pcie *pci);\n+void cdns_pcie_debugfs_init(struct cdns_pcie *pci);\n+#else\n+static inline void cdns_pcie_debugfs_deinit(struct cdns_pcie *pci)\n+{\n+}\n+static inline void cdns_pcie_debugfs_init(struct cdns_pcie *pci)\n+{\n+}\n+#endif\n+\n #endif /* _PCIE_CADENCE_H */\n", "prefixes": [ "v3", "2/2" ] }