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GET /api/patches/2220065/?format=api
{ "id": 2220065, "url": "http://patchwork.ozlabs.org/api/patches/2220065/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260406083404.31359-2-clamor95@gmail.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260406083404.31359-2-clamor95@gmail.com>", "list_archive_url": null, "date": "2026-04-06T08:33:56", "name": "[v1,1/9] ARM: tegra: lg-x3: Complete video device graph", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "dfcb98e247de0a05983f270ccb19f9c1ef80c84c", "submitter": { "id": 84146, "url": "http://patchwork.ozlabs.org/api/people/84146/?format=api", "name": "Svyatoslav Ryhel", "email": "clamor95@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260406083404.31359-2-clamor95@gmail.com/mbox/", "series": [ { "id": 498831, "url": "http://patchwork.ozlabs.org/api/series/498831/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=498831", "date": "2026-04-06T08:33:55", "name": "ARM: tegra: complete a few Tegra30 device trees", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498831/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220065/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220065/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13578-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=msn01Gi/;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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/* WiFi */\n \t};\n \n+\thost1x@50000000 {\n+\t\tvi@54080000 {\n+\t\t\tcsi@800 {\n+\t\t\t\t/delete-node/ channel@1;\n+\t\t\t};\n+\n+\t\t\tports {\n+\t\t\t\t/delete-node/ port@1;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n \tpinmux@70000868 {\n \t\tpinctrl-names = \"default\";\n \t\tpinctrl-0 = <&state_default>;\n@@ -116,6 +128,22 @@ rmi4-f11@11 {\n \t\t};\n \t};\n \n+\ti2c@7000c500 {\n+\t\tcamera-pmic@7d {\n+\t\t\tvt_1v2_front: ldo1 {\n+\t\t\t\tregulator-name = \"vt_1v2_dig\";\n+\t\t\t\tregulator-min-microvolt = <1200000>;\n+\t\t\t\tregulator-max-microvolt = <1200000>;\n+\t\t\t};\n+\n+\t\t\tvt_2v7_front: ldo2 {\n+\t\t\t\tregulator-name = \"vt_2v7_vana\";\n+\t\t\t\tregulator-min-microvolt = <2700000>;\n+\t\t\t\tregulator-max-microvolt = <2700000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n \tspi@7000dc00 {\n \t\tdsi@2 {\n \t\t\t/*\ndiff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts b/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts\nindex 414117fd4382..896639599c12 100644\n--- a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts\n+++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts\n@@ -118,6 +118,52 @@ rmi4-f1a@1a {\n \t\t};\n \t};\n \n+\ti2c@7000c500 {\n+\t\t/* Aptina 1/6\" HD SOC (MT9M114) */\n+\t\tfront-camera@48 {\n+\t\t\tcompatible = \"onnn,mt9m114\";\n+\t\t\treg = <0x48>;\n+\n+\t\t\tclocks = <&tegra_car TEGRA30_CLK_CSUS>;\n+\n+\t\t\treset-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_LOW>;\n+\n+\t\t\tvddio-supply = <&vio_1v8_front>;\n+\t\t\tvdd-supply = <&vt_1v8_front>;\n+\t\t\tvaa-supply = <&vt_2v8_front>;\n+\n+\t\t\torientation = <0>; /* Front camera */\n+\n+\t\t\tassigned-clocks = <&tegra_car TEGRA30_CLK_VI_SENSOR>,\n+\t\t\t\t\t <&tegra_car TEGRA30_CLK_CSUS>;\n+\t\t\tassigned-clock-rates = <24000000>;\n+\t\t\tassigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>,\n+\t\t\t\t\t\t <&tegra_car TEGRA30_CLK_VI_SENSOR>;\n+\n+\t\t\tport {\n+\t\t\t\tfront_camera_output: endpoint {\n+\t\t\t\t\tbus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;\n+\t\t\t\t\tlink-frequencies = /bits/ 64 <384000000>;\n+\t\t\t\t\tremote-endpoint = <&csib_input>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\tcamera-pmic@7d {\n+\t\t\tvt_1v8_front: ldo1 {\n+\t\t\t\tregulator-name = \"vt_1v8_dig\";\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <1800000>;\n+\t\t\t};\n+\n+\t\t\tvt_2v8_front: ldo2 {\n+\t\t\t\tregulator-name = \"vt_2v8_vana\";\n+\t\t\t\tregulator-min-microvolt = <2800000>;\n+\t\t\t\tregulator-max-microvolt = <2800000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n \tspi@7000dc00 {\n \t\tdsi@2 {\n \t\t\t/*\ndiff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi b/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi\nindex 768e201456d8..d2a5904cebed 100644\n--- a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi\n+++ b/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi\n@@ -3,6 +3,7 @@\n #include <dt-bindings/input/gpio-keys.h>\n #include <dt-bindings/input/input.h>\n #include <dt-bindings/leds/common.h>\n+#include <dt-bindings/media/video-interfaces.h>\n #include <dt-bindings/mfd/max77620.h>\n #include <dt-bindings/thermal/thermal.h>\n \n@@ -74,6 +75,91 @@ trustzone@bfe00000 {\n \t};\n \n \thost1x@50000000 {\n+\t\tvi@54080000 {\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tcsi@800 {\n+\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\tavdd-dsi-csi-supply = <&avdd_dsi_csi>;\n+\n+\t\t\t\t/* CSI-A */\n+\t\t\t\tchannel@0 {\n+\t\t\t\t\treg = <0>;\n+\n+\t\t\t\t\tnvidia,mipi-calibrate = <&csi 0>; /* CSIA pad */\n+\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\t\tport@0 {\n+\t\t\t\t\t\treg = <0>;\n+\n+\t\t\t\t\t\tcsia_input: endpoint {\n+\t\t\t\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t\t\t\t\tremote-endpoint = <&rear_camera_output>;\n+\t\t\t\t\t\t};\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@1 {\n+\t\t\t\t\t\treg = <1>;\n+\n+\t\t\t\t\t\tcsia_output: endpoint {\n+\t\t\t\t\t\t\tremote-endpoint = <&vi_ppa_input>;\n+\t\t\t\t\t\t};\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\t/* CSI-B */\n+\t\t\t\tchannel@1 {\n+\t\t\t\t\treg = <1>;\n+\n+\t\t\t\t\tnvidia,mipi-calibrate = <&csi 1>; /* CSIB pad */\n+\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\t\tport@0 {\n+\t\t\t\t\t\treg = <0>;\n+\n+\t\t\t\t\t\tcsib_input: endpoint {\n+\t\t\t\t\t\t\tdata-lanes = <3>;\n+\t\t\t\t\t\t\tremote-endpoint = <&front_camera_output>;\n+\t\t\t\t\t\t};\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@1 {\n+\t\t\t\t\t\treg = <1>;\n+\n+\t\t\t\t\t\tcsib_output: endpoint {\n+\t\t\t\t\t\t\tremote-endpoint = <&vi_ppb_input>;\n+\t\t\t\t\t\t};\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tports {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\tport@0 {\n+\t\t\t\t\treg = <0>;\n+\n+\t\t\t\t\tvi_ppa_input: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&csia_output>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tport@1 {\n+\t\t\t\t\treg = <1>;\n+\n+\t\t\t\t\tvi_ppb_input: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&csib_output>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n \t\tlcd: dc@54200000 {\n \t\t\trgb {\n \t\t\t\tstatus = \"okay\";\n@@ -1112,29 +1198,68 @@ dw9714: coil@c {\n \t\t\tcompatible = \"dongwoon,dw9714\";\n \t\t\treg = <0x0c>;\n \n-\t\t\tenable-gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_HIGH>;\n+\t\t\tpowerdown-gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;\n \n \t\t\tvcc-supply = <&vcc_focuser>;\n \t\t};\n \n+\t\t/* SONY IMX111 1/4\" BSI */\n+\t\trear-camera@10 {\n+\t\t\tcompatible = \"sony,imx111\";\n+\t\t\treg = <0x10>;\n+\n+\t\t\tclocks = <&tegra_car TEGRA30_CLK_CSUS>;\n+\n+\t\t\treset-gpios = <&gpio TEGRA_GPIO(K, 4) GPIO_ACTIVE_LOW>;\n+\n+\t\t\tiovdd-supply = <&vio_1v8_rear>;\n+\t\t\tdvdd-supply = <&vdd_1v2_rear>;\n+\t\t\tavdd-supply = <&vdd_2v7_rear>;\n+\n+\t\t\torientation = <1>; /* Rear camera */\n+\t\t\trotation = <90>;\n+\n+\t\t\tnvmem = <&m24c08>;\n+\t\t\tlens-focus = <&dw9714>;\n+\n+\t\t\tassigned-clocks = <&tegra_car TEGRA30_CLK_VI_SENSOR>,\n+\t\t\t\t\t <&tegra_car TEGRA30_CLK_CSUS>;\n+\t\t\tassigned-clock-rates = <24000000>;\n+\t\t\tassigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>,\n+\t\t\t\t\t\t <&tegra_car TEGRA30_CLK_VI_SENSOR>;\n+\n+\t\t\tport {\n+\t\t\t\trear_camera_output: endpoint {\n+\t\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t\t\tbus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;\n+\t\t\t\t\tlink-frequencies = /bits/ 64 <542400000>;\n+\t\t\t\t\tremote-endpoint = <&csia_input>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\t/* rear camera sensor eeprom m24c08 from ST */\n+\t\tm24c08: eeprom@50 {\n+\t\t\tcompatible = \"atmel,24c08\";\n+\t\t\treg = <0x50>;\n+\n+\t\t\t/* if high then WP is on, if low then off */\n+\t\t\twp-gpios = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;\n+\n+\t\t\t/* it is not OTP but writing is unwanted */\n+\t\t\tread-only;\n+\t\t\tpagesize = <16>;\n+\t\t\tnum-addresses = <1>;\n+\n+\t\t\tvcc-supply = <&vio_1v8_rear>;\n+\t\t};\n+\n \t\tcamera-pmic@7d {\n \t\t\tcompatible = \"ti,lp8720\";\n \t\t\treg = <0x7d>;\n \n \t\t\tenable-gpios = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;\n \n-\t\t\tvt_1v2_front: ldo1 {\n-\t\t\t\tregulator-name = \"vt_1v2_dig\";\n-\t\t\t\tregulator-min-microvolt = <1200000>;\n-\t\t\t\tregulator-max-microvolt = <1200000>;\n-\t\t\t};\n-\n-\t\t\tvt_2v7_front: ldo2 {\n-\t\t\t\tregulator-name = \"vt_2v7_vana\";\n-\t\t\t\tregulator-min-microvolt = <2700000>;\n-\t\t\t\tregulator-max-microvolt = <2700000>;\n-\t\t\t};\n-\n \t\t\tvdd_2v7_rear: ldo3 {\n \t\t\t\tregulator-name = \"8m_2v7_vana\";\n \t\t\t\tregulator-min-microvolt = <2700000>;\n@@ -1348,10 +1473,11 @@ vdd_1v2_mhl: ldo7 {\n \t\t\t\t\tmaxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;\n \t\t\t\t};\n \n-\t\t\t\tldo8 {\n+\t\t\t\tavdd_dsi_csi: ldo8 {\n \t\t\t\t\tregulator-name = \"avdd_dsi_csi\";\n \t\t\t\t\tregulator-min-microvolt = <1200000>;\n \t\t\t\t\tregulator-max-microvolt = <1200000>;\n+\t\t\t\t\tregulator-boot-on;\n \n \t\t\t\t\tmaxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;\n \t\t\t\t};\n", "prefixes": [ "v1", "1/9" ] }