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GET /api/patches/2220001/?format=api
{ "id": 2220001, "url": "http://patchwork.ozlabs.org/api/patches/2220001/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260405180826.729652-1-alessandro@0x65c.net/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260405180826.729652-1-alessandro@0x65c.net>", "list_archive_url": null, "date": "2026-04-05T18:08:26", "name": "[v2] target/arm: Move OMAP CP15 register definitions to cpregs-omap.c", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0ce3e78a3187614be2a16b5686ebaf26f2452490", "submitter": { "id": 91581, "url": "http://patchwork.ozlabs.org/api/people/91581/?format=api", "name": "Alessandro Ratti", "email": "alessandro@0x65c.net" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260405180826.729652-1-alessandro@0x65c.net/mbox/", "series": [ { "id": 498800, "url": "http://patchwork.ozlabs.org/api/series/498800/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498800", "date": "2026-04-05T18:08:26", "name": "[v2] target/arm: Move OMAP CP15 register definitions to cpregs-omap.c", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/498800/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220001/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220001/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=0x65c.net header.i=@0x65c.net header.a=rsa-sha256\n header.s=email header.b=Ln0CAtoM;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fpgVT2JS1z1yCs\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 06 Apr 2026 04:10:25 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w9RvF-0000s3-6j; Sun, 05 Apr 2026 14:10:09 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1)\n (envelope-from <bounce+db73df.54ef4-qemu-devel=nongnu.org@0x65c.net>)\n id 1w9RvC-0000q3-L0\n for qemu-devel@nongnu.org; Sun, 05 Apr 2026 14:10:06 -0400", "from v54.v54282eed.euw1.send.eu.mailgun.net ([185.250.239.4])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1)\n (envelope-from <bounce+db73df.54ef4-qemu-devel=nongnu.org@0x65c.net>)\n id 1w9Rv9-0003pq-Lh\n for qemu-devel@nongnu.org; Sun, 05 Apr 2026 14:10:06 -0400", "from fedora (pub158181109038.dh-hfc.datazug.ch [158.181.109.38]) by\n 156ae33b9e0caa96ebc0625acb347aacab81fa16d94b4849a1bfe8b0b0a7b333\n with SMTP id 69d2a574828f1b98b862e3dc; Sun, 05 Apr 2026 18:09:56 GMT" ], "DKIM-Signature": "a=rsa-sha256; v=1; c=relaxed/relaxed; d=0x65c.net; q=dns/txt;\n s=email; t=1775412596; x=1775419796;\n h=Content-Transfer-Encoding: Content-Type: MIME-Version: Message-ID: Date:\n Subject: Subject: Cc: To: To: From: From: Sender: Sender;\n bh=JOleBJBRpg381ow9j6GuXq2KaxSaFMOsthewtkYVuug=;\n b=Ln0CAtoMspEOp6Qy6twCZbzdn4UQ1qVHfI5fQQTk3m/lZncTlEXXGOtMGFDBmGuHd8dt1doJzyAcoWhKRp3P66ihwYzOi9S4VBtmY/Ub0o2dXIx8L51cxmUQKO1iN1Tvjx0vtzG1lxDEisIJqOMhHMvDrm0qqpUbXH3Zi8MPFVCRUWnGia72lapkVb682RGLM5FZWzbU5YONsCOCAByHqQJELXXrpacf4+7o1pDpdYVMNQZA65DehvFzlkU47WHnnOPDyYp73IFKgsGNkrlue0hbbWj1QGFL/djiuy+q9M5FACrdLkbaNOzbku11+vMnuSKdGFXmsuRifCKTrpRkbA==", "X-Mailgun-Sid": "WyJiNjdhNCIsInFlbXUtZGV2ZWxAbm9uZ251Lm9yZyIsIjU0ZWY0Il0=", "X-Mailgun-Sending-Ip": "185.250.239.4", "From": "Alessandro Ratti <alessandro@0x65c.net>", "To": "qemu-devel@nongnu.org", "Cc": "peter.maydell@linaro.org, pbonzini@redhat.com,\n Alessandro Ratti <alessandro@0x65c.net>, =?utf-8?q?Philippe_Mathieu-Daud?=\n\t=?utf-8?q?=C3=A9?= <philmd@linaro.org>", "Subject": "[PATCH v2] target/arm: Move OMAP CP15 register definitions to\n cpregs-omap.c", "Date": "Sun, 5 Apr 2026 20:08:26 +0200", "Message-ID": "<20260405180826.729652-1-alessandro@0x65c.net>", "X-Mailer": "git-send-email 2.53.0", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=185.250.239.4;\n envelope-from=bounce+db73df.54ef4-qemu-devel=nongnu.org@0x65c.net;\n helo=v54.v54282eed.euw1.send.eu.mailgun.net", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The OMAP CP15 registers are only relevant to system-mode emulation\nof OMAP SoCs. Move them out of the monolithic helper.c into a\ndedicated file, following the pattern of cpregs-pmu.c and\ncpregs-gcs.c. This reduces the size of helper.c and compiles\nthe OMAP-specific code out of CONFIG_USER_ONLY builds.\n\nSuggested-by: Paolo Bonzini <pbonzini@redhat.com>\nReviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nSigned-off-by: Alessandro Ratti <alessandro@0x65c.net>\n---\nv1 -> v2:\n- addresses Philippe's review adding the correct includes.\n\n target/arm/cpregs-omap-stub.c | 10 ++++\n target/arm/cpregs-omap.c | 88 +++++++++++++++++++++++++++++++++++\n target/arm/helper.c | 79 +------------------------------\n target/arm/internals.h | 2 +\n target/arm/meson.build | 2 +\n 5 files changed, 103 insertions(+), 78 deletions(-)\n create mode 100644 target/arm/cpregs-omap-stub.c\n create mode 100644 target/arm/cpregs-omap.c", "diff": "diff --git a/target/arm/cpregs-omap-stub.c b/target/arm/cpregs-omap-stub.c\nnew file mode 100644\nindex 0000000000..39c511205c\n--- /dev/null\n+++ b/target/arm/cpregs-omap-stub.c\n@@ -0,0 +1,10 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+\n+#include \"qemu/osdep.h\"\n+#include \"target/arm/cpu-qom.h\"\n+#include \"internals.h\"\n+\n+void define_omap_cp_regs(ARMCPU *cpu)\n+{\n+ g_assert_not_reached();\n+}\ndiff --git a/target/arm/cpregs-omap.c b/target/arm/cpregs-omap.c\nnew file mode 100644\nindex 0000000000..ac855baada\n--- /dev/null\n+++ b/target/arm/cpregs-omap.c\n@@ -0,0 +1,88 @@\n+/*\n+ * QEMU ARM OMAP CP15 register definitions\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"target/arm/cpu.h\"\n+#include \"target/arm/cpregs.h\"\n+#include \"target/arm/internals.h\"\n+\n+static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ env->cp15.c15_ticonfig = value & 0xe7;\n+ /* The OS_TYPE bit in this register changes the reported CPUID! */\n+ env->cp15.c0_cpuid = (value & (1 << 5)) ?\n+ ARM_CPUID_TI915T : ARM_CPUID_TI925T;\n+}\n+\n+static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ env->cp15.c15_threadid = value & 0xffff;\n+}\n+\n+static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ /* Wait-for-interrupt (deprecated) */\n+ cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT);\n+}\n+\n+static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ /*\n+ * On OMAP there are registers indicating the max/min index of dcache lines\n+ * containing a dirty line; cache flush operations have to reset these.\n+ */\n+ env->cp15.c15_i_max = 0x000;\n+ env->cp15.c15_i_min = 0xff0;\n+}\n+\n+static const ARMCPRegInfo omap_cp_reginfo[] = {\n+ { .name = \"DFSR\", .cp = 15, .crn = 5, .crm = CP_ANY,\n+ .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,\n+ .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),\n+ .resetvalue = 0, },\n+ { .name = \"\", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,\n+ .access = PL1_RW, .type = ARM_CP_NOP },\n+ { .name = \"TICONFIG\", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,\n+ .access = PL1_RW,\n+ .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,\n+ .writefn = omap_ticonfig_write },\n+ { .name = \"IMAX\", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,\n+ .access = PL1_RW,\n+ .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },\n+ { .name = \"IMIN\", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,\n+ .access = PL1_RW, .resetvalue = 0xff0,\n+ .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },\n+ { .name = \"THREADID\", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,\n+ .access = PL1_RW,\n+ .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,\n+ .writefn = omap_threadid_write },\n+ { .name = \"TI925T_STATUS\", .cp = 15, .crn = 15,\n+ .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,\n+ .type = ARM_CP_NO_RAW,\n+ .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },\n+ /*\n+ * TODO: Peripheral port remap register:\n+ * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller\n+ * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),\n+ * when MMU is off.\n+ */\n+ { .name = \"OMAP_CACHEMAINT\", .cp = 15, .crn = 7, .crm = CP_ANY,\n+ .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,\n+ .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,\n+ .writefn = omap_cachemaint_write },\n+ { .name = \"C9\", .cp = 15, .crn = 9,\n+ .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,\n+ .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },\n+};\n+\n+void define_omap_cp_regs(ARMCPU *cpu)\n+{\n+ define_arm_cp_regs(cpu, omap_cp_reginfo);\n+}\ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 7389f2988c..3ac88078aa 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -2900,83 +2900,6 @@ static const ARMCPRegInfo ttbcr2_reginfo = {\n },\n };\n \n-static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,\n- uint64_t value)\n-{\n- env->cp15.c15_ticonfig = value & 0xe7;\n- /* The OS_TYPE bit in this register changes the reported CPUID! */\n- env->cp15.c0_cpuid = (value & (1 << 5)) ?\n- ARM_CPUID_TI915T : ARM_CPUID_TI925T;\n-}\n-\n-static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,\n- uint64_t value)\n-{\n- env->cp15.c15_threadid = value & 0xffff;\n-}\n-\n-static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,\n- uint64_t value)\n-{\n-#ifdef CONFIG_USER_ONLY\n- g_assert_not_reached();\n-#else\n- /* Wait-for-interrupt (deprecated) */\n- cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT);\n-#endif\n-}\n-\n-static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,\n- uint64_t value)\n-{\n- /*\n- * On OMAP there are registers indicating the max/min index of dcache lines\n- * containing a dirty line; cache flush operations have to reset these.\n- */\n- env->cp15.c15_i_max = 0x000;\n- env->cp15.c15_i_min = 0xff0;\n-}\n-\n-static const ARMCPRegInfo omap_cp_reginfo[] = {\n- { .name = \"DFSR\", .cp = 15, .crn = 5, .crm = CP_ANY,\n- .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,\n- .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),\n- .resetvalue = 0, },\n- { .name = \"\", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,\n- .access = PL1_RW, .type = ARM_CP_NOP },\n- { .name = \"TICONFIG\", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,\n- .access = PL1_RW,\n- .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,\n- .writefn = omap_ticonfig_write },\n- { .name = \"IMAX\", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,\n- .access = PL1_RW,\n- .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },\n- { .name = \"IMIN\", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,\n- .access = PL1_RW, .resetvalue = 0xff0,\n- .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },\n- { .name = \"THREADID\", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,\n- .access = PL1_RW,\n- .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,\n- .writefn = omap_threadid_write },\n- { .name = \"TI925T_STATUS\", .cp = 15, .crn = 15,\n- .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,\n- .type = ARM_CP_NO_RAW,\n- .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },\n- /*\n- * TODO: Peripheral port remap register:\n- * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller\n- * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),\n- * when MMU is off.\n- */\n- { .name = \"OMAP_CACHEMAINT\", .cp = 15, .crn = 7, .crm = CP_ANY,\n- .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,\n- .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,\n- .writefn = omap_cachemaint_write },\n- { .name = \"C9\", .cp = 15, .crn = 9,\n- .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,\n- .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },\n-};\n-\n static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {\n /*\n * RAZ/WI the whole crn=15 space, when we don't have a more specific\n@@ -7043,7 +6966,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)\n define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);\n }\n if (arm_feature(env, ARM_FEATURE_OMAPCP)) {\n- define_arm_cp_regs(cpu, omap_cp_reginfo);\n+ define_omap_cp_regs(cpu);\n }\n if (arm_feature(env, ARM_FEATURE_STRONGARM)) {\n define_arm_cp_regs(cpu, strongarm_cp_reginfo);\ndiff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 8ec2750847..73fcb84a84 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -1796,6 +1796,8 @@ void define_at_insn_regs(ARMCPU *cpu);\n void define_pm_cpregs(ARMCPU *cpu);\n /* Add the cpreg definitions for GCS cpregs */\n void define_gcs_cpregs(ARMCPU *cpu);\n+/* Add the cpreg definitions for OMAP CP15 regs */\n+void define_omap_cp_regs(ARMCPU *cpu);\n \n /* Effective value of MDCR_EL2 */\n static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)\ndiff --git a/target/arm/meson.build b/target/arm/meson.build\nindex 6e0e504a40..192ac7c31e 100644\n--- a/target/arm/meson.build\n+++ b/target/arm/meson.build\n@@ -33,6 +33,7 @@ arm_user_ss.add(files(\n 'helper.c',\n 'vfp_fpscr.c',\n 'el2-stubs.c',\n+ 'cpregs-omap-stub.c',\n ))\n arm_user_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING',\n \t\t if_true: files('common-semi-target.c'))\n@@ -48,6 +49,7 @@ arm_common_system_ss.add(files(\n 'arm-powerctl.c',\n 'cortex-regs.c',\n 'cpregs-gcs.c',\n+ 'cpregs-omap.c',\n 'cpregs-pmu.c',\n 'cpu-irq.c',\n 'debug_helper.c',\n", "prefixes": [ "v2" ] }