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GET /api/patches/2219991/?format=api
{ "id": 2219991, "url": "http://patchwork.ozlabs.org/api/patches/2219991/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260405154154.46829-2-me@ziyao.cc/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260405154154.46829-2-me@ziyao.cc>", "list_archive_url": null, "date": "2026-04-05T15:41:53", "name": "[v3,1/2] PCI: cadence: Add flags for disabling ASPM support advertisement", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7ad669895334a32a4a35eaf188a765cee4b958b1", "submitter": { "id": 92226, "url": "http://patchwork.ozlabs.org/api/people/92226/?format=api", "name": "Yao Zi", "email": "me@ziyao.cc" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260405154154.46829-2-me@ziyao.cc/mbox/", "series": [ { "id": 498791, "url": "http://patchwork.ozlabs.org/api/series/498791/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=498791", "date": "2026-04-05T15:41:52", "name": "PCI/sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/498791/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219991/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219991/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51922-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit 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i=me@ziyao.cc;\n\th=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To;\n\tbh=04BMJdL2dI79QKtXQzctXE5shAcrq8uO/xheWpEk3q0=;\n\tb=pip/tquT1K6NZ4z681YAkIDO30fEWrGoU+4bDImKUG9YcikRB87mzcF4K9OPEzMj\n\tAMAy5PjxJMbm5D3vCkzuBV1i0OD/SXed6xGeppsW2tx7Ghbfg74tQpLpc3IfTnJeeRT\n\tGPF9E7dT+g1AMwMcQG5FE2GGW+OxlR2F9IWcUy70=", "From": "Yao Zi <me@ziyao.cc>", "To": "Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>,\n Siddharth Vadapalli <s-vadapalli@ti.com>, Hans Zhang <18255117159@163.com>,\n Kishon Vijay Abraham I <kishon@kernel.org>,\n Chen Wang <unicorn_wang@outlook.com>,\n Manikandan K Pillai <mpillai@cadence.com>,\n Christophe JAILLET <christophe.jaillet@wanadoo.fr>,\n Inochi Amaoto <inochiama@gmail.com>, Han Gao <rabenda.cn@gmail.com>", "Cc": "linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tYao Zi <me@ziyao.cc>,\n\tHan Gao <gaohan@iscas.ac.cn>", "Subject": "[PATCH v3 1/2] PCI: cadence: Add flags for disabling ASPM support\n advertisement", "Date": "Sun, 5 Apr 2026 15:41:53 +0000", "Message-ID": "<20260405154154.46829-2-me@ziyao.cc>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260405154154.46829-1-me@ziyao.cc>", "References": "<20260405154154.46829-1-me@ziyao.cc>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-ZohoMailClient": "External" }, "content": "Add flags for disabling advertisement of ASPM L0s/L1 states by clearing\ncorresponding bits in Link Capabilities Register through the local\nmanagement bus, allowing ASPM to be disabled on platforms which don't\nsupport it.\n\nSigned-off-by: Yao Zi <me@ziyao.cc>\nTested-by: Han Gao <gaohan@iscas.ac.cn>\n---\n .../controller/cadence/pcie-cadence-host.c | 7 +++++++\n drivers/pci/controller/cadence/pcie-cadence.h | 19 +++++++++++++++++++\n 2 files changed, 26 insertions(+)", "diff": "diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c\nindex db3154c1eccb..0bc9e6e90e0e 100644\n--- a/drivers/pci/controller/cadence/pcie-cadence-host.c\n+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c\n@@ -147,6 +147,13 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)\n \tcdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0);\n \tcdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);\n \n+\tvalue = cdns_pcie_rp_readl(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP);\n+\tif (rc->quirk_broken_aspm_l0s)\n+\t\tvalue &= ~PCI_EXP_LNKCAP_ASPM_L0S;\n+\tif (rc->quirk_broken_aspm_l1)\n+\t\tvalue &= ~PCI_EXP_LNKCAP_ASPM_L1;\n+\tcdns_pcie_rp_writel(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP, value);\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h\nindex 443033c607d7..32a5666204f5 100644\n--- a/drivers/pci/controller/cadence/pcie-cadence.h\n+++ b/drivers/pci/controller/cadence/pcie-cadence.h\n@@ -115,6 +115,8 @@ struct cdns_pcie {\n * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk\n * @ecam_supported: Whether the ECAM is supported\n * @no_inbound_map: Whether inbound mapping is supported\n+ * @quirk_broken_aspm_l0s: Disable ASPM L0s support as quirk.\n+ * @quirk_broken_aspm_l1: Disable ASPM L1 support as quirk.\n */\n struct cdns_pcie_rc {\n \tstruct cdns_pcie\tpcie;\n@@ -127,6 +129,8 @@ struct cdns_pcie_rc {\n \tunsigned int\t\tquirk_detect_quiet_flag:1;\n \tunsigned int ecam_supported:1;\n \tunsigned int no_inbound_map:1;\n+\tunsigned int quirk_broken_aspm_l0s:1;\n+\tunsigned int quirk_broken_aspm_l1:1;\n };\n \n /**\n@@ -344,6 +348,21 @@ static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg)\n \treturn cdns_pcie_read_sz(addr, 0x2);\n }\n \n+static inline void cdns_pcie_rp_writel(struct cdns_pcie *pcie,\n+\t\t\t\t u32 reg, u32 value)\n+{\n+\tvoid __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;\n+\n+\tcdns_pcie_write_sz(addr, 0x4, value);\n+}\n+\n+static inline u32 cdns_pcie_rp_readl(struct cdns_pcie *pcie, u32 reg)\n+{\n+\tvoid __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;\n+\n+\treturn cdns_pcie_read_sz(addr, 0x4);\n+}\n+\n static inline void cdns_pcie_hpa_rp_writeb(struct cdns_pcie *pcie,\n \t\t\t\t\t u32 reg, u8 value)\n {\n", "prefixes": [ "v3", "1/2" ] }