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GET /api/patches/2219990/?format=api
{ "id": 2219990, "url": "http://patchwork.ozlabs.org/api/patches/2219990/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260405154154.46829-3-me@ziyao.cc/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260405154154.46829-3-me@ziyao.cc>", "list_archive_url": null, "date": "2026-04-05T15:41:54", "name": "[v3,2/2] PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "dd44d6d22f73136a706b486bfa4e657530af5028", "submitter": { "id": 92226, "url": "http://patchwork.ozlabs.org/api/people/92226/?format=api", "name": "Yao Zi", "email": "me@ziyao.cc" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260405154154.46829-3-me@ziyao.cc/mbox/", "series": [ { "id": 498791, "url": "http://patchwork.ozlabs.org/api/series/498791/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=498791", "date": "2026-04-05T15:41:52", "name": "PCI/sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/498791/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219990/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219990/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51921-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ziyao.cc header.i=me@ziyao.cc header.a=rsa-sha256\n header.s=zmail header.b=OE3t4X7j;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-51921-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=ziyao.cc header.i=me@ziyao.cc\n header.b=\"OE3t4X7j\"", "smtp.subspace.kernel.org;\n arc=pass smtp.client-ip=136.143.188.15", "smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=ziyao.cc", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=ziyao.cc" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fpcDN3vWDz1yCs\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 06 Apr 2026 01:43:00 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id A482A30062F1\n\tfor <incoming@patchwork.ozlabs.org>; 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arc=pass smtp.client-ip=136.143.188.15", "i=1; mx.zohomail.com;\n\tdkim=pass header.i=ziyao.cc;\n\tspf=pass smtp.mailfrom=me@ziyao.cc;\n\tdmarc=pass header.from=<me@ziyao.cc>" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1775403753;\n\ts=zmail; d=ziyao.cc; i=me@ziyao.cc;\n\th=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To;\n\tbh=1PVEcOp97E5tLdQMKMMvg6mvW4Dcd/k5d5K5tE7bKKg=;\n\tb=OE3t4X7j0mWqeHfTN+gQ2lxn08PU8iaaIXCal1VFExyrcXBrpNOHedo0i1AEnD/D\n\tcZq6qk5YcReOYy0wHoGyYeFd1Np+Ns0wdKSqgfqGpQD502ke/0f4LSr3HsEJ9iod53y\n\tbeDmubHo3BGzzPe0KpELV9m4SNZWXcB5CTIMLDbI=", "From": "Yao Zi <me@ziyao.cc>", "To": "Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>,\n Siddharth Vadapalli <s-vadapalli@ti.com>, Hans Zhang <18255117159@163.com>,\n Kishon Vijay Abraham I <kishon@kernel.org>,\n Chen Wang <unicorn_wang@outlook.com>,\n Manikandan K Pillai <mpillai@cadence.com>,\n Christophe JAILLET <christophe.jaillet@wanadoo.fr>,\n Inochi Amaoto <inochiama@gmail.com>, Han Gao <rabenda.cn@gmail.com>", "Cc": "linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tYao Zi <me@ziyao.cc>,\n\tHan Gao <gaohan@iscas.ac.cn>", "Subject": "[PATCH v3 2/2] PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root\n Ports", "Date": "Sun, 5 Apr 2026 15:41:54 +0000", "Message-ID": "<20260405154154.46829-3-me@ziyao.cc>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260405154154.46829-1-me@ziyao.cc>", "References": "<20260405154154.46829-1-me@ziyao.cc>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-ZohoMailClient": "External" }, "content": "Since commit f3ac2ff14834 (\"PCI/ASPM: Enable all ClockPM and ASPM\nstates for devicetree platforms\") force enable ASPM on all device tree\nplatform, the SG2042 root port breaks as it advertises L0s and L1\ncapabilities without supporting it.\n\nSet ASPM quirks to disable advertisement of L0s and L1 support, so\nit doesn't try to enable those states.\n\nFixes: 4e27aca4881a (\"riscv: sophgo: dts: add PCIe controllers for SG2042\")\nCo-developed-by: Inochi Amaoto <inochiama@gmail.com>\nSigned-off-by: Inochi Amaoto <inochiama@gmail.com>\nSigned-off-by: Yao Zi <me@ziyao.cc>\nTested-by: Han Gao <gaohan@iscas.ac.cn>\n---\n drivers/pci/controller/cadence/pcie-sg2042.c | 2 ++\n 1 file changed, 2 insertions(+)", "diff": "diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c\nindex 0c50c74d03ee..4a2af4d0713e 100644\n--- a/drivers/pci/controller/cadence/pcie-sg2042.c\n+++ b/drivers/pci/controller/cadence/pcie-sg2042.c\n@@ -48,6 +48,8 @@ static int sg2042_pcie_probe(struct platform_device *pdev)\n \tbridge->child_ops = &sg2042_pcie_child_ops;\n \n \trc = pci_host_bridge_priv(bridge);\n+\trc->quirk_broken_aspm_l0s = 1;\n+\trc->quirk_broken_aspm_l1 = 1;\n \tpcie = &rc->pcie;\n \tpcie->dev = dev;\n \n", "prefixes": [ "v3", "2/2" ] }