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GET /api/patches/2219795/?format=api
{ "id": 2219795, "url": "http://patchwork.ozlabs.org/api/patches/2219795/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260404133934.2733015-1-yoshinori.sato@nifty.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260404133934.2733015-1-yoshinori.sato@nifty.com>", "list_archive_url": null, "date": "2026-04-04T13:39:32", "name": "[RFC,v2] RX: enable LRA is default", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d06e65984ecc580d9074a7cc3333ab1e73ce2daf", "submitter": { "id": 91050, "url": "http://patchwork.ozlabs.org/api/people/91050/?format=api", "name": "Yoshinori Sato", "email": "yoshinori.sato@nifty.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260404133934.2733015-1-yoshinori.sato@nifty.com/mbox/", "series": [ { "id": 498726, "url": "http://patchwork.ozlabs.org/api/series/498726/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=498726", "date": "2026-04-04T13:39:32", "name": "[RFC,v2] RX: enable LRA is default", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/498726/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219795/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219795/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nifty.com header.i=@nifty.com header.a=rsa-sha256\n header.s=default-1th84yt82rvi header.b=N+0AoeCS;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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a=rsa-sha256; d=sourceware.org; s=key;\n t=1775309984; c=relaxed/simple;\n bh=h2WGss8JbxQL+3TZGoIyQA/t/aba3cadj0OCMgIKKYM=;\n h=From:To:Subject:Date:Message-ID:MIME-Version:DKIM-Signature;\n b=KmfTrhpQRlSXngQaeQgvo1+O4GPDLcdKzmBytT6I/ix527bj1xu0Br+qGtYDjEQL5oFO5OsRZIynxu6KYTaXnakapEcpdcnUbhhjWKHvQyIf+BlfOZRCEUuj0EIl5vTdIS457nBS2vuTRodML1wZjwltCL9nsKpR/oM8CznMsVw=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "From": "Yoshinori Sato <yoshinori.sato@nifty.com>", "To": "gcc-patches@gcc.gnu.org", "Cc": "Yoshinori Sato <yoshinori.sato@nifty.com>", "Subject": "[RFC PATCH v2] RX: enable LRA is default", "Date": "Sat, 4 Apr 2026 22:39:32 +0900", "Message-ID": "<20260404133934.2733015-1-yoshinori.sato@nifty.com>", "X-Mailer": "git-send-email 2.47.3", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com;\n s=default-1th84yt82rvi; t=1775309980;\n bh=KBiA/KQOaDgrZxbrLSCFc5zRWo+W+xLlAJaLhv3d0aQ=;\n h=From:To:Cc:Subject:Date;\n b=N+0AoeCSsFcTs+nFyRiFR4cLkSNx8h0OP4WFro83P1wSydzqF+JwiMz2pbjvEyM/LcovVMwT\n L4rJsjBZDTYDg8JybkjXg3DOlST6DFgSxtnAVWOWpAaWXnibP3vlhO1pH5//xuXfHHaGb5iM8G\n fVsDh+b7aKoM4puEwNLg0n8oLAnV/vsgLrE0mu/+niljiTQwjYxjPBkAVQUJHlvUGIgB5oHvWg\n p/WnuT/TxfdxMtYs1Sphnb9nGyZAOOXcC3sy4k4g+64Uq1/Wo6GRWkyYREbg3GrWaGjHj5vMaM\n mfK3qqLShpbaTs6gj2HsIapl9kMNLiBEz1iFRlXBY9XBdy/g==", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Always enable LRA on RX targets.\nSome Machine Descriptions did not work properly with LRA,\nso their definitions have been changed.\n\nv1 -> v2\nFix WORD_REGISTER_OPERATIONS.\nCleanup shift operations.\n\nChangeLog:\n\t* gcc/config/rx/predicates.md (rx_double_src_operand): New.\n\t(rx_double_dest_operand): New.\n\t* gcc/config/rx/rx-protos.h (rx_split_double_move): New helper proto.\n\t(rx_relax_double_operands): Likewise.\n\t* gcc/config/rx/rx.cc (rx_gen_move_template):\n\tFix operation size in unsigned extend.\n\t(rx_gen_move_template): Remove DImode and DFmode.\n\t(rx_enable_lra): Remove.\n\t(rx_hard_regno_mode_ok): Add ATTRIBUTE_UNUSED.\n\t(rx_modes_tieable_p): Add int case.\n\t(rx_get_subword): New. Double word move helper.\n\t(rx_split_double_move): Likewise.\n\t(rx_relax_double_operands): Likewise.\n\t(TARGET_LRA_P): Remove.\n\t* gcc/config/rx/rx.md (mov<register_modes:mode>):\n\tThe operand variation has been made compatible with LRA.\n\t(*mov<register_modes:mode>_internal):\n\tA penalty has been added to reduce the register allocation load of the LRA.\n\t(movdi): Limit the arguments to make register allocation easier.\n\t(movdf): Likewise.\n\t(movdi_internal): New.\n\t(movdf_internal): New.\n\t(addsi3_pid): New. Handling UNSPEC_PID_ADDR.\n\t(adddi3): New. simplify implementation.\n\t(subdi3): Likewise.\n\t(addsi3_flags): adddi3 is not use. Remove it.\n\t(adc_internal): Likewise.\n\t(adc_flags): Likewise.\n\t(adddi3_internal): Likewise.\n\t(subsi3_flags): subsi3 not use. Remove it.\n\t(sbb_internal): Likewise.\n\t(*sbb_flags): Likewise.\n\t(subdi3): Likewise.\n\t(addsi3_lra): New. alternative addptrsi3.\n\t(ashlsi3_lra): likewise.\n\t* gcc/config/rx/rx.opt (mlra): Remove.\n\nSigned-off-by: Yoshinori Sato <yoshinori.sato@nifty.com>\n---\n gcc/config/rx/predicates.md | 14 ++\n gcc/config/rx/rx-protos.h | 2 +\n gcc/config/rx/rx.cc | 112 +++++++++---\n gcc/config/rx/rx.md | 348 ++++++++++++------------------------\n gcc/config/rx/rx.opt | 6 -\n 5 files changed, 215 insertions(+), 267 deletions(-)", "diff": "diff --git a/gcc/config/rx/predicates.md b/gcc/config/rx/predicates.md\nindex aa926be31ac..37fd63b538a 100644\n--- a/gcc/config/rx/predicates.md\n+++ b/gcc/config/rx/predicates.md\n@@ -307,3 +307,17 @@\n (define_predicate \"rshift_operator\"\n (match_code \"ashiftrt,lshiftrt\")\n )\n+\n+;; DI and DF are expanded into multiple mov instructions,\n+;; so they require stronger constraints than regular move.\n+(define_predicate \"rx_double_src_operand\"\n+ (ior (and (match_code \"reg,subreg,const_int,const_double\")\n+ (match_operand 0 \"general_operand\"))\n+ (and (match_code \"mem\")\n+ (match_operand 0 \"rx_restricted_mem_operand\"))))\n+\n+(define_predicate \"rx_double_dest_operand\"\n+ (ior (and (match_code \"reg,subreg\")\n+ (match_operand 0 \"general_operand\"))\n+ (and (match_code \"mem\")\n+ (match_operand 0 \"rx_restricted_mem_operand\"))))\ndiff --git a/gcc/config/rx/rx-protos.h b/gcc/config/rx/rx-protos.h\nindex 829882b0bc8..5a36ef26948 100644\n--- a/gcc/config/rx/rx-protos.h\n+++ b/gcc/config/rx/rx-protos.h\n@@ -70,6 +70,8 @@ extern void rx_copy_reg_dead_or_unused_notes (rtx reg, const rtx_insn* src,\n \n extern bool rx_fuse_in_memory_bitop (rtx* operands, rtx_insn* curr_insn,\n \t\t\t\t rtx (*gen_insn)(rtx, rtx));\n+extern void rx_split_double_move (rtx* operands, machine_mode mode);\n+extern void rx_relax_double_operands (rtx* operands, machine_mode mode);\n \n /* Result value of rx_find_set_of_reg. */\n struct set_of_reg\ndiff --git a/gcc/config/rx/rx.cc b/gcc/config/rx/rx.cc\nindex 902e756a34e..1c552fe0649 100644\n--- a/gcc/config/rx/rx.cc\n+++ b/gcc/config/rx/rx.cc\n@@ -970,7 +970,8 @@ rx_gen_move_template (rtx * operands, bool is_movu)\n rtx src = operands[1];\n \n /* Decide which extension, if any, should be given to the move instruction. */\n- switch (CONST_INT_P (src) ? GET_MODE (dest) : GET_MODE (src))\n+ /* When zero-extending, always check the size of the source. */\n+ switch ((is_movu || MEM_P(src)) ? GET_MODE (src) : GET_MODE(dest))\n {\n case E_QImode:\n /* The .B extension is not valid when\n@@ -984,10 +985,9 @@ rx_gen_move_template (rtx * operands, bool is_movu)\n \t loading an immediate into a register. */\n \textension = \".W\";\n break;\n- case E_DFmode:\n- case E_DImode:\n case E_SFmode:\n case E_SImode:\n+ gcc_assert(! is_movu);\n extension = \".L\";\n break;\n case E_VOIDmode:\n@@ -1025,18 +1025,8 @@ rx_gen_move_template (rtx * operands, bool is_movu)\n else\n dst_template = \"%0\";\n \n- if (GET_MODE (dest) == DImode || GET_MODE (dest) == DFmode)\n- {\n- gcc_assert (! is_movu);\n-\n- if (REG_P (src) && REG_P (dest) && (REGNO (dest) == REGNO (src) + 1))\n-\tsprintf (out_template, \"mov.L\\t%%H1, %%H0 ! mov.L\\t%%1, %%0\");\n- else\n-\tsprintf (out_template, \"mov.L\\t%%1, %%0 ! mov.L\\t%%H1, %%H0\");\n- }\n- else\n- sprintf (out_template, \"%s%s\\t%s, %s\", is_movu ? \"movu\" : \"mov\",\n-\t extension, src_template, dst_template);\n+ sprintf (out_template, \"%s%s\\t%s, %s\", is_movu ? \"movu\" : \"mov\",\n+\t extension, src_template, dst_template);\n return out_template;\n }\n \f\n@@ -3495,12 +3485,6 @@ rx_ok_to_inline (tree caller, tree callee)\n || lookup_attribute (\"gnu_inline\", DECL_ATTRIBUTES (callee)) != NULL_TREE;\n }\n \n-static bool\n-rx_enable_lra (void)\n-{\n- return TARGET_ENABLE_LRA;\n-}\n-\n rx_atomic_sequence::rx_atomic_sequence (const_tree fun_decl)\n {\n if (is_fast_interrupt_func (fun_decl) || is_interrupt_func (fun_decl))\n@@ -3617,7 +3601,7 @@ rx_hard_regno_nregs (unsigned int, machine_mode mode)\n /* Implement TARGET_HARD_REGNO_MODE_OK. */\n \n static bool\n-rx_hard_regno_mode_ok (unsigned int regno, machine_mode)\n+rx_hard_regno_mode_ok (unsigned int regno, machine_mode mode ATTRIBUTE_UNUSED)\n {\n return REGNO_REG_CLASS (regno) == GR_REGS;\n }\n@@ -3627,7 +3611,9 @@ rx_hard_regno_mode_ok (unsigned int regno, machine_mode)\n static bool\n rx_modes_tieable_p (machine_mode mode1, machine_mode mode2)\n {\n- return ((GET_MODE_CLASS (mode1) == MODE_FLOAT\n+ return (GET_MODE_CLASS (mode1) == MODE_INT\n+\t && GET_MODE_CLASS (mode2) == MODE_INT)\n+ || ((GET_MODE_CLASS (mode1) == MODE_FLOAT\n \t || GET_MODE_CLASS (mode1) == MODE_COMPLEX_FLOAT)\n \t == (GET_MODE_CLASS (mode2) == MODE_FLOAT\n \t || GET_MODE_CLASS (mode2) == MODE_COMPLEX_FLOAT));\n@@ -3644,7 +3630,82 @@ rx_c_mode_for_floating_type (enum tree_index ti)\n return TARGET_64BIT_DOUBLES ? DFmode : SFmode;\n return default_mode_for_floating_type (ti);\n }\n+\n+static rtx\n+rx_get_subword (rtx op, machine_mode mode, int reg_offset)\n+{\n+ int mem_offset = reg_offset * 4;\n+ if (TARGET_BIG_ENDIAN_DATA)\n+ mem_offset = 4 - mem_offset;\n+\n+ if (MEM_P (op))\n+ {\n+ rtx addr = XEXP (op, 0);\n+ rtx new_addr = plus_constant (Pmode, addr, mem_offset);\n+ rtx new_mem = gen_rtx_MEM (SImode, new_addr);\n+ MEM_COPY_ATTRIBUTES (new_mem, op);\n+ return new_mem;\n+ }\n+\n+ if (REG_P (op) && REGNO (op) < FIRST_PSEUDO_REGISTER)\n+ return gen_rtx_REG (SImode, REGNO (op) + reg_offset);\n+\n+ return simplify_gen_subreg (SImode, op, mode, mem_offset);\n+}\n+\n+void\n+rx_split_double_move (rtx * operands, machine_mode mode)\n+{\n+ rtx dest = operands[0];\n+ rtx src = operands[1];\n+\n+ rtx real_dest = (GET_CODE (dest) == SUBREG) ? SUBREG_REG (dest) : dest;\n+ rtx real_src = (GET_CODE (src) == SUBREG) ? SUBREG_REG (src) : src;\n+\n+ rtx dest_low, dest_high, src_low, src_high;\n+\n+ src_low = rx_get_subword (MEM_P (real_src) ? real_src : src, mode, 0);\n+ src_high = rx_get_subword (MEM_P (real_src) ? real_src : src, mode, 1);\n+\n+ dest_low = rx_get_subword (MEM_P (real_dest) ? real_dest : dest, mode, 0);\n+ dest_high = rx_get_subword (MEM_P (real_dest) ? real_dest : dest, mode, 1);\n+\n+ if (REG_P (operands[0]) && reg_overlap_mentioned_p (dest_low, operands[1]))\n+ {\n+ emit_move_insn (dest_high, src_high);\n+ emit_move_insn (dest_low, src_low);\n+ }\n+ else\n+ {\n+ emit_move_insn (dest_low, src_low);\n+ emit_move_insn (dest_high, src_high);\n+ }\n+}\n+\n+void\n+rx_relax_double_operands(rtx * operands, machine_mode mode)\n+{\n+ if (MEM_P (operands[0]) && !rx_restricted_mem_operand (operands[0], mode))\n+ {\n+ rtx addr = XEXP (operands[0], 0);\n+ addr = force_reg (Pmode, addr);\n+ operands[0] = replace_equiv_address (operands[0], addr);\n+ }\n+\n+ if (MEM_P (operands[1]) && !rx_restricted_mem_operand (operands[1], mode))\n+ {\n+ rtx addr = XEXP (operands[1], 0);\n+ addr = force_reg (Pmode, addr);\n+ operands[1] = replace_equiv_address (operands[1], addr);\n+ }\n+\n+ if (MEM_P (operands[0]) && !REG_P (operands[1]))\n+ {\n+ operands[1] = force_reg (mode, operands[1]);\n+ }\n+}\n \f\n+\n #undef TARGET_NARROW_VOLATILE_BITFIELD\n #define TARGET_NARROW_VOLATILE_BITFIELD\t\trx_narrow_volatile_bitfield\n \n@@ -3786,16 +3847,13 @@ rx_c_mode_for_floating_type (enum tree_index ti)\n #undef TARGET_WARN_FUNC_RETURN\n #define TARGET_WARN_FUNC_RETURN \t\trx_warn_func_return\n \n-#undef TARGET_LRA_P\n-#define TARGET_LRA_P \t\t\t\trx_enable_lra\n-\n #undef TARGET_HARD_REGNO_NREGS\n #define TARGET_HARD_REGNO_NREGS\t\t\trx_hard_regno_nregs\n #undef TARGET_HARD_REGNO_MODE_OK\n #define TARGET_HARD_REGNO_MODE_OK\t\trx_hard_regno_mode_ok\n \n #undef TARGET_MODES_TIEABLE_P\n-#define TARGET_MODES_TIEABLE_P\t\t\trx_modes_tieable_p\n+#define TARGET_MODES_TIEABLE_P rx_modes_tieable_p\n \n #undef TARGET_RTX_COSTS\n #define TARGET_RTX_COSTS rx_rtx_costs\ndiff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md\nindex 808dfc8b35a..8e9efd195a3 100644\n--- a/gcc/config/rx/rx.md\n+++ b/gcc/config/rx/rx.md\n@@ -575,26 +575,22 @@\n \"\"\n {\n if (MEM_P (operands[0]) && MEM_P (operands[1]))\n- operands[1] = copy_to_mode_reg (<register_modes:MODE>mode, operands[1]);\n+ operands[1] = force_reg (<register_modes:MODE>mode, operands[1]);\n operands[0] = rx_maybe_pidify_operand (operands[0], 0);\n operands[1] = rx_maybe_pidify_operand (operands[1], 0);\n- if (GET_CODE (operands[0]) != REG\n-\t&& GET_CODE (operands[1]) == PLUS)\n- operands[1] = copy_to_mode_reg (<register_modes:MODE>mode, operands[1]);\n- if (GET_CODE (operands[1]) == PLUS && GET_MODE (operands[1]) == SImode)\n- {\n- emit_insn (gen_addsi3 (operands[0], XEXP (operands[1], 0), XEXP (operands[1], 1)));\n- DONE;\n- }\n+ if (MEM_P (operands[0]) && GET_CODE (operands[1]) == PLUS)\n+ operands[1] = force_reg (<register_modes:MODE>mode, operands[1]);\n if (CONST_INT_P (operand1)\n && ! rx_is_legitimate_constant (<register_modes:MODE>mode, operand1))\n FAIL;\n }\n )\n \n+;; To reduce the register allocation load in LRA,\n+;; a constraint is applied to penalize store operations to memory.\n (define_insn \"*mov<register_modes:mode>_internal\"\n [(set (match_operand:register_modes\n-\t 0 \"nonimmediate_operand\" \"=r,r,r,r,r,r,m,Q,Q,Q,Q,r\")\n+\t 0 \"nonimmediate_operand\" \"=r,r,r,r,r,r,?m,?Q,?Q,?Q,?Q,r\")\n \t(match_operand:register_modes\n \t 1 \"general_operand\" \"Int08,Sint16,Sint24,i,r,m,r,Int08,Sint16,Sint24,i,RpdaRpid\"))]\n \"\"\n@@ -603,6 +599,58 @@\n (set_attr \"timings\" \"11,11,11,11,11,12,11,11,11,11,11,11\")]\n )\n \n+(define_expand \"movdi\"\n+ [(set (match_operand:DI 0 \"nonimmediate_operand\" \"\")\n+ (match_operand:DI 1 \"general_operand\" \"\"))]\n+ \"\"\n+ {\n+ rx_relax_double_operands(operands, DImode);\n+\n+ emit_insn (gen_movdi_internal (operands[0], operands[1]));\n+ DONE;\n+ }\n+)\n+\n+(define_insn_and_split \"movdi_internal\"\n+ [(set (match_operand:DI 0 \"rx_double_dest_operand\" \"=r,r,m\")\n+ (match_operand:DI 1 \"rx_double_src_operand\" \"ri,m,r\"))]\n+ \"\"\n+ \"#\"\n+ \"reload_completed\"\n+ [(const_int 0)]\n+ {\n+ rx_split_double_move (operands, DImode);\n+ DONE;\n+ }\n+ [(set_attr \"length\" \"8\")]\n+)\n+\n+(define_expand \"movdf\"\n+ [(set (match_operand:DF 0 \"nonimmediate_operand\" \"\")\n+ (match_operand:DF 1 \"general_operand\" \"\"))]\n+ \"\"\n+ {\n+ rx_relax_double_operands(operands, DFmode);\n+\n+ emit_insn (gen_movdf_internal (operands[0], operands[1]));\n+ DONE;\n+ }\n+)\n+\n+(define_insn_and_split \"movdf_internal\"\n+ [(set (match_operand:DF 0 \"rx_double_dest_operand\" \"=r,r,m\")\n+ (match_operand:DF 1 \"rx_double_src_operand\" \"rF,m,r\"))]\n+ \"\"\n+ \"#\"\n+ \"reload_completed\"\n+ [(const_int 0)]\n+ {\n+ rx_split_double_move (operands, DFmode);\n+ DONE;\n+ }\n+ [(set_attr \"length\" \"8\")]\n+)\n+\n (define_insn \"extend<small_int_modes:mode>si2\"\n [(set (match_operand:SI 0 \"register_operand\" \"=r,r\")\n (sign_extend:SI (match_operand:small_int_modes\n@@ -928,50 +976,27 @@\n (set_attr \"length\" \"2,2,2,3,4,5,6,2,3,3,4,5,6,5\")]\n )\n \n-;; A helper to expand the above with the CC_MODE filled in.\n-(define_expand \"addsi3_flags\"\n- [(parallel [(set (reg:CC_ZSC CC_REG)\n-\t\t (compare:CC_ZSC\n-\t\t (plus:SI (match_operand:SI 1 \"register_operand\")\n-\t\t\t (match_operand:SI 2 \"rx_source_operand\"))\n-\t\t (const_int 0)))\n-\t (set (match_operand:SI 0 \"register_operand\")\n-\t\t (plus:SI (match_dup 1) (match_dup 2)))])]\n-)\n-\n-(define_insn \"adc_internal\"\n- [(set (match_operand:SI 0 \"register_operand\" \"=r,r,r,r,r,r\")\n-\t(plus:SI\n-\t (plus:SI\n-\t (ltu:SI (reg:CC CC_REG) (const_int 0))\n-\t (match_operand:SI 1 \"register_operand\" \"%0,0,0,0,0,0\"))\n-\t (match_operand:SI 2 \"rx_source_operand\" \"r,Sint08,Sint16,Sint24,i,Q\")))\n- (clobber (reg:CC CC_REG))]\n- \"reload_completed\"\n- \"adc\\t%2, %0\"\n- [(set_attr \"timings\" \"11,11,11,11,11,33\")\n- (set_attr \"length\" \"3,4,5,6,7,6\")]\n+(define_insn \"addsi3_pid\"\n+ [(set (match_operand:SI 0 \"register_operand\" \"=r\")\n+ (plus:SI (match_operand:SI 1 \"register_operand\" \"%0\")\n+ (const:SI (unspec:SI [(match_operand:SI 2 \"immediate_operand\" \"i\")] UNSPEC_PID_ADDR))))]\n+ \"\"\n+ \"add\\t%2, %0\"\n+ [(set_attr \"length\" \"6\")\n+ (set_attr \"timings\" \"11\")]\n )\n \n-(define_insn \"*adc_flags\"\n- [(set (reg CC_REG)\n-\t(compare\n-\t (plus:SI\n-\t (plus:SI\n-\t (ltu:SI (reg:CC CC_REG) (const_int 0))\n-\t (match_operand:SI 1 \"register_operand\" \"%0,0,0,0,0,0\"))\n-\t (match_operand:SI 2 \"rx_source_operand\" \"r,Sint08,Sint16,Sint24,i,Q\"))\n-\t (const_int 0)))\n- (set (match_operand:SI\t0 \"register_operand\" \"=r,r,r,r,r,r\")\n-\t(plus:SI\n-\t (plus:SI\n-\t (ltu:SI (reg:CC CC_REG) (const_int 0))\n-\t (match_dup 1))\n-\t (match_dup 2)))]\n- \"reload_completed && rx_match_ccmode (insn, CC_ZSCmode)\"\n- \"adc\\t%2, %0\"\n- [(set_attr \"timings\" \"11,11,11,11,11,33\")\n- (set_attr \"length\" \"3,4,5,6,7,6\")]\n+(define_insn \"adddi3\"\n+ [(set (match_operand:DI 0 \"register_operand\" \"=r,r,r\")\n+\t(plus:DI (match_operand:DI 1 \"register_operand\" \"%0,0,0\")\n+\t\t (match_operand:DI 2 \"rx_source_operand\" \"r,i,Q\")))\n+ (clobber (reg:CC CC_REG))]\n+ \"\"\n+ {\n+ return \"add\\t%L2, %L0\\n\\tadc\\t%H2, %H0\";\n+ }\n+ [(set_attr \"length\" \"6\")\n+ (set_attr \"timings\" \"22\")]\n )\n \n ;; Peepholes to match:\n@@ -1007,93 +1032,6 @@\n \t\t (plus:SI (match_dup 1) (const_int 0)))])]\n )\n \n-(define_expand \"adddi3\"\n- [(set (match_operand:DI 0 \"register_operand\")\n-\t(plus:DI (match_operand:DI 1 \"register_operand\")\n-\t\t (match_operand:DI 2 \"rx_source_operand\")))]\n- \"\"\n-{\n- rtx op0l, op0h, op1l, op1h, op2l, op2h;\n-\n- op0l = gen_lowpart (SImode, operands[0]);\n- op1l = gen_lowpart (SImode, operands[1]);\n- op2l = gen_lowpart (SImode, operands[2]);\n- op0h = gen_highpart (SImode, operands[0]);\n- op1h = gen_highpart (SImode, operands[1]);\n- op2h = gen_highpart_mode (SImode, DImode, operands[2]);\n-\n- emit_insn (gen_adddi3_internal (op0l, op0h, op1l, op2l, op1h, op2h));\n- DONE;\n-})\n-\n-(define_insn_and_split \"adddi3_internal\"\n- [(set (match_operand:SI 0 \"register_operand\" \"=&r\")\n-\t(plus:SI (match_operand:SI 2 \"register_operand\" \"r\")\n-\t\t (match_operand:SI 3 \"rx_source_operand\" \"riQ\")))\n- (set (match_operand:SI 1 \"register_operand\" \"=r\")\n-\t(plus:SI\n-\t (plus:SI\n-\t (ltu:SI (plus:SI (match_dup 2) (match_dup 3)) (match_dup 2))\n-\t (match_operand:SI 4 \"register_operand\" \"%1\"))\n-\t (match_operand:SI 5 \"rx_source_operand\" \"riQ\")))\n- (clobber (match_scratch:SI 6 \"=&r\"))\n- (clobber (reg:CC CC_REG))]\n- \"\"\n- \"#\"\n- \"reload_completed\"\n- [(const_int 0)]\n-{\n- rtx op0l = operands[0];\n- rtx op0h = operands[1];\n- rtx op1l = operands[2];\n- rtx op2l = operands[3];\n- rtx op1h = operands[4];\n- rtx op2h = operands[5];\n- rtx scratch = operands[6];\n- rtx x;\n-\n- if (reg_overlap_mentioned_p (op0l, op1h))\n- {\n- emit_move_insn (scratch, op0l);\n- op1h = scratch;\n- if (reg_overlap_mentioned_p (op0l, op2h))\n-\top2h = scratch;\n- }\n- else if (reg_overlap_mentioned_p (op0l, op2h))\n- {\n- emit_move_insn (scratch, op0l);\n- op2h = scratch;\n- }\n-\n- if (rtx_equal_p (op0l, op1l))\n- ;\n- /* It is preferable that op0l == op1l... */\n- else if (rtx_equal_p (op0l, op2l))\n- x = op1l, op1l = op2l, op2l = x;\n- /* ... but it is only a requirement if op2l == MEM. */\n- else if (MEM_P (op2l))\n- {\n- /* Let's hope that we still have a scratch register free. */\n- gcc_assert (op1h != scratch);\n- emit_move_insn (scratch, op2l);\n- op2l = scratch;\n- }\n-\n- emit_insn (gen_addsi3_flags (op0l, op1l, op2l));\n-\n- if (rtx_equal_p (op0h, op1h))\n- ;\n- else if (rtx_equal_p (op0h, op2h))\n- x = op1h, op1h = op2h, op2h = x;\n- else\n- {\n- emit_move_insn (op0h, op1h);\n- op1h = op0h;\n- }\n- emit_insn (gen_adc_internal (op0h, op1h, op2h));\n- DONE;\n-})\n-\n (define_insn_and_split \"andsi3\"\n [(set (match_operand:SI 0 \"register_operand\" \"=r,r,r,r,r,r,r,r,r\")\n \t(and:SI (match_operand:SI 1 \"register_operand\" \"%0,0,0,0,0,0,r,r,0\")\n@@ -1650,89 +1588,18 @@\n (set_attr \"length\" \"2,2,6,3,5\")]\n )\n \n-;; A helper to expand the above with the CC_MODE filled in.\n-(define_expand \"subsi3_flags\"\n- [(parallel [(set (reg:CC_ZSC CC_REG)\n-\t\t (compare:CC_ZSC\n-\t\t (minus:SI (match_operand:SI 1 \"register_operand\")\n-\t\t\t (match_operand:SI 2 \"rx_source_operand\"))\n-\t\t (const_int 0)))\n-\t (set (match_operand:SI 0 \"register_operand\")\n-\t\t (minus:SI (match_dup 1) (match_dup 2)))])]\n-)\n-\n-(define_insn \"sbb_internal\"\n- [(set (match_operand:SI 0 \"register_operand\" \"=r,r\")\n-\t(minus:SI\n-\t (minus:SI\n-\t (match_operand:SI 1 \"register_operand\" \" 0,0\")\n-\t (match_operand:SI 2 \"rx_compare_operand\" \" r,Q\"))\n-\t (geu:SI (reg:CC CC_REG) (const_int 0))))\n- (clobber (reg:CC CC_REG))]\n- \"reload_completed\"\n- \"sbb\\t%2, %0\"\n- [(set_attr \"timings\" \"11,33\")\n- (set_attr \"length\" \"3,6\")]\n-)\n-\n-(define_insn \"*sbb_flags\"\n- [(set (reg CC_REG)\n-\t(compare\n-\t (minus:SI\n-\t (minus:SI\n-\t (match_operand:SI 1 \"register_operand\" \" 0,0\")\n-\t (match_operand:SI 2 \"rx_compare_operand\" \" r,Q\"))\n-\t (geu:SI (reg:CC CC_REG) (const_int 0)))\n-\t (const_int 0)))\n- (set (match_operand:SI\t0 \"register_operand\" \"=r,r\")\n-\t(minus:SI\n-\t (minus:SI (match_dup 1) (match_dup 2))\n-\t (geu:SI (reg:CC CC_REG) (const_int 0))))]\n- \"reload_completed\"\n- \"sbb\\t%2, %0\"\n- [(set_attr \"timings\" \"11,33\")\n- (set_attr \"length\" \"3,6\")]\n-)\n-\n-(define_expand \"subdi3\"\n- [(set (match_operand:DI 0 \"register_operand\")\n-\t(minus:DI (match_operand:DI 1 \"register_operand\")\n-\t\t (match_operand:DI 2 \"register_operand\")))]\n- \"\"\n-{\n- rtx op0l, op0h, op1l, op1h, op2l, op2h;\n-\n- op0l = gen_lowpart (SImode, operands[0]);\n- op1l = gen_lowpart (SImode, operands[1]);\n- op2l = gen_lowpart (SImode, operands[2]);\n- op0h = gen_highpart (SImode, operands[0]);\n- op1h = gen_highpart (SImode, operands[1]);\n- op2h = gen_highpart_mode (SImode, DImode, operands[2]);\n-\n- emit_insn (gen_subdi3_internal (op0l, op0h, op1l, op2l, op1h, op2h));\n- DONE;\n-})\n-\n-(define_insn_and_split \"subdi3_internal\"\n- [(set (match_operand:SI 0 \"register_operand\" \"=&r,&r\")\n-\t(minus:SI (match_operand:SI 2 \"register_operand\" \" 0, r\")\n-\t\t (match_operand:SI 3 \"rx_compare_operand\" \"rQ, r\")))\n- (set (match_operand:SI 1 \"register_operand\" \"= r, r\")\n-\t(minus:SI\n-\t (minus:SI\n-\t (match_operand:SI 4 \"register_operand\" \" 1, 1\")\n-\t (match_operand:SI 5 \"rx_compare_operand\" \" rQ,rQ\"))\n-\t (gtu:SI (match_dup 3) (match_dup 2))))\n+(define_insn \"subdi3\"\n+ [(set (match_operand:DI 0 \"register_operand\" \"=r,r\")\n+\t(minus:DI (match_operand:DI 1 \"register_operand\" \"0,0\")\n+\t\t (match_operand:DI 2 \"rx_source_operand\" \"r,Q\")))\n (clobber (reg:CC CC_REG))]\n \"\"\n- \"#\"\n- \"reload_completed\"\n- [(const_int 0)]\n-{\n- emit_insn (gen_subsi3_flags (operands[0], operands[2], operands[3]));\n- emit_insn (gen_sbb_internal (operands[1], operands[4], operands[5]));\n- DONE;\n-})\n+ {\n+ return \"sub\\t%L2, %L0\\n\\tsbb\\t%H2, %H0\";\n+ }\n+ [(set_attr \"length\" \"6\")\n+ (set_attr \"timings\" \"22\")]\n+)\n \n (define_insn_and_split \"xorsi3\"\n [(set (match_operand:SI 0 \"register_operand\" \"=r,r,r,r,r,r\")\n@@ -1936,6 +1803,7 @@\n [(set_attr \"timings\" \"33\")\n (set_attr \"length\" \"5\")] ;; This length is corrected in rx_adjust_insn_length\n )\n+\n \f\n ;; Floating Point Instructions\n \n@@ -2870,20 +2738,32 @@\n \"\"\n )\n \n-(define_insn \"movdi\"\n- [(set (match_operand:DI 0 \"nonimmediate_operand\" \"=rm\")\n- (match_operand:DI 1 \"general_operand\" \"rmi\"))]\n- \"TARGET_ENABLE_LRA\"\n- { return rx_gen_move_template (operands, false); }\n- [(set_attr \"length\" \"16\")\n- (set_attr \"timings\" \"22\")]\n+;; RX does not allow addition without destroying CC.\n+;; As an alternative to addptrsi3, we define addsi3, which hides changes to CC.\n+(define_insn_and_split \"*addsi3_lra\"\n+ [(set (match_operand:SI 0 \"register_operand\" \"=&r\")\n+ (plus:SI (match_operand:SI 1 \"register_operand\" \"r\")\n+ (match_operand:SI 2 \"rx_source_operand\" \"ri\")))]\n+ \"lra_in_progress || reload_completed\"\n+ \"#\"\n+ \"&& reload_completed\"\n+ [(parallel [\n+ (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))\n+ (clobber (reg:CC 16))\n+ ])]\n )\n \n-(define_insn \"movdf\"\n- [(set (match_operand:DF 0 \"nonimmediate_operand\" \"=rm\")\n- (match_operand:DF 1 \"general_operand\" \"rmi\"))]\n- \"TARGET_ENABLE_LRA\"\n- { return rx_gen_move_template (operands, false); }\n- [(set_attr \"length\" \"16\")\n- (set_attr \"timings\" \"22\")]\n+(define_insn_and_split \"*ashlsi3_lra\"\n+ [(set (match_operand:SI 0 \"register_operand\" \"=r,r\")\n+ (ashift:SI (match_operand:SI 1 \"register_operand\" \"%0,r\")\n+ (match_operand:SI 2 \"nonmemory_operand\" \"ri,ri\")))]\n+ \"lra_in_progress || reload_completed\"\n+ \"@\n+ shll\\t%2, %0\n+ shll\\t%2, %1, %0\"\n+ \"&& reload_completed\"\n+ [(parallel [\n+ (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))\n+ (clobber (reg:CC CC_REG))\n+ ])]\n )\ndiff --git a/gcc/config/rx/rx.opt b/gcc/config/rx/rx.opt\nindex 5caad487389..0e4c9872356 100644\n--- a/gcc/config/rx/rx.opt\n+++ b/gcc/config/rx/rx.opt\n@@ -128,12 +128,6 @@ Enable the use the standard RX ABI where all stacked function arguments are natu\n \n ;---------------------------------------------------\n \n-mlra\n-Target Mask(ENABLE_LRA)\n-Enable the use of the LRA register allocator.\n-\n-;---------------------------------------------------\n-\n mallow-string-insns\n Target Var(rx_allow_string_insns) Init(1)\n Enables or disables the use of the SMOVF, SMOVB, SMOVU, SUNTIL, SWHILE and RMPA instructions. Enabled by default.\n", "prefixes": [ "RFC", "v2" ] }