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GET /api/patches/2219764/?format=api
{ "id": 2219764, "url": "http://patchwork.ozlabs.org/api/patches/2219764/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260404-t_power_on_fux-v4-3-2891391177f4@oss.qualcomm.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260404-t_power_on_fux-v4-3-2891391177f4@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-04T08:17:20", "name": "[v4,3/3] PCI: qcom: Program T_POWER_ON", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9f049a5227618c2aacd2a98e8c5de5badf89b7ff", "submitter": { "id": 89908, "url": "http://patchwork.ozlabs.org/api/people/89908/?format=api", "name": "Krishna Chaitanya Chundru", "email": "krishna.chundru@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260404-t_power_on_fux-v4-3-2891391177f4@oss.qualcomm.com/mbox/", "series": [ { "id": 498705, "url": "http://patchwork.ozlabs.org/api/series/498705/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=498705", "date": "2026-04-04T08:17:17", "name": "PCI: qcom: Program T_POWER_ON value for L1.2 exit timing", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/498705/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219764/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219764/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51867-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=ffcfS3+B;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=IPRYAPXk;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260404-t_power_on_fux-v4-3-2891391177f4@oss.qualcomm.com>", "References": "<20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com>", "In-Reply-To": "<20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com>", "To": "Manivannan Sadhasivam <mani@kernel.org>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>, Jingoo Han <jingoohan1@gmail.com>", "Cc": "linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com,\n quic_vbadigan@quicinc.com,\n Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>", "X-Mailer": "b4 0.14.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1775290642; l=2508;\n i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id;\n bh=eLlhRSUUKQzMD4xw0eb0Pj6hBFVgOdEaGYz5rmdOD0w=;\n b=FoSqAxwrZC+d2vwgX0vXTnnO4tPPZUWaJ/+SnJjtKhp10P54ksl61uq7Bio4H4ZaPODY184qU\n uXcFi/zk+gtBjD3aKb7GyEFrr9nbEPEMfcr8roD85aBqaFVuZML5aIg", "X-Developer-Key": "i=krishna.chundru@oss.qualcomm.com; a=ed25519;\n pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg=", "X-Authority-Analysis": "v=2.4 cv=ari/yCZV c=1 sm=1 tr=0 ts=69d0c924 cx=c_pps\n a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22\n a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=wXczfBY3881IDOTkNB0A:9 a=QEXdDO2ut3YA:10\n a=3WC7DwWrALyhR5TkjVHa:22", "X-Proofpoint-ORIG-GUID": "UqZnf952IXLo4HqTNgr7X3J7zrYbW2Cz", "X-Proofpoint-GUID": "UqZnf952IXLo4HqTNgr7X3J7zrYbW2Cz", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDA0MDA3MiBTYWx0ZWRfXynaIHlhzdAKe\n 8fenJAZYeI1fy8B5EV5s1V8W9h4+7fHKAoCEC86zk8eXbWraLri9witK8NQ3/Za7czL34Y6siGf\n vhd/0kSSmzGVWm1z7o1s29TzaPsgpP0HxJjAmz2/UhCdJXPbTk1edgH0n5/QA3C2p5bTi7yGNTM\n fuwxzPkT1pd4TE/Esuf74aK1hrFMJc89Y2mv44uTxrTfibILUId0ofiAFmXuSvHpltdfi06BdmF\n KbG9KRaOmWuhwmedbGjhmOuzOO9bzD/VyqTxlY4oolThLAf228iLp/ox96pCzTQz/4Vk0q2r/oo\n qMSi47QQ7ZoYxFQx77huy10e/fFWaBUpCD2xTZDWJZobCiqQsXYu54cqKaIjD9+FZE1BacicYPI\n AkANNPxMjRSNnmDcnoXm5Cbo1PJpOGg0B+6QmCGZcgWulCL6lnv+m+5ci5aF10kAJNprg5k+2KB\n k2+pEYbpmJj7xbxVXFg==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-03_07,2026-04-03_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n impostorscore=0 suspectscore=0 clxscore=1015 malwarescore=0 phishscore=0\n lowpriorityscore=0 bulkscore=0 priorityscore=1501 spamscore=0 adultscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604040072" }, "content": "Some platforms have incorrect T_POWER_ON value programmed in hardware.\nGenerally these will be corrected by bootloaders, but not all targets\nsupport bootloaders to program correct values due to that\nLTR_L1.2_THRESHOLD value calculated by aspm driver can be wrong, which\ncan result in improper L1.2 exit behavior and if AER happens to be\nsupported and enabled, the error may be *reported* via AER.\n\nParse \"t-power-on-us\" property from each root port node and program them\nas part of host initialization using dw_pcie_program_t_power_on() before\nlink training.\n\nThis property in added to the dtschema here[1].\n\nSigned-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>\nLink[1]: https://lore.kernel.org/all/20260205093346.667898-1-krishna.chundru@oss.qualcomm.com/\n---\n drivers/pci/controller/dwc/pcie-qcom.c | 14 ++++++++++++++\n 1 file changed, 14 insertions(+)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c\nindex 67a16af69ddc75fca1b123e70715e692a91a9135..a8f82f860c08fe2eabad2c0eed541b8dd121215e 100644\n--- a/drivers/pci/controller/dwc/pcie-qcom.c\n+++ b/drivers/pci/controller/dwc/pcie-qcom.c\n@@ -269,6 +269,7 @@ struct qcom_pcie_perst {\n struct qcom_pcie_port {\n \tstruct list_head list;\n \tstruct phy *phy;\n+\tu32 l1ss_t_power_on;\n \tstruct list_head perst;\n };\n \n@@ -1283,6 +1284,14 @@ static int qcom_pcie_phy_power_on(struct qcom_pcie *pcie)\n \treturn 0;\n }\n \n+static void qcom_pcie_configure_ports(struct qcom_pcie *pcie)\n+{\n+\tstruct qcom_pcie_port *port;\n+\n+\tlist_for_each_entry(port, &pcie->ports, list)\n+\t\tdw_pcie_program_t_power_on(pcie->pci, port->l1ss_t_power_on);\n+}\n+\n static int qcom_pcie_host_init(struct dw_pcie_rp *pp)\n {\n \tstruct dw_pcie *pci = to_dw_pcie_from_pp(pp);\n@@ -1317,6 +1326,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)\n \tdw_pcie_remove_capability(pcie->pci, PCI_CAP_ID_MSIX);\n \tdw_pcie_remove_ext_capability(pcie->pci, PCI_EXT_CAP_ID_DPC);\n \n+\tqcom_pcie_configure_ports(pcie);\n+\n \tqcom_pcie_perst_deassert(pcie);\n \n \tif (pcie->cfg->ops->config_sid) {\n@@ -1759,6 +1770,9 @@ static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node *node\n \tif (ret)\n \t\treturn ret;\n \n+\t/* TODO: Need to move to dwc once multi root port support is added. */\n+\tof_property_read_u32(node, \"t-power-on-us\", &port->l1ss_t_power_on);\n+\n \tport->phy = phy;\n \tINIT_LIST_HEAD(&port->list);\n \tlist_add_tail(&port->list, &pcie->ports);\n", "prefixes": [ "v4", "3/3" ] }