Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2219763/?format=api
{ "id": 2219763, "url": "http://patchwork.ozlabs.org/api/patches/2219763/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260404-t_power_on_fux-v4-2-2891391177f4@oss.qualcomm.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260404-t_power_on_fux-v4-2-2891391177f4@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-04T08:17:19", "name": "[v4,2/3] PCI: dwc: Add helper to Program T_POWER_ON", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "664abdaf4a55342f9ce55e1df3608e920d8c8e1e", "submitter": { "id": 89908, "url": "http://patchwork.ozlabs.org/api/people/89908/?format=api", "name": "Krishna Chaitanya Chundru", "email": "krishna.chundru@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260404-t_power_on_fux-v4-2-2891391177f4@oss.qualcomm.com/mbox/", "series": [ { "id": 498705, "url": "http://patchwork.ozlabs.org/api/series/498705/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=498705", "date": "2026-04-04T08:17:17", "name": "PCI: qcom: Program T_POWER_ON value for L1.2 exit timing", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/498705/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219763/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219763/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51866-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=TxAyVwWp;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=WTWWCWGw;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-51866-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"TxAyVwWp\";\n\tdkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"WTWWCWGw\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=205.220.180.131", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=oss.qualcomm.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fnpRj3hpwz1yCs\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 04 Apr 2026 19:20:01 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id C4C0B30524FF\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 4 Apr 2026 08:17:38 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 76C743A543C;\n\tSat, 4 Apr 2026 08:17:38 +0000 (UTC)", "from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 18D1537647B\n\tfor <linux-pci@vger.kernel.org>; Sat, 4 Apr 2026 08:17:36 +0000 (UTC)", "from pps.filterd (m0279869.ppops.net [127.0.0.1])\n\tby mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 6342Bfpm4113344\n\tfor <linux-pci@vger.kernel.org>; Sat, 4 Apr 2026 08:17:36 GMT", "from mail-pj1-f69.google.com (mail-pj1-f69.google.com\n [209.85.216.69])\n\tby mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dasn5rk5m-1\n\t(version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n\tfor <linux-pci@vger.kernel.org>; Sat, 04 Apr 2026 08:17:35 +0000 (GMT)", "by mail-pj1-f69.google.com with SMTP id\n 98e67ed59e1d1-3595485abbbso2930079a91.2\n for <linux-pci@vger.kernel.org>; Sat, 04 Apr 2026 01:17:35 -0700 (PDT)", "from hu-krichai-hyd.qualcomm.com ([202.46.23.25])\n by smtp.gmail.com with ESMTPSA id\n 41be03b00d2f7-c76c657dfb7sm6786408a12.24.2026.04.04.01.17.30\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Sat, 04 Apr 2026 01:17:34 -0700 (PDT)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775290658; cv=none;\n b=cVzSG6V5IoqFt5mbR73lSFUag6IaFh+y5Ghf8Ew+pc3FY5bbYlabsGqwkxQDS2suORvhlQu2fhGZ5V6Rj/uRf5SNB2AlJOFbocwfZ60HUzQ7/Fah+GFNkBkau4XuEjvW6bXtCJEMr9BKIGgkDinR7OSruCTAcQ4T0d/Xskm3r+Q=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775290658; c=relaxed/simple;\n\tbh=WxyWJaM1nRlxUT9s9i7G0JqWO3oDpGfwYpYNm18PeQs=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=DYitFAXnHsMqflxMoRItu2eDtb9MA+jqphCOXqquqkEy3BvnTG02+DUSUurckuT8GHzd2R26lli6LtYas/SSrn3+6gqLbNORZNEk54hnnsKf7f3BOWo1/feZ8oT/1ge+98v7B386wyUAe+xKJ7JH4K7BxSy2JjPyy911/7S1KkE=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com;\n spf=pass smtp.mailfrom=oss.qualcomm.com;\n dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=TxAyVwWp;\n dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=WTWWCWGw; arc=none smtp.client-ip=205.220.180.131", "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n\tcc:content-transfer-encoding:content-type:date:from:in-reply-to\n\t:message-id:mime-version:references:subject:to; s=qcppdkim1; bh=\n\tQ5wgiGfuhLOG5aXzit2OLL975WIbQOoDmxtVx7USbCY=; b=TxAyVwWpGZC6atFF\n\t7mNBXXNI9dNq6tLgkqx0mhJdBmpsA/WT0pHJj6Ebe5BGjlfljqrtSJDJ8Gmil/HB\n\tOml+ha8Rj3hErZ2O85+1XBfXpoUbsw0QZXWIoAx9gPIZiBSGw5we6XyApLIZjGvB\n\tlePqkl2T9/qUlMVQKR0BW8zfJGhiajl7DSScJBpsAIdSJ8eHRezVrd5wMuQTfrDS\n\tTgplnGlKUu9dzKMmHQUhdyLSe9hZiF4DPzzgHasXYTTA7+ohXtPDzWYV8WG2XZMU\n\tyC7dkpxP4IimngsWwcSQu98grCT9fU0Gcgr2P9ELk3V+wzXq7IjjqpyCOh9O0tWD\n\tEGMoqA==", "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=oss.qualcomm.com; s=google; t=1775290655; x=1775895455;\n darn=vger.kernel.org;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:from:to:cc:subject:date:message-id\n :reply-to;\n bh=Q5wgiGfuhLOG5aXzit2OLL975WIbQOoDmxtVx7USbCY=;\n b=WTWWCWGwe5KXXvyNcEEEPScGt1ctpojAsiDT8r04t9MKQMhwHVioEItjNFkS00CjfB\n cX/2mJl+bNCKyLltstXoWWV+b4Cne3a93BUlj8U3V5ymoDpSS7QB38Lf3jAFLYc7UZp5\n te9jRX5diF4sl23HNZDLz1ZSh50/sah8CQDWeuDENwPrekYJcbP5xxVHbUkxjc3/7Dis\n YuXzb5XuE+GcntYyD30kjQQ0W9zOJ+RcfA6DVdnTYh01Dm9BD3AksXbXKU20BUH4MX8C\n cv2txca3mVQ8uM3tMGtCSBmUXRQMSXVpnnaDrIe+HUHjZbPpfMhvKSFLJj3yAtpcRJhy\n opeQ==" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775290655; x=1775895455;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=Q5wgiGfuhLOG5aXzit2OLL975WIbQOoDmxtVx7USbCY=;\n b=Oqu7Yc5rBGHOnwmTKzGQNBU6JesJeEpdHsA+ADkavG3qfeFIs0PqRMmzs54AY05WXc\n +ymAprfwrKtNKhkw8L57ZlhPPKvBdeqLxlPApex8bmDAs0u/DjViuFCEBlsrxHmuVCmS\n ruG1gGKoX61HHNItHld05XguOQpPV4SQa72eFRBZe0UBJ3i7eYwPU75xiAwEVhF71x3X\n nKMxDGMQ3WJdBd8Swikxi+VGBGHWxcpNKo5bdVJVIsLNgbNOaFQZNO2N7WIwCH/Y7nBc\n Xzkw+0FiLMZJWs5xnd9rZcicRmfoRsb1X2nZk8s0BN774tqdD+ODG8FXZ9LVddxgoh1k\n VvHg==", "X-Gm-Message-State": "AOJu0Ywx+p+RgbVZGIh8A2X5mGvxDttwqPKATUrBEdn64WO6WSMDaWAS\n\tgIRq/K6pBnfzhdgazaZpxC2DH0yr+gT5bSs7qzN6WDFDZ7AC94rkHSzeSwtyQRVqg19aC47nTr7\n\tE2NUNh/NVHDQd+HmD2O63ZyAozBEEFwJF5RkHapjgdBDqrFPKHrJ4HsWqMTVam5I=", "X-Gm-Gg": "AeBDiev5wHh8O1RmbTXe3WyxcCE5LCwxYTpDkgL3dVlc1DFzk3ccJWRpsvdhGtwrXj0\n\tntexa5RFqFG3reNk69DrmCJlnWVFVTfggfh409uWb7Iqj2i1AkZoNDeIt10ZBvkeDWhBES7xgHh\n\tdX+AdSNRhtogKUDBI2e3glKnHqbWTxctKEk6jO9kvbwKP7XXuoILFKDiU6MttPG6HD0tfu178pI\n\tjwW8DZeop3aXeQPnckXNI6lKZaVcAfN819/kcHpifl1E6rPf5T6E3h+FxuDc2E5h2odRg9rdsIn\n\tMED8VxzWfaf0BLb71b91TpcPcQnEWZUcFz77SdZ4xntSfiBkOGDcIr9I7G0GnfRtbJJaiy4Zf26\n\tzXZSphIYaJL73N2wTKbabqlfqPePtcn/mRfhkWV/s0rnx6lyjAD89QAhw", "X-Received": [ "by 2002:a05:6300:6d8b:20b0:39f:57b1:ede2 with SMTP id\n adf61e73a8af0-39f57b26e77mr421900637.37.1775290655021;\n Sat, 04 Apr 2026 01:17:35 -0700 (PDT)", "by 2002:a05:6300:6d8b:20b0:39f:57b1:ede2 with SMTP id\n adf61e73a8af0-39f57b26e77mr421879637.37.1775290654535;\n Sat, 04 Apr 2026 01:17:34 -0700 (PDT)" ], "From": "Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>", "Date": "Sat, 04 Apr 2026 13:47:19 +0530", "Subject": "[PATCH v4 2/3] PCI: dwc: Add helper to Program T_POWER_ON", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "Message-Id": "<20260404-t_power_on_fux-v4-2-2891391177f4@oss.qualcomm.com>", "References": "<20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com>", "In-Reply-To": "<20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com>", "To": "Manivannan Sadhasivam <mani@kernel.org>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>, Jingoo Han <jingoohan1@gmail.com>", "Cc": "linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com,\n quic_vbadigan@quicinc.com,\n Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>,\n Shawn Lin <shawn.lin@rock-chips.com>", "X-Mailer": "b4 0.14.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1775290642; l=3029;\n i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id;\n bh=WxyWJaM1nRlxUT9s9i7G0JqWO3oDpGfwYpYNm18PeQs=;\n b=NZPGIsL8x+PRfP7EAG/l0EzDeAARbiXQ3V/gQXfIIL33gW1mnESBNlL3uw3M8FpAVsO24W8Pk\n T5xV5lrUbFXDwQg/VXK9GyrUP3wLjqhT4w5LHBHuUSW5BYJGO0SWOtt", "X-Developer-Key": "i=krishna.chundru@oss.qualcomm.com; a=ed25519;\n pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg=", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDA0MDA3MiBTYWx0ZWRfXz0CGp04hW3jn\n 48CkKOLF5yht4nK2q7EGRoxTT3UZANuCLHm1N9dhhC0nKZuY0v0+Edgf1yy7LuvVRe+B0HiTEnm\n WP/GQepJLVlutHoThQQrTZiYE2BdFld0P8RRwkngZSjAri2hZKzC+5xyuxXN3PsiGlMggwgL601\n ACjyOocvikaU3OW8OspzjUqLf0EWk2tJXEeC/Hz4+lXOXVMuGzFV0oQtWsPktFXvTVSqRG7Yixr\n pWaB9gX64XOu8FCDUJuPJGAuBgMVCKRpkv/wp6duVaXYVq2tNitpVS8jju2T3AK1mZOlAN1j7QK\n 0Xlar8H/WvRfXnObcdiMclkrPnzS4ktvFuI2UOSPl91POnxY4GX/co6EdDvSxSEV4T2U5cioGCy\n iq2A+7/oQ6ykFq/G5r2ZXlKIb2gV9ohr5f9t/UaEuM7Miwlsvp+G7JqKvd2OS183yoAX/TkzNhS\n Dm0ChfM3uWLrgNYC+Pw==", "X-Proofpoint-ORIG-GUID": "RMgpkSD7ntWMi-it7r75blt6gCoQO2Ih", "X-Authority-Analysis": "v=2.4 cv=K9wv3iWI c=1 sm=1 tr=0 ts=69d0c920 cx=c_pps\n a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22\n a=s8YR1HE3AAAA:8 a=EUspDBNiAAAA:8 a=kXhGf0cxdCgfIYue-YsA:9 a=3ZKOabzyN94A:10\n a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=jGH_LyMDp9YhSvY-UuyI:22", "X-Proofpoint-GUID": "RMgpkSD7ntWMi-it7r75blt6gCoQO2Ih", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-03_07,2026-04-03_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0 clxscore=1015\n lowpriorityscore=0 impostorscore=0 adultscore=0 phishscore=0 spamscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604040072" }, "content": "The T_POWER_ON indicates the time (in μs) that a Port requires the port\non the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ#\nasserted before actively driving the interface. This value is used by\nthe ASPM driver to compute the LTR_L1.2_THRESHOLD.\n\nCurrently, some controllers exposes T_POWER_ON value of zero in the L1SS\ncapability registers, leading to incorrect LTR_L1.2_THRESHOLD calculations,\nwhich can result in improper L1.2 exit behavior and if AER happens to be\nsupported and enabled, the error may be *reported* via AER.\n\nAdd a helper to override T_POWER_ON value by the DWC controller drivers.\n\nTested-by: Shawn Lin <shawn.lin@rock-chips.com>\nReviewed-by: Shawn Lin <shawn.lin@rock-chips.com>\nSigned-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>\n---\n drivers/pci/controller/dwc/pcie-designware.c | 28 ++++++++++++++++++++++++++++\n drivers/pci/controller/dwc/pcie-designware.h | 1 +\n 2 files changed, 29 insertions(+)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c\nindex 5741c09dde7f40487c6da6dfd66f7c8d96a74259..6289329ef2b2a4ac9264d1c6cb5ea4e88c261634 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.c\n+++ b/drivers/pci/controller/dwc/pcie-designware.c\n@@ -1249,6 +1249,34 @@ void dw_pcie_hide_unsupported_l1ss(struct dw_pcie *pci)\n \tdw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, l1ss_cap);\n }\n \n+/* TODO: Need to handle multi root ports */\n+void dw_pcie_program_t_power_on(struct dw_pcie *pci, u16 t_power_on)\n+{\n+\tu8 scale, value;\n+\tu16 offset;\n+\tu32 val;\n+\n+\tif (!t_power_on)\n+\t\treturn;\n+\n+\toffset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS);\n+\tif (!offset)\n+\t\treturn;\n+\n+\tpcie_encode_t_power_on(t_power_on, &scale, &value);\n+\n+\tdw_pcie_dbi_ro_wr_en(pci);\n+\n+\tval = readl(pci->dbi_base + offset + PCI_L1SS_CAP);\n+\tval &= ~(PCI_L1SS_CAP_P_PWR_ON_SCALE | PCI_L1SS_CAP_P_PWR_ON_VALUE);\n+\tFIELD_MODIFY(PCI_L1SS_CAP_P_PWR_ON_SCALE, &val, scale);\n+\tFIELD_MODIFY(PCI_L1SS_CAP_P_PWR_ON_VALUE, &val, value);\n+\n+\twritel(val, pci->dbi_base + offset + PCI_L1SS_CAP);\n+\n+\tdw_pcie_dbi_ro_wr_dis(pci);\n+}\n+\n void dw_pcie_setup(struct dw_pcie *pci)\n {\n \tu32 val;\ndiff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h\nindex ae6389dd9caa5c27690f998d58729130ea863984..da67beece3f11e33d9a1937fa23d443feea3bbc7 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.h\n+++ b/drivers/pci/controller/dwc/pcie-designware.h\n@@ -602,6 +602,7 @@ int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,\n \t\t\t\tu8 bar, size_t size);\n void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index);\n void dw_pcie_hide_unsupported_l1ss(struct dw_pcie *pci);\n+void dw_pcie_program_t_power_on(struct dw_pcie *pci, u16 t_power_on);\n void dw_pcie_setup(struct dw_pcie *pci);\n void dw_pcie_iatu_detect(struct dw_pcie *pci);\n int dw_pcie_edma_detect(struct dw_pcie *pci);\n", "prefixes": [ "v4", "2/3" ] }