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GET /api/patches/2219664/?format=api
{ "id": 2219664, "url": "http://patchwork.ozlabs.org/api/patches/2219664/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260403162541.86608-2-sgdfkk@163.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260403162541.86608-2-sgdfkk@163.com>", "list_archive_url": null, "date": "2026-04-03T16:25:35", "name": "[v7,1/7] mips: loongson: minimal initial SoC support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9b8564b0e07edc596ee10dcd03c7ce9b227994a8", "submitter": { "id": 92844, "url": "http://patchwork.ozlabs.org/api/people/92844/?format=api", "name": null, "email": "sgdfkk@163.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260403162541.86608-2-sgdfkk@163.com/mbox/", "series": [ { "id": 498655, "url": "http://patchwork.ozlabs.org/api/series/498655/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=498655", "date": "2026-04-03T16:25:35", "name": "add loongson mips ls1c300 initial support", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/498655/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219664/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219664/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=163.com header.i=@163.com header.a=rsa-sha256\n header.s=s110527 header.b=XmTNkvSd;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=163.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=163.com header.i=@163.com header.b=\"XmTNkvSd\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=163.com", "phobos.denx.de; spf=pass smtp.mailfrom=sgdfkk@163.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fnPGt3H8sz1xtJ\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 04 Apr 2026 03:25:58 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 216FD84132;\n\tFri, 3 Apr 2026 18:25:55 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id B6BBF84132; Fri, 3 Apr 2026 18:25:53 +0200 (CEST)", "from m16.mail.163.com (m16.mail.163.com [117.135.210.4])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id B9DDA840B0\n for <u-boot@lists.denx.de>; Fri, 3 Apr 2026 18:25:50 +0200 (CEST)", "from server-e.. (unknown [])\n by gzsmtp3 (Coremail) with SMTP id PigvCgAnAXQF6s9pHqSgBw--.137S3;\n Sat, 04 Apr 2026 00:25:47 +0800 (CST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,HK_RANDOM_ENVFROM,\n HK_RANDOM_FROM,RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED,\n SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY autolearn=no\n autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com;\n s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=Rp\n yn8PBhTf1qk9kQuaTJUZ1o34AZtqWYkEXHWDyQfCA=; b=XmTNkvSdNWEi44qgou\n Skn0zeWQbleeErZHdOqzDTJQxsSArRHUBSBYANtRSj5aP9f+a4RH1BfFN1p1B7dA\n w0ZUdiBjR9iukyaww/dCxNrvdIMevYa9lhqtVMSdUng/A/MCgVeg3kTul8bcPSJf\n lgo/puc0mZm3dPKAq4gwfKJnA=", "From": "sgdfkk@163.com", "To": "u-boot@lists.denx.de", "Cc": "Du Huanpeng <u74147@gmail.com>", "Subject": "[PATCH v7 1/7] mips: loongson: minimal initial SoC support", "Date": "Sat, 4 Apr 2026 00:25:35 +0800", "Message-ID": "<20260403162541.86608-2-sgdfkk@163.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260403162541.86608-1-sgdfkk@163.com>", "References": "<20260403162541.86608-1-sgdfkk@163.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "PigvCgAnAXQF6s9pHqSgBw--.137S3", "X-Coremail-Antispam": "1Uf129KBjvJXoWxKryDCw1fZFWrur43CryrCrg_yoWDGrW5pa\n n0ka1rGrs7Zr47Jr93A34UWrs3Aan5GFW2vF43tFy8Aa97Z3WDXFs3tFnxtrW7JFWDJayr\n WryrWFW7KF4qvw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07U8nYwUUUUU=", "X-Originating-IP": "[240e:3b0:4805:581::3001]", "X-CM-SenderInfo": "xvjgwyrn6rljoofrz/xtbC6AsLYmnP6gu4-AAA3J", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Du Huanpeng <u74147@gmail.com>\n\nLoongson 1C is a cost-effective SOC chip for industrial control and\nthe Internet of Things. The Loongson 1C includes a floating-point\nprocessing unit, supports multiple types of memory, and supports\nhigh-capacity MLC NAND Flash. Loongson 1C provides developers with a\nwealth of peripheral interfaces and on-chip modules, including Camera\ncontroller, USB OTG and USB HOST interfaces, AC97/I2S controller, LCD\ncontroller, SPI interface, UART interface, etc., providing sufficient\ncomputing power and multi-application connectivity.\n\nSome highlights of this SoC are:\n- Single core LS232, MIPS32 instruction set compatible, main frequency\n300MHZ\n- 16KB data cache and 16KB instruction cache\n- 64 bit float unit, hardware division\n- 8/16 bit SDRAM controller, 45 ~ 133MHz\n- 8/16 bit SRAM, NAND\n- I2S/AC97, LCD, MAC, USB, OTG, SPI, I2C, PWM, CAN, SDIO, ADC\n- 12 UARTs\n\nLinks:\nhttps://www.loongson.cn/\n\nintroduce base support for the ls1c300 SoC.\n- debug UART2\n- serial console\n- clock\n- watchdog\n- sysreset\n- uart\n\nSigned-off-by: Du Huanpeng <u74147@gmail.com>\n---\n MAINTAINERS | 9 ++++\n arch/mips/Kconfig | 11 ++++\n arch/mips/Makefile | 1 +\n arch/mips/mach-loongson/Kconfig | 69 ++++++++++++++++++++++++\n arch/mips/mach-loongson/Makefile | 6 +++\n arch/mips/mach-loongson/cpu.c | 19 +++++++\n arch/mips/mach-loongson/ls1c300/Makefile | 7 +++\n arch/mips/mach-loongson/ls1c300/init.c | 61 +++++++++++++++++++++\n arch/mips/mach-loongson/spl.c | 46 ++++++++++++++++\n 9 files changed, 229 insertions(+)\n create mode 100644 arch/mips/mach-loongson/Kconfig\n create mode 100644 arch/mips/mach-loongson/Makefile\n create mode 100644 arch/mips/mach-loongson/cpu.c\n create mode 100644 arch/mips/mach-loongson/ls1c300/Makefile\n create mode 100644 arch/mips/mach-loongson/ls1c300/init.c\n create mode 100644 arch/mips/mach-loongson/spl.c", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex d4b527560aa..11d56d9795d 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1379,6 +1379,15 @@ F:\tdrivers/net/cortina_ni.c\n F:\tdrivers/net/cortina_ni.h\n F:\tdrivers/net/phy/ca_phy.c\n \n+MIPS LOONGSON LS1C300\n+M:\tDu Huanpeng <u74147@gmail.com>\n+S:\tMaintained\n+F:\tarch/mips/dts/loongson32-ls1c300b.dtsi\n+F:\tarch/mips/mach-loongson/\n+F:\tdrivers/clk/loongson/\n+F:\tdrivers/watchdog/loongson_wdt.c\n+F:\tinclude/dt-bindings/clock/ls1c300-clk.h\n+\n MIPS MEDIATEK\n M:\tWeijie Gao <weijie.gao@mediatek.com>\n R:\tGSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>\ndiff --git a/arch/mips/Kconfig b/arch/mips/Kconfig\nindex 36612756294..0e3fc9ceeb5 100644\n--- a/arch/mips/Kconfig\n+++ b/arch/mips/Kconfig\n@@ -88,6 +88,16 @@ config ARCH_MTMIPS\n \tselect SUPPORT_LITTLE_ENDIAN\n \tselect SUPPORT_SPL\n \n+config ARCH_LSMIPS\n+\tbool \"Support Loongson MIPS platforms\"\n+\tselect DM\n+\tselect DM_SERIAL\n+\tselect OF_CONTROL\n+\tselect SUPPORTS_CPU_MIPS32_R1\n+\tselect SUPPORTS_CPU_MIPS32_R2\n+\tselect SUPPORTS_LITTLE_ENDIAN\n+\tselect SUPPORT_SPL\n+\n config ARCH_JZ47XX\n \tbool \"Support Ingenic JZ47xx\"\n \tselect SUPPORT_SPL\n@@ -202,6 +212,7 @@ source \"arch/mips/mach-bmips/Kconfig\"\n source \"arch/mips/mach-jz47xx/Kconfig\"\n source \"arch/mips/mach-pic32/Kconfig\"\n source \"arch/mips/mach-mtmips/Kconfig\"\n+source \"arch/mips/mach-loongson/Kconfig\"\n source \"arch/mips/mach-octeon/Kconfig\"\n \n if MIPS\ndiff --git a/arch/mips/Makefile b/arch/mips/Makefile\nindex 453c7885075..72b800c755b 100644\n--- a/arch/mips/Makefile\n+++ b/arch/mips/Makefile\n@@ -19,6 +19,7 @@ machine-$(CONFIG_ARCH_BMIPS) += bmips\n machine-$(CONFIG_ARCH_JZ47XX) += jz47xx\n machine-$(CONFIG_MACH_PIC32) += pic32\n machine-$(CONFIG_ARCH_MTMIPS) += mtmips\n+machine-$(CONFIG_ARCH_LSMIPS) += loongson\n machine-$(CONFIG_ARCH_MSCC) += mscc\n machine-${CONFIG_ARCH_OCTEON} += octeon\n \ndiff --git a/arch/mips/mach-loongson/Kconfig b/arch/mips/mach-loongson/Kconfig\nnew file mode 100644\nindex 00000000000..57d22927270\n--- /dev/null\n+++ b/arch/mips/mach-loongson/Kconfig\n@@ -0,0 +1,69 @@\n+menu \"Loongson MIPS platforms\"\n+\tdepends on ARCH_LSMIPS\n+\n+config SYS_MALLOC_F_LEN\n+\tdefault 0x1000\n+\n+config SYS_SOC\n+\tdefault \"ls1c300\" if SOC_LS1C300\n+\n+config SYS_DCACHE_SIZE\n+\tdefault 16384\n+\n+config SYS_DCACHE_LINE_SIZE\n+\tdefault 32\n+\n+config SYS_ICACHE_SIZE\n+\tdefault 16384\n+\n+config SYS_ICACHE_LINE_SIZE\n+\tdefault 32\n+\n+config SPL_PAYLOAD\n+\tdefault \"u-boot-lzma.img\" if SPL_LZMA\n+\n+config BUILD_TARGET\n+\tdefault \"u-boot-with-spl.bin\" if SPL\n+\tdefault \"u-boot.bin\" if !SPL\n+\n+choice\n+\tprompt \"Loongson MIPS SoC select\"\n+\n+config SOC_LS1C300\n+\tbool \"LS1C300\"\n+\tselect CLK_CCF\n+\tselect SPL_SEPARATE_BSS if SPL\n+\tselect SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL\n+\tselect SPL_LOADER_SUPPORT if SPL\n+\tselect SPL_OF_CONTROL if SPL_DM\n+\tselect SPL_SIMPLE_BUS if SPL_DM\n+\tselect SPL_DM_SERIAL if SPL_DM\n+\tselect SPL_CLK if SPL_DM && SPL_SERIAL\n+\tselect SPL_SYSRESET if SPL_DM\n+\tselect SPL_OF_LIBFDT if SPL_OF_CONTROL\n+\thelp\n+\t This supports Loongson LS1C300\n+\n+endchoice\n+\n+choice\n+\tprompt \"Board select\"\n+\n+config BOARD_LS1C300\n+\tbool \"Loongson LS1C300 Eval\"\n+\tdepends on SOC_LS1C300\n+\thelp\n+\t ls1c300-eval board has a LS1C300 SoC with 64MiB of SDRAM\n+\t and 512KiB of flash (SPI NOR) and additional NAND storage.\n+\n+endchoice\n+\n+config CONS_PIN\n+\tint \"pin group used in uart\"\n+\tdefault 0\n+\thelp\n+\t Select pin group connected to UART for your board.\n+\n+source \"board/loongson/ls1c300-eval/Kconfig\"\n+\n+endmenu\ndiff --git a/arch/mips/mach-loongson/Makefile b/arch/mips/mach-loongson/Makefile\nnew file mode 100644\nindex 00000000000..654143a5f70\n--- /dev/null\n+++ b/arch/mips/mach-loongson/Makefile\n@@ -0,0 +1,6 @@\n+# SPDX-License-Identifier: GPL-2.0+\n+\n+obj-y += cpu.o\n+obj-$(CONFIG_SPL_BUILD) += spl.o\n+\n+obj-$(CONFIG_SOC_LS1C300) += ls1c300/\ndiff --git a/arch/mips/mach-loongson/cpu.c b/arch/mips/mach-loongson/cpu.c\nnew file mode 100644\nindex 00000000000..249fdcbdc5f\n--- /dev/null\n+++ b/arch/mips/mach-loongson/cpu.c\n@@ -0,0 +1,19 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>\n+ * Copyright (C) 2022-2026 Du Huanpeng <u74147@gmail.com>\n+ */\n+\n+#include <init.h>\n+#include <malloc.h>\n+#include <linux/bitops.h>\n+#include <linux/io.h>\n+#include <linux/sizes.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+int dram_init(void)\n+{\n+\tgd->ram_size = get_ram_size((void *)KSEG1, SZ_256M) - CONFIG_TEXT_BASE % SZ_256M;\n+\treturn 0;\n+}\ndiff --git a/arch/mips/mach-loongson/ls1c300/Makefile b/arch/mips/mach-loongson/ls1c300/Makefile\nnew file mode 100644\nindex 00000000000..17b9d6fb9ca\n--- /dev/null\n+++ b/arch/mips/mach-loongson/ls1c300/Makefile\n@@ -0,0 +1,7 @@\n+# SPDX-License-Identifier: GPL-2.0\n+\n+obj-y += lowlevel_init.o\n+obj-y += sdram.o\n+obj-y += init.o\n+obj-y += gpio.o\n+obj-$(CONFIG_SPL_BUILD) += serial.o\ndiff --git a/arch/mips/mach-loongson/ls1c300/init.c b/arch/mips/mach-loongson/ls1c300/init.c\nnew file mode 100644\nindex 00000000000..aea0a863e3e\n--- /dev/null\n+++ b/arch/mips/mach-loongson/ls1c300/init.c\n@@ -0,0 +1,61 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2020 MediaTek Inc.\n+ *\n+ * Author: Gao Weijie <weijie.gao@mediatek.com>\n+ *\n+ * based on: arch/mips/mach-mtmips/mt7628/init.c\n+ * Copyright (C) 2020-2026 Du Huanpeng <u74147@gmail.com>\n+ */\n+\n+#include <clk.h>\n+#include <dm.h>\n+#include <dm/uclass.h>\n+#include <dt-bindings/clock/ls1c300-clk.h>\n+#include <linux/io.h>\n+#include <linux/sizes.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+int print_cpuinfo(void)\n+{\n+\tstruct udevice *udev;\n+\tstruct clk clk;\n+\tint ret;\n+\tulong xtal;\n+\tchar buf[SZ_32];\n+\n+\tprintf(\"CPU: Loongson ls1c300b\\n\");\n+\n+\tret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(ls1c300_clk), &udev);\n+\tif (ret) {\n+\t\tprintf(\"error: clock driver not found.\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\tclk.dev = udev;\n+\n+\tret = clk_request(udev, &clk);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tclk.id = CLK_XTAL;\n+\txtal = clk_get_rate(&clk);\n+\n+\tclk.id = CLK_CPU_THROT;\n+\tgd->cpu_clk = clk_get_rate(&clk);\n+\n+\tclk.id = CLK_APB;\n+\tgd->mem_clk = clk_get_rate(&clk);\n+\n+\tprintf(\"Clock: CPU: %sMHz, \", strmhz(buf, gd->cpu_clk));\n+\tprintf(\"SDRAM: %sMHz, \", strmhz(buf, gd->mem_clk));\n+\tprintf(\"XTAL: %sMHz\\n\", strmhz(buf, xtal));\n+\n+\treturn 0;\n+}\n+\n+ulong notrace get_tbclk(void)\n+{\n+\treturn gd->cpu_clk / 2;\n+}\ndiff --git a/arch/mips/mach-loongson/spl.c b/arch/mips/mach-loongson/spl.c\nnew file mode 100644\nindex 00000000000..40454d2cbc9\n--- /dev/null\n+++ b/arch/mips/mach-loongson/spl.c\n@@ -0,0 +1,46 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.\n+ *\n+ * Author: Gao Weijie <weijie.gao@mediatek.com>\n+ *\n+ * Copyright (C) 2022-2026 Du Huanpeng <u74147@gmail.com>\n+ */\n+\n+#include <init.h>\n+#include <spl.h>\n+#include <asm/sections.h>\n+#include <linux/libfdt.h>\n+#include <linux/sizes.h>\n+#include <mach/serial.h>\n+\n+void __noreturn board_init_f(ulong dummy)\n+{\n+\tspl_init();\n+\n+#ifdef CONFIG_SPL_SERIAL\n+\t/*\n+\t * loongson_spl_serial_init() is useful if debug uart is enabled,\n+\t * or DM based serial is not enabled.\n+\t */\n+\tloongson_spl_serial_init();\n+\tpreloader_console_init();\n+#endif\n+\n+\tboard_init_r(NULL, 0);\n+}\n+\n+void board_boot_order(u32 *spl_boot_list)\n+{\n+\tspl_boot_list[0] = BOOT_DEVICE_NOR;\n+}\n+\n+unsigned long spl_nor_get_uboot_base(void)\n+{\n+\tvoid *uboot_base = __image_copy_end;\n+\n+\tif (fdt_magic(uboot_base) == FDT_MAGIC)\n+\t\treturn (unsigned long)uboot_base + fdt_totalsize(uboot_base);\n+\n+\treturn (unsigned long)uboot_base;\n+}\n", "prefixes": [ "v7", "1/7" ] }